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annotate m68k_to_x86.c @ 184:ebcbdd1c4cc8

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Fix a bunch of bugs in the CPU core, add a 68K debugger
author Mike Pavone <pavone@retrodev.com>
date Sun, 13 Jan 2013 13:01:13 -0800
parents 2f08d9e90a4c
children 8e138da572ab
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1 #include "gen_x86.h"
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2 #include "m68k_to_x86.h"
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dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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3 #include "mem.h"
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4 #include <stdio.h>
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5 #include <stddef.h>
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6 #include <stdlib.h>
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7 #include <string.h>
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8
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9 #define BUS 4
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10 #define PREDEC_PENALTY 2
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11 #define CYCLES RAX
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12 #define LIMIT RBP
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13 #define SCRATCH1 RCX
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14 #define SCRATCH2 RDI
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15 #define CONTEXT RSI
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16
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17 #define FLAG_N RBX
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18 #define FLAG_V BH
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19 #define FLAG_Z RDX
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20 #define FLAG_C DH
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21
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22 typedef struct {
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23 int32_t disp;
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24 uint8_t mode;
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25 uint8_t base;
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26 uint8_t index;
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27 uint8_t cycles;
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28 } x86_ea;
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29
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6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
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30 char disasm_buf[1024];
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31
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32 void handle_cycle_limit_int();
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33 void m68k_read_word_scratch1();
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34 void m68k_read_long_scratch1();
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35 void m68k_read_byte_scratch1();
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36 void m68k_write_word();
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37 void m68k_write_long_lowfirst();
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38 void m68k_write_long_highfirst();
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39 void m68k_write_byte();
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40 void m68k_save_context();
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ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
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41 void m68k_load_context();
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42 void m68k_modified_ret_addr();
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43 void m68k_native_addr();
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44 void m68k_native_addr_and_sync();
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45 void m68k_trap();
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e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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46 void m68k_invalid();
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47 void set_sr();
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48 void set_ccr();
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49 void get_sr();
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3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
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50 void do_sync();
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51 void m68k_start_context(uint8_t * addr, m68k_context * context);
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52
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53 uint8_t * cycles(uint8_t * dst, uint32_t num)
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54 {
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55 dst = add_ir(dst, num, CYCLES, SZ_D);
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56 return dst;
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57 }
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59 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address)
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60 {
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61 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
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62 uint8_t * jmp_off = dst+1;
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63 dst = jcc(dst, CC_NC, dst + 7);
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64 dst = mov_ir(dst, address, SCRATCH1, SZ_D);
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65 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
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66 *jmp_off = dst - (jmp_off+1);
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67 return dst;
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68 }
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69
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70 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
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71 {
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72 if (op->addr_mode == MODE_REG) {
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73 return opts->dregs[op->params.regs.pri];
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74 }
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75 if (op->addr_mode == MODE_AREG) {
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76 return opts->aregs[op->params.regs.pri];
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77 }
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78 return -1;
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79 }
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81 //must be called with an m68k_op_info that uses a register
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82 size_t reg_offset(m68k_op_info *op)
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83 {
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84 if (op->addr_mode == MODE_REG) {
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85 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
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86 }
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87 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
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88 }
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89
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90 void print_regs_exit(m68k_context * context)
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91 {
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937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
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92 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
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93 for (int i = 0; i < 8; i++) {
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94 printf("d%d: %X\n", i, context->dregs[i]);
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95 }
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96 for (int i = 0; i < 8; i++) {
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97 printf("a%d: %X\n", i, context->aregs[i]);
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98 }
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99 exit(0);
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100 }
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101
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102 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
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103 {
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104 int8_t reg = native_reg(&(inst->src), opts);
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6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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105 uint8_t sec_reg;
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106 int32_t dec_amount,inc_amount;
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107 if (reg >= 0) {
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108 ea->mode = MODE_REG_DIRECT;
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109 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
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110 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D);
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111 ea->base = SCRATCH1;
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112 } else {
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113 ea->base = reg;
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114 }
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115 return out;
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116 }
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117 switch (inst->src.addr_mode)
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118 {
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119 case MODE_REG:
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120 case MODE_AREG:
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121 //We only get one memory parameter, so if the dst operand is a register in memory,
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diff changeset
122 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
123 reg = native_reg(&(inst->dst), opts);
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
124 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG)
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
125 || inst->op == M68K_EXG) {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
126
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
127 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
128 ea->base = CONTEXT;
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
129 ea->disp = reg_offset(&(inst->src));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
130 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
131 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
132 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
133 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
134 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
135 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
136 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
137 ea->base = SCRATCH1;
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
138 //we're explicitly handling the areg dest here, so we exit immediately
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
139 return out;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
140 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
141 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
142 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
143 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
144 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
145 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
158
a2ab895d9708 Fix predec address mode when used as source
Mike Pavone <pavone@retrodev.com>
parents: 157
diff changeset
146 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
147 } else {
158
a2ab895d9708 Fix predec address mode when used as source
Mike Pavone <pavone@retrodev.com>
parents: 157
diff changeset
148 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
149 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
150 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
151 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
152 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
153 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
154 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
155 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
156 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
157 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
158 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
159 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
160 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
161 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
162 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
163 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
164 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
165 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
166 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
167 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
168 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
169
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
170 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
183
2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents: 182
diff changeset
171 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
172 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
173 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
174 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
175 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
176 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
177 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
178 ea->mode = MODE_REG_DIRECT;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
179 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
180 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
181 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
182 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
183 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
184 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
185 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
186 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
187 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
188 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
189 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
190 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
191 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
192 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
193 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
194 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
195 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
196 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
197 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
198 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
199 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
200 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
201 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
202 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
203 break;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
204 case MODE_AREG_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
205 out = cycles(out, 6);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
206 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
207 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
208 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
209 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
210 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
211 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
212 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
213 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
214 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
215 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
216 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
217 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
218 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
219 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
220 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
221 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
222 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
223 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
224 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
225 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
226 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
227 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
228 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
229 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
230 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
231 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
232 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
233 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
234 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
235 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
236 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
237 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
238 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
239 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
240 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
241 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
242 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
243 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
244 }
97
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
245 switch (inst->extra.size)
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
246 {
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
247 case OPSIZE_BYTE:
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
248 out = call(out, (char *)m68k_read_byte_scratch1);
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
249 break;
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
250 case OPSIZE_WORD:
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
251 out = call(out, (char *)m68k_read_word_scratch1);
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
252 break;
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
253 case OPSIZE_LONG:
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
254 out = call(out, (char *)m68k_read_long_scratch1);
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
255 break;
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
256 }
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
257 ea->mode = MODE_REG_DIRECT;
c7185fd840fc Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents: 96
diff changeset
258 ea->base = SCRATCH1;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
259 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
260 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
261 out = cycles(out, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
262 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
263 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
264 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
265 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
266 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
267 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
268 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
269 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
270 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
271 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
272 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
273 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
274 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
275 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
276 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
277 break;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
278 case MODE_PC_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
279 out = cycles(out, 6);
96
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
280 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
281 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
282 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
283 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
284 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
285 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
286 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
287 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
288 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
289 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
290 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
291 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
292 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
293 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
294 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
295 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
296 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
297 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
298 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
299 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
300 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
301 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
302 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
303 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
304 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
305 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
306 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
307 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
308 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
309 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
310 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
311 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
312 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
313 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
314 }
96
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
315 switch (inst->extra.size)
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
316 {
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
317 case OPSIZE_BYTE:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
318 out = call(out, (char *)m68k_read_byte_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
319 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
320 case OPSIZE_WORD:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
321 out = call(out, (char *)m68k_read_word_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
322 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
323 case OPSIZE_LONG:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
324 out = call(out, (char *)m68k_read_long_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
325 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
326 }
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
327 ea->mode = MODE_REG_DIRECT;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
328 ea->base = SCRATCH1;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
329 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
330 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
331 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
332 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
333 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
334 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
335 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
336 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
337 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
338 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
339 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
340 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
341 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
342 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
343 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
344 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
345 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
346 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
347 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
348 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
349 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
350 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
351 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
352 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
353 case MODE_IMMEDIATE:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
354 case MODE_IMMEDIATE_WORD:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
355 if (inst->variant != VAR_QUICK) {
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
356 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
357 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
358 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
359 ea->disp = inst->src.params.immed;
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
360 return out;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
361 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
362 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
363 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
364 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
365 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
366 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
367 if (ea->mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
368 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
369 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
370 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
371 ea->mode = MODE_REG_DIRECT;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
372 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
373 ea->base = SCRATCH1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
374 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
375 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
376 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
377
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
378 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read)
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
379 {
98
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
380 int8_t reg = native_reg(&(inst->dst), opts), sec_reg;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
381 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
382 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
383 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
384 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
385 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
386 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
387 switch (inst->dst.addr_mode)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 case MODE_AREG:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
391 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
392 ea->base = CONTEXT;
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
393 ea->disp = reg_offset(&(inst->dst));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
394 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
395 case MODE_AREG_PREDEC:
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
396 if (inst->src.addr_mode == MODE_AREG_PREDEC) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
397 out = push_r(out, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
398 }
182
924af8b2f7a0 Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
399 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
400 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
401 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
402 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
403 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
404 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
405 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
406 case MODE_AREG_POSTINC:
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
407 if (fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
408 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
409 } else {
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
410 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
411 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
412 } else {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
413 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
414 }
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
415 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
416 {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
417 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
418 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
419 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
420 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
421 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
422 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
423 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
424 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
425 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
426 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
427 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
428 if (inst->src.addr_mode == MODE_AREG_PREDEC) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
429 //restore src operand to SCRATCH2
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
430 out =pop_r(out, SCRATCH2);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
431 } else {
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
432 //save reg value in SCRATCH2 so we can use it to save the result in memory later
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
433 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
434 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
435 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
436 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
437 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
438 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
439
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
440 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
441 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
442 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
443 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
444 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
445 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
446 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
447 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
448 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
449 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
450 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
451 case MODE_AREG_DISPLACE:
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
452 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
453 reg = fake_read ? SCRATCH2 : SCRATCH1;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
454 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
455 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
456 } else {
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
457 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
458 }
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
459 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
460 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
461 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
462 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
463 {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
464 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
465 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
466 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
467 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
468 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
469 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
470 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
471 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
472 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
473 }
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
474 out = pop_r(out, SCRATCH2);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
475 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
476 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
477 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
478 break;
98
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
479 case MODE_AREG_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
480 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
481 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
482 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
483 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
484 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
485 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
486 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
487 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
488 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
489 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
490 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
491 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
492 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
493 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
494 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
495 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
496 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
497 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
498 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
499 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
500 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
501 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
502 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
503 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
504 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
505 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
506 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
507 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
508 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
509 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
510 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
511 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
512 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
513 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
514 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
515 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
516 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
517 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
518 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
519 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
520 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
521 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
522 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
523 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
524 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
525 {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
526 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
527 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
528 break;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
529 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
530 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
531 break;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
532 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
533 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
534 break;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
535 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
536 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
537 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
538 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
539 ea->base = SCRATCH1;
161
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
540 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
541 case MODE_PC_DISPLACE:
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
542 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
543 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
544 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
545 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
546 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
547 {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
548 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
549 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
550 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
551 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
552 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
553 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
554 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
555 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
556 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
557 }
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
558 out = pop_r(out, SCRATCH2);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
559 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
560 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
561 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
562 break;
98
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
563 case MODE_PC_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
564 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
565 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
566 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
567 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
568 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
569 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
570 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
571 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
572 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
573 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
574 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
575 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
576 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
577 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
578 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
579 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
580 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
581 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
582 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
583 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
584 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
585 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
586 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
587 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
588 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
589 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
590 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
591 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
592 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
593 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
594 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
595 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
596 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
597 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
598 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
599 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
600 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
601 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
602 } else {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
603 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
604 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
605 {
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
606 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
607 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
608 break;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
609 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
610 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
611 break;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
612 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
613 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
614 break;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
615 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
616 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
617 }
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
618 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
619 ea->base = SCRATCH1;
104e257fb93c Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents: 97
diff changeset
620 break;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
621 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
622 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
623 //Add cycles for reading address from instruction stream
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
624 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0));
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
625 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
626 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
627 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
628 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
629 {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
630 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
631 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
632 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
633 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
634 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
635 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
636 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
637 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
638 break;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
639 }
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
640 out = pop_r(out, SCRATCH2);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
641 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
642 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
643 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
644 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
645 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
646 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
647 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
648 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
649 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
650 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
651 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
652
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
653 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
654 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
655 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
656 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
657 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
658 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
659 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
660 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
661 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
662 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
663 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
664 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
665 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
666 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
667 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
668 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
669 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
670 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
671 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
672 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
673 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
674 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
675 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
676 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
677 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
678
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
679 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
680 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
681 address &= 0xFFFFFF;
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
682 if (address > 0x400000) {
86
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
683 printf("get_native_address: %X\n", address);
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
684 }
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
685 address /= 2;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
686 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
687 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
688 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
689 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
690 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
691 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
692 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
693 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
694 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
695 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
696
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
697 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
698 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
699 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
700 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
701 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
702 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
703 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
704 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
705
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
706 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
707 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
708 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
709 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
710 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
711 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
712 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
713 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
714 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
715 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
716 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
717 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
718 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
719 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
720 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
721 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
722 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
723 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
724 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
725 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
726 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
727 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
728 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
729 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
730 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
731 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
732
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
733 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
734 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
735 address &= 0xFFFFFF;
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
736 address/= 2;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
737 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
738 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
739 native_code_map[chunk].base = native_addr;
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
740 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
741 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
742 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
743 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
744 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
745 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
746
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
747 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
748 {
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
749 int8_t reg, flags_reg, sec_reg;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
750 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
751 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
752 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
753 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
754 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
755 reg = native_reg(&(inst->dst), opts);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
756 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
757 //update statically set flags
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
758 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
759 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
760 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
761
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
762 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
763 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
764 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
765 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
766 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
767 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
768 if(src.mode == MODE_REG_DISPLACE8) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
769 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
770 } else {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
771 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
772 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
773 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
774 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
775 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
776 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
777 uint8_t size = inst->extra.size;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
778 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
779 {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
780 case MODE_AREG:
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
781 size = OPSIZE_LONG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
782 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
783 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
784 if (src.mode == MODE_REG_DIRECT) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
785 dst = mov_rr(dst, src.base, reg, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
786 } else if (src.mode == MODE_REG_DISPLACE8) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
787 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
788 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
789 dst = mov_ir(dst, src.disp, reg, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
790 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
791 } else if(src.mode == MODE_REG_DIRECT) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
792 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
793 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
794 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
795 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
796 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
797 dst = cmp_ir(dst, 0, flags_reg, size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
798 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
799 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
800 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
801 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
802 case MODE_AREG_PREDEC:
182
924af8b2f7a0 Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
803 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
804 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
805 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
806 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
807 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
808 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
809 case MODE_AREG_INDIRECT:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
810 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
811 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
812 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
813 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
814 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
815 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
816 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
817 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
818 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
819 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
820 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
821 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
822 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
823 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
824 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
825 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
826 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
827 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
828 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
829 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
830 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
831 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
832 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
833 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
834 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
835 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
836 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
837 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
838 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
839 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
840 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
841 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
842 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
843 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
844 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
845 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
846 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
847 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
848 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
849 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
850 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
851 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
852 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
853 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
854 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
855 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
856 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
857 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
858 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
859 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
860 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
861 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
862 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
863 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
864 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
865 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
866 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
867 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
868 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
869 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
870 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
871 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
872 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
873 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
874 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
875 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
876 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
877 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
878 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
879 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
880 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
881 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
882 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
883 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
884 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
885 break;
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
886 case MODE_AREG_INDEX_DISP8:
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
887 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
107
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
888 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
889 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
890 } else {
107
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
891 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
892 }
107
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
893 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
894 if (inst->dst.params.regs.sec & 1) {
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
895 if (inst->dst.params.regs.sec & 0x10) {
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
896 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
897 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
898 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
899 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
900 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
901 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
902 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
903 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
904 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
905 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
906 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
907 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
908 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
909 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
910 dst = push_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
911 }
107
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
912 if (inst->dst.params.regs.sec & 0x10) {
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
913 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
914 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
915 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
916 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
917 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
918 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
919 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
920 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
921 } else {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
922 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
923 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
924 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
925 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
926 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
927 dst = pop_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
928 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
929 }
107
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
930 if (inst->dst.params.regs.displacement) {
9705075fcf36 Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents: 106
diff changeset
931 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
932 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
933 if (src.mode == MODE_REG_DIRECT) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
934 if (src.base != SCRATCH1) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
935 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
936 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
937 } else if (src.mode == MODE_REG_DISPLACE8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
938 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
939 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
940 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
941 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
942 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
943 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
944 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
945 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
946 }
99
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
947 switch (inst->extra.size)
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
948 {
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
949 case OPSIZE_BYTE:
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
950 dst = call(dst, (char *)m68k_write_byte);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
951 break;
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
952 case OPSIZE_WORD:
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
953 dst = call(dst, (char *)m68k_write_word);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
954 break;
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
955 case OPSIZE_LONG:
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
956 dst = call(dst, (char *)m68k_write_long_highfirst);
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
957 break;
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
958 }
8491de5d6c06 Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents: 98
diff changeset
959 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
960 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
961 dst = cycles(dst, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
962 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
963 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
964 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
965 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
966 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
967 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
968 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
969 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
970 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
971 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
972 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
973 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
974 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
975 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
976 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
977 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
978 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
979 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
980 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
981 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
982 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
983 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
984 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
985 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
986 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
987 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
988 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
989 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
990 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
991 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
992 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
993 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
994 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
995 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
996 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
997 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
998 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
999 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1000 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1001 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1002 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1003 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1004 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1005 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1006 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1007 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1008 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1009 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1010 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1011 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1012 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1013 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1014 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1015 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1016 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1017 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1018 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1019 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1020 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1021 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1022 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1023 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
1024 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1025 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1026 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1027 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1028 exit(1);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1029 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1030
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1031 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1032 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1033 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1034 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1035
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1036 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1037 {
161
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1038 int8_t bit,reg,sec_reg;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1039 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1040 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1041 //reg to mem
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1042 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1043 int8_t dir;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1044 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1045 reg = 15;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1046 dir = -1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1047 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1048 reg = 0;
159
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents: 158
diff changeset
1049 dir = 1;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1050 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1051 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1052 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1053 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1054 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1055 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1056 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1057 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1058 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1059 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1060 break;
161
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1061 case MODE_AREG_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1062 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1063 reg = SCRATCH2;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1064 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1065 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1066 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1067 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1068 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1069 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1070 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1071 case MODE_AREG_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1072 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1073 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1074 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1075 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1076 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1077 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1078 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1079 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1080 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1081 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1082 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1083 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1084 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1085 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1086 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1087 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1088 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1089 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1090 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1091 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1092 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1093 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1094 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1095 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1096 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1097 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1098 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1099 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1100 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1101 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1102 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1103 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1104 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1105 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1106 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1107 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1108 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1109 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1110 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1111 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1112 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1113 case MODE_PC_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1114 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1115 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1116 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1117 case MODE_PC_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1118 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1119 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1120 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1121 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1122 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1123 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1124 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1125 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1126 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1127 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1128 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1129 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1130 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1131 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1132 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1133 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1134 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1135 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1136 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1137 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1138 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1139 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1140 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1141 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1142 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1143 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1144 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1145 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1146 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1147 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1148 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1149 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1150 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1151 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1152 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1153 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents: 159
diff changeset
1154 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1155 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1156 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1157 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1158 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1159 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1160 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1161 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1162 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1163 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1164 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1165 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1166 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1167 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1168 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1169 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1170 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1171 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1172 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1173 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1174 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1175 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1176 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1177 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1178 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1179 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1180 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1181 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1182 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1183 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1184 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1185 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1186 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1187 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1188 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1189 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1190 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1191 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1192 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1193 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1194 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1195 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1196 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1197 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1198 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1199 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1200 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1201 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1202 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1203 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1204 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1205 //mem to reg
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1206 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1207 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1208 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1209 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1210 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1211 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1212 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1213 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1214 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1215 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1216 break;
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1217 case MODE_AREG_DISPLACE:
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1218 early_cycles += BUS;
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1219 reg = SCRATCH2;
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1220 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1221 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1222 } else {
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1223 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1224 }
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1225 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1226 break;
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1227 case MODE_AREG_INDEX_DISP8:
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1228 early_cycles += 6;
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1229 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1230 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1231 } else {
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1232 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1233 }
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1234 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1235 if (inst->src.params.regs.sec & 1) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1236 if (inst->src.params.regs.sec & 0x10) {
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1237 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1238 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1239 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1240 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1241 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1242 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1243 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1244 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1245 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1246 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1247 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1248 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1249 } else {
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1250 if (inst->src.params.regs.sec & 0x10) {
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1251 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1252 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1253 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1254 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1255 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1256 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1257 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1258 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1259 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1260 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1261 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1262 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1263 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1264 }
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1265 if (inst->src.params.regs.displacement) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1266 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1267 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1268 break;
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1269 case MODE_PC_DISPLACE:
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1270 early_cycles += BUS;
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1271 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1272 break;
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1273 case MODE_PC_INDEX_DISP8:
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1274 early_cycles += 6;
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1275 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1276 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1277 if (inst->src.params.regs.sec & 1) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1278 if (inst->src.params.regs.sec & 0x10) {
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1279 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1280 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1281 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1282 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1283 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1284 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1285 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1286 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1287 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1288 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1289 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1290 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1291 } else {
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1292 if (inst->src.params.regs.sec & 0x10) {
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1293 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1294 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1295 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1296 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1297 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1298 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1299 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1300 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1301 } else {
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1302 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1303 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1304 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1305 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1306 }
169
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1307 if (inst->src.params.regs.displacement) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 168
diff changeset
1308 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1309 }
eba78ad49a11 Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents: 161
diff changeset
1310 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1311 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1312 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1313 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1314 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1315 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1316 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1317 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1318 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1319 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1320 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1321 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1322 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1323 for(reg = 0; reg < 16; reg ++) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
1324 if (inst->dst.params.immed & (1 << reg)) {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1325 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1326 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1327 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1328 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1329 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1330 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1331 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1332 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1333 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1334 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1335 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1336 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1337 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1338 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1339 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1340 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1341 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1342 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1343 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1344 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1345 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1346 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1347 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1348 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1349 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
1350 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1351 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
1352 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1353 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1354 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1355 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1356 //prefetch
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1357 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1358 return dst;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1359 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1360
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1361 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1362 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1363 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1364 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1365 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1366 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1367 int8_t reg = native_reg(&(inst->dst), opts);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1368 if (reg >= 0) {
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1369 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1370 return xor_rr(dst, reg, reg, inst->extra.size);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1371 }
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1372 x86_ea dst_op;
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1373 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1374 if (dst_op.mode == MODE_REG_DIRECT) {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1375 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size);
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1376 } else {
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1377 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1378 }
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1379 dst = m68k_save_result(inst, dst, opts);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1380 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1381 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1382
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1383 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1384 {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1385 x86_ea dst_op;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1386 uint8_t dst_size = inst->extra.size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1387 inst->extra.size--;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1388 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1389 if (dst_op.mode == MODE_REG_DIRECT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1390 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1391 dst = cmp_ir(dst, 0, dst_op.base, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1392 } else {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1393 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1394 dst = cmp_ir(dst, 0, SCRATCH1, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1395 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1396 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1397 inst->extra.size = dst_size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1398 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1399 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1400 dst = setcc_r(dst, CC_Z, FLAG_Z);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1401 dst = setcc_r(dst, CC_S, FLAG_N);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1402 //M68K EXT only operates on registers so no need for a call to save result here
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1403 return dst;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1404 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
1405
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1406 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1407 {
100
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1408 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1409 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1410 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1411 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1412 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1413 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1414 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1415 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1416 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1417 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1418 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1419 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1420 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1421 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1422 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1423 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1424 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1425 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1426 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1427 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1428 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1429 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1430 if (dst_reg >= 0) {
168
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1431 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1432 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1433 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1434 } else {
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1435 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1436 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1437 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1438 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1439 } else {
168
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1440 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1441 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1442 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1443 } else {
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1444 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1445 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1446 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1447 }
165
62b152811bae Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents: 162
diff changeset
1448 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1449 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1450 break;
100
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1451 case MODE_AREG_INDEX_DISP8:
168
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1452 dst = cycles(dst, 12);
100
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1453 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1454 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1455 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1456 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1457 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1458 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1459 if (inst->src.params.regs.sec & 1) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1460 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1461 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1462 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1463 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1464 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1465 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1466 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1467 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1468 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1469 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1470 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1471 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1472 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1473 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1474 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1475 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1476 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1477 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1478 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1479 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1480 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1481 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1482 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1483 } else {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1484 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1485 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1486 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1487 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1488 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1489 if (inst->src.params.regs.displacement) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1490 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1491 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1492 if (dst_reg >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1493 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1494 } else {
165
62b152811bae Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents: 162
diff changeset
1495 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
100
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1496 }
45cd7d3e7918 Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents: 99
diff changeset
1497 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1498 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1499 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1500 if (dst_reg >= 0) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
1501 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1502 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
1503 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1504 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1505 break;
133
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1506 case MODE_PC_INDEX_DISP8:
168
7b099f2b382b Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents: 167
diff changeset
1507 dst = cycles(dst, BUS*3);
133
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1508 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1509 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1510 if (inst->src.params.regs.sec & 1) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1511 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1512 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1513 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1514 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1515 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1516 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1517 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1518 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1519 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1520 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1521 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1522 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1523 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1524 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1525 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1526 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1527 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1528 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1529 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1530 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1531 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1532 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1533 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1534 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1535 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1536 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1537 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1538 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1539 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1540 if (inst->src.params.regs.displacement) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1541 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1542 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1543 if (dst_reg >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1544 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1545 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1546 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1547 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1548 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1549 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1550 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1551 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1552 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1553 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1554 } else {
133
c4d10c2aaee2 Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents: 132
diff changeset
1555 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1556 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1557 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1558 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1559 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1560 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1561 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1562 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1563 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1564 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1565
116
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1566 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1567 {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1568 uint8_t sec_reg;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1569 switch(inst->src.addr_mode)
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1570 {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1571 case MODE_AREG_INDIRECT:
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1572 dst = cycles(dst, BUS);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1573 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1574 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1575 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1576 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1577 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1578 break;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1579 case MODE_AREG_DISPLACE:
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1580 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1581 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1582 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1583 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1584 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1585 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1586 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1587 break;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1588 case MODE_AREG_INDEX_DISP8:
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1589 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1590 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1591 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1592 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1593 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1594 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1595 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1596 if (inst->src.params.regs.sec & 1) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1597 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1598 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1599 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1600 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1601 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1602 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1603 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1604 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1605 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1606 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1607 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1608 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1609 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1610 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1611 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1612 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1613 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1614 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1615 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1616 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1617 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1618 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1619 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1620 } else {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1621 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1622 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1623 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1624 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1625 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1626 if (inst->src.params.regs.displacement) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1627 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1628 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1629 break;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1630 case MODE_PC_DISPLACE:
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1631 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1632 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1633 break;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1634 case MODE_ABSOLUTE:
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1635 case MODE_ABSOLUTE_SHORT:
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1636 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1637 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1638 break;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1639 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1640 m68k_disasm(inst, disasm_buf);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1641 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
116
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1642 exit(1);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1643 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1644 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1645 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1646 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1647 return dst;
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1648 }
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
1649
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1650 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1651 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1652 int32_t disp = inst->src.params.immed;
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1653 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1654 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1655 dst = cycles(dst, 10);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1656 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1657 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1658 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1659 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1660 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1661 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1662 dst = call(dst, (char *)m68k_write_long_highfirst);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1663 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1664 if (!dest_addr) {
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
1665 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1666 //dummy address to be replaced later
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1667 dest_addr = dst + 256;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1668 }
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1669 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1670 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1671 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1672 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1673 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1674 dst = jmp(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1675 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1676 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1677 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1678
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1679 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1680 {
156
3900cfde9dbb Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Mike Pavone <pavone@retrodev.com>
parents: 155
diff changeset
1681 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1682 int32_t disp = inst->src.params.immed;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1683 uint32_t after = inst->address + 2;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1684 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1685 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1686 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1687 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1688 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1689 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1690 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1691 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1692 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1693 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1694 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1695 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1696 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1697 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1698 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1699 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1700 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1701 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1702 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1703 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1704 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1705 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1706 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1707 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1708 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1709 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1710 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1711 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1712 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1713 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1714 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1715 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1716 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1717 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1718 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1719 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1720 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1721 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1722 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1723 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1724 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1725 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1726 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1727 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1728 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1729 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1730 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1731 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1732 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1733 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1734 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1735 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1736 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1737 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1738 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1739 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1740 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1741 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1742 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1743 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1744
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1745 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1746 {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1747 uint8_t cond = inst->extra.cond;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1748 x86_ea dst_op;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1749 inst->extra.size = OPSIZE_BYTE;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1750 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1751 if (cond == COND_TRUE || cond == COND_FALSE) {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1752 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1753 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1754 } else {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1755 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1756 }
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1757 if (dst_op.mode == MODE_REG_DIRECT) {
179
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1758 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1759 } else {
179
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1760 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1761 }
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1762 } else {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1763 uint8_t cc = CC_NZ;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1764 switch (cond)
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1765 {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1766 case COND_HIGH:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1767 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1768 case COND_LOW_SAME:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1769 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1770 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1771 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1772 case COND_CARRY_CLR:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1773 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1774 case COND_CARRY_SET:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1775 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1776 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1777 case COND_NOT_EQ:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1778 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1779 case COND_EQ:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1780 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1781 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1782 case COND_OVERF_CLR:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1783 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1784 case COND_OVERF_SET:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1785 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1786 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1787 case COND_PLUS:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1788 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1789 case COND_MINUS:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1790 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1791 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1792 case COND_GREATER_EQ:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1793 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1794 case COND_LESS:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1795 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1796 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1797 case COND_GREATER:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1798 cc = CC_Z;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1799 case COND_LESS_EQ:
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1800 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1801 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1802 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1803 break;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1804 }
179
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1805 uint8_t *true_off = dst + 1;
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1806 dst = jcc(dst, cc, dst+2);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1807 dst = cycles(dst, BUS);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1808 if (dst_op.mode == MODE_REG_DIRECT) {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1809 dst = mov_ir(dst, 0, dst_op.base, SZ_B);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1810 } else {
179
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1811 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1812 }
179
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1813 uint8_t *end_off = dst+1;
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1814 dst = jmp(dst, dst+2);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1815 *true_off = dst - (true_off+1);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1816 dst = cycles(dst, 6);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1817 if (dst_op.mode == MODE_REG_DIRECT) {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1818 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1819 } else {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1820 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1821 }
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents: 178
diff changeset
1822 *end_off = dst - (end_off+1);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1823 }
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1824 dst = m68k_save_result(inst, dst, opts);
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1825 return dst;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1826 }
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
1827
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1828 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1829 {
132
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1830 uint8_t * dest_addr, sec_reg;
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1831 uint32_t m68k_addr;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1832 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1833 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1834 case MODE_AREG_INDIRECT:
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1835 dst = cycles(dst, BUS*2);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1836 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1837 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1838 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1839 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1840 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1841 dst = call(dst, (uint8_t *)m68k_native_addr);
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
1842 dst = jmp_r(dst, SCRATCH1);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1843 break;
132
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1844 case MODE_AREG_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1845 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1846 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1847 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1848 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1849 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1850 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1851 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1852 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1853 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1854 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1855 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1856 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1857 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1858 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1859 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1860 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1861 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1862 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1863 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1864 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1865 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1866 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1867 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1868 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1869 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1870 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1871 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1872 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1873 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1874 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1875 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1876 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1877 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1878 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1879 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1880 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1881 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1882 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1883 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1884 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1885 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1886 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1887 break;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1888 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1889 dst = cycles(dst, 10);
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1890 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1891 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1892 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1893 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1894 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1895 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1896 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1897 }
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1898 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1899 } else {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1900 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1901 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1902 dst = jmp_r(dst, SCRATCH1);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1903 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1904 break;
132
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1905 case MODE_PC_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1906 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1907 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1908 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1909 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1910 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1911 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1912 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1913 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1914 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1915 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1916 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1917 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1918 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1919 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1920 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1921 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1922 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1923 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1924 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1925 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1926 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1927 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1928 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1929 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1930 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1931 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1932 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1933 } else {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1934 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1935 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1936 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1937 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1938 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1939 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1940 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1941 }
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1942 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1943 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents: 129
diff changeset
1944 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1945 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1946 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1947 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1948 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1949 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1950 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1951 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1952 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1953 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1954 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1955 }
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1956 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1957 } else {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1958 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1959 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1960 dst = jmp_r(dst, SCRATCH1);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1961 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1962 break;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1963 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1964 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
1965 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode);
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 102
diff changeset
1966 exit(1);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1967 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1968 return dst;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1969 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1970
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1971 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1972 {
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
1973 uint8_t * dest_addr, sec_reg;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1974 uint32_t after;
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1975 uint32_t m68k_addr;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1976 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1977 {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1978 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1979 dst = cycles(dst, BUS*2);
119
ee19ddadb398 Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents: 118
diff changeset
1980 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1981 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1982 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1983 }
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
1984 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
1985 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 78
diff changeset
1986 dst = call(dst, (char *)m68k_write_long_highfirst);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1987 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1988 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1989 } else {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1990 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1991 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1992 dst = call(dst, (uint8_t *)m68k_native_addr);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1993 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1994 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1995 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1996 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1997 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1998 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
1999 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2000 break;
174
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2001 case MODE_AREG_DISPLACE:
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2002 dst = cycles(dst, BUS*2);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2003 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2004 if (opts->flags & OPT_NATIVE_CALL_STACK) {
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2005 dst = push_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2006 }
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2007 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2008 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2009 dst = call(dst, (char *)m68k_write_long_highfirst);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2010 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2011 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2012 } else {
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2013 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2014 }
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2015 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2016 dst = call(dst, (uint8_t *)m68k_native_addr);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2017 if (opts->flags & OPT_NATIVE_CALL_STACK) {
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2018 dst = call_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2019 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2020 dst = pop_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2021 } else {
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2022 dst = jmp_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2023 }
a1c3ecb4823f Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents: 173
diff changeset
2024 break;
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2025 case MODE_AREG_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2026 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119
ee19ddadb398 Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents: 118
diff changeset
2027 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2028 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2029 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2030 }
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2031 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2032 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2033 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2034 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2035 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2036 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2037 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2038 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2039 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2040 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2041 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2042 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2043 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2044 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2045 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2046 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2047 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2048 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2049 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2050 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2051 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2052 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2053 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2054 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2055 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2056 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2057 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2058 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2059 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2060 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2061 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2062 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2063 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2064 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2065 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2066 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2067 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2068 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2069 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2070 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2071 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2072 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2073 dst = call(dst, (uint8_t *)m68k_native_addr);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2074 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2075 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2076 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2077 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2078 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2079 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2080 }
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2081 break;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2082 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2083 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2084 dst = cycles(dst, 10);
119
ee19ddadb398 Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents: 118
diff changeset
2085 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2086 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2087 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2088 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2089 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2090 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2091 dst = call(dst, (char *)m68k_write_long_highfirst);
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2092 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2093 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2094 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2095 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2096 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2097 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2098 dest_addr = dst + 256;
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2099 }
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2100 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2101 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2102 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2103 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2104 }
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2105 } else {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2106 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2107 dst = call(dst, (uint8_t *)m68k_native_addr);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2108 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2109 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2110 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2111 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2112 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2113 }
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2114 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2115 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2116 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2117 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2118 break;
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2119 case MODE_PC_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2120 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119
ee19ddadb398 Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents: 118
diff changeset
2121 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2122 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2123 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2124 }
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2125 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2126 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2127 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2128 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2129 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2130 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2131 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2132 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2133 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2134 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2135 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2136 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2137 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2138 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2139 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2140 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2141 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2142 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2143 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2144 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2145 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2146 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2147 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2148 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2149 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2150 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2151 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2152 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2153 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2154 } else {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2155 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2156 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2157 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2158 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2159 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2160 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2161 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2162 }
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2163 dst = call(dst, (uint8_t *)m68k_native_addr);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2164 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2165 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2166 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2167 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2168 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2169 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2170 }
110
a575808dd90b Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents: 107
diff changeset
2171 break;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2172 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2173 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2174 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2175 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
119
ee19ddadb398 Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents: 118
diff changeset
2176 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2177 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2178 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2179 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2180 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2181 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2182 dst = call(dst, (char *)m68k_write_long_highfirst);
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2183 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2184 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2185 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2186 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2187 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2188 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2189 dest_addr = dst + 256;
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2190 }
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2191 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2192 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2193 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2194 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2195 }
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2196 } else {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2197 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
2198 dst = call(dst, (uint8_t *)m68k_native_addr);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2199 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2200 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2201 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2202 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2203 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2204 }
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2205 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2206 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2207 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2208 }
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2209 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2210 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2211 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2212 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode);
105
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
2213 exit(1);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2214 }
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
2215 return dst;
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
2216 }
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
2217
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2218 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2219 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2220 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2221 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2222 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2223 dst = call(dst, (char *)m68k_read_long_scratch1);
155
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2224 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2225 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2226 dst = jcc(dst, CC_NZ, dst+3);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2227 dst = retn(dst);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2228 dst = jmp(dst, (char *)m68k_modified_ret_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2229 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2230 dst = call(dst, (uint8_t *)m68k_native_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2231 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
2232 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2233 return dst;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2234 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2235
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2236 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2237 {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2238 //best case duration
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2239 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2240 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2241 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2242 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2243 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2244 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2245 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2246 {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2247 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2248 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2249 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2250 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2251 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2252 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2253 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2254 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2255 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2256 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2257 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2258 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2259 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2260 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2261 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2262 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2263 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2264 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2265 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2266 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2267 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2268 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2269 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2270 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2271 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2272 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2273 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2274 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2275 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2276 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2277 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2278 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2279 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2280 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2281 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2282 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2283 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2284 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2285 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2286 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2287 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2288 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2289 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2290 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2291 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2292 } else {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2293 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2294 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2295 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2296 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2297 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2298 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2299 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2300 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2301 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2302 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2303 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2304 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2305 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2306 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2307 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2308 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2309 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2310 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2311 } else {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2312 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2313 }
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2314 return dst;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2315 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2316
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2317 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2318 {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2319 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2320 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2321 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2322 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2323 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2324 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2325 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2326 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2327 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2328 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2329 dst = call(dst, (char *)m68k_write_long_highfirst);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2330 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2331 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2332 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2333 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2334 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2335 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2336 //prefetch
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2337 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2338 return dst;
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2339 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2340
172
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2341 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2342 {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2343 int8_t reg;
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2344 dst = cycles(dst, BUS*2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2345 if (inst->src.addr_mode == MODE_REG) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2346 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2347 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2348 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2349 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2350 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2351 if (inst->dst.params.regs.displacement) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2352 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2353 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2354 reg = native_reg(&(inst->src), opts);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2355 if (inst->extra.size == OPSIZE_LONG) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2356 if (reg >= 0) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2357 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2358 dst = shr_ir(dst, 24, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2359 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2360 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2361 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2362 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2363 dst = shr_ir(dst, 16, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2364
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2365 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2366 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2367 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2368 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2369 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2370 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2371 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2372 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2373 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2374 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2375 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2376 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2377 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2378 if (reg >= 0) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2379 dst = mov_rr(dst, reg, SCRATCH1, SZ_W);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2380 dst = shr_ir(dst, 8, SCRATCH1, SZ_W);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2381 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2382 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2383 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2384 dst = mov_rr(dst, reg, SCRATCH1, SZ_W);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2385 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2386 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2387 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2388 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2389 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2390 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2391 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2392 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2393 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2394 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2395 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2396 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2397 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2398 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2399 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2400 if (inst->src.params.regs.displacement) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2401 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2402 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2403 reg = native_reg(&(inst->dst), opts);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2404 if (inst->extra.size == OPSIZE_LONG) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2405 if (reg >= 0) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2406 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2407 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2408 dst = shl_ir(dst, 24, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2409 dst = mov_rr(dst, SCRATCH1, reg, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2410 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2411 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2412 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2413 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2414 dst = shl_ir(dst, 16, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2415 dst = or_rr(dst, SCRATCH1, reg, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2416 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2417 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2418 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2419 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2420 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2421 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2422 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2423 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2424 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2425 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2426 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2427 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2428 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2429 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2430 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2431 if (reg >= 0) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2432
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2433 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2434 dst = mov_rr(dst, SCRATCH1, reg, SZ_W);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2435 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2436 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2437 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2438 dst = mov_rr(dst, SCRATCH1, reg, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2439 } else {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2440 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2441 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2442 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2443 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2444 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B);
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2445 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2446 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2447 return dst;
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2448 }
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2449
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2450 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2451 {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2452 uint8_t size = inst->extra.size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2453 x86_ea src_op, dst_op;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2454 dst = translate_m68k_src(inst, &src_op, dst, opts);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2455 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2456 dst = push_r(dst, SCRATCH1);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2457 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2458 dst = pop_r(dst, SCRATCH2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2459 src_op.base = SCRATCH2;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2460 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2461 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2462 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2463 size = OPSIZE_LONG;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2464 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2465 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2466 dst = cycles(dst, BUS);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2467 if (src_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2468 if (dst_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2469 dst = cmp_rr(dst, src_op.base, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2470 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2471 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2472 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2473 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2474 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2475 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2476 if (dst_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2477 dst = cmp_ir(dst, src_op.disp, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2478 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2479 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2480 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2481 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2482 dst = setcc_r(dst, CC_C, FLAG_C);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2483 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2484 dst = setcc_r(dst, CC_S, FLAG_N);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2485 dst = setcc_r(dst, CC_O, FLAG_V);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2486 return dst;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2487 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2488
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2489 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2490 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2491 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2492 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2493
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2494 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2495 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2496 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2497 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2498 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2499 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2500 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2501 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2502 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2503 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2504 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2505 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2506 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2507 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2508 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2509 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2510 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2511 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2512 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2513 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2514 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2515 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2516 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2517 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2518 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2519 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2520 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2521 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2522 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2523 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2524 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2525 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2526 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2527 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2528 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2529 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2530
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2531 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2532 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2533 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2534 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2535 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2536 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2537 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2538 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2539 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2540 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2541 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2542 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2543 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2544 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2545 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2546 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2547 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2548 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2549 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2550 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2551 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2552 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2553 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2554 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2555 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2556 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2557
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2558 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2559 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2560 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2561 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2562 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2563 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2564 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2565 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2566 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2567
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2568 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2569
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2570 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2571 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2572 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2573 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2574 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2575 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2576 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2577 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2578 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2579 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2580 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2581 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2582 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2583 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2584 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2585 }
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
2586 return dst;
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2587 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2588
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2589 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2590
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2591 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2592 {
122
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
2593 uint8_t * end_off, *zero_off, *norm_off;
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2594 uint8_t dst_reg;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2595 map_native_address(opts->native_code_map, inst->address, dst);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
2596 dst = check_cycles_int(dst, inst->address);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2597 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2598 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2599 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2600 return translate_m68k_lea(dst, inst, opts);
116
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
2601 } else if(inst->op == M68K_PEA) {
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 113
diff changeset
2602 return translate_m68k_pea(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2603 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2604 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2605 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2606 return translate_m68k_bcc(dst, inst, opts);
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
2607 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
2608 return translate_m68k_jmp(dst, inst, opts);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2609 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
2610 return translate_m68k_jsr(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2611 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2612 return translate_m68k_rts(dst, inst, opts);
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2613 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
2614 return translate_m68k_dbcc(dst, inst, opts);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2615 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2616 return translate_m68k_clr(dst, inst, opts);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2617 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2618 return translate_m68k_movem(dst, inst, opts);
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2619 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
2620 return translate_m68k_link(dst, inst, opts);
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
2621 } else if(inst->op == M68K_EXT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
2622 return translate_m68k_ext(dst, inst, opts);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
2623 } else if(inst->op == M68K_SCC) {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 110
diff changeset
2624 return translate_m68k_scc(dst, inst, opts);
172
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2625 } else if(inst->op == M68K_MOVEP) {
c61507f897e4 Implement movep
Mike Pavone <pavone@retrodev.com>
parents: 171
diff changeset
2626 return translate_m68k_movep(dst, inst, opts);
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
2627 } else if(inst->op == M68K_INVALID) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
2628 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D);
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
2629 return call(dst, (uint8_t *)m68k_invalid);
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2630 } else if(inst->op == M68K_CMP) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2631 return translate_m68k_cmp(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2632 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2633 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2634 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2635 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2636 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2637 if (inst->dst.addr_mode != MODE_UNUSED) {
92
c3d034e076ee Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
2638 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2639 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2640 uint8_t size;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2641 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2642 {
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
2643 //case M68K_ABCD:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
2644 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2645 case M68K_ADD:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2646 dst = cycles(dst, BUS);
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2647 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2648 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2649 if (dst_op.mode == MODE_REG_DIRECT) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2650 dst = add_rr(dst, src_op.base, dst_op.base, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2651 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2652 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2653 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2654 } else if (src_op.mode == MODE_REG_DISPLACE8) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2655 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2656 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2657 if (dst_op.mode == MODE_REG_DIRECT) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2658 dst = add_ir(dst, src_op.disp, dst_op.base, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2659 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2660 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2661 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2662 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2663 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2664 dst = setcc_r(dst, CC_C, FLAG_C);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2665 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2666 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2667 dst = setcc_r(dst, CC_O, FLAG_V);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2668 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2669 }
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2670 dst = m68k_save_result(inst, dst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
2671 break;
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2672 case M68K_ADDX:
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2673 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2674 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2675 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2676 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2677 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2678 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2679 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2680 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2681 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2682 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2683 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2684 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2685 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2686 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2687 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2688 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2689 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2690 dst = setcc_r(dst, CC_C, FLAG_C);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2691 dst = jcc(dst, CC_Z, dst+4);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2692 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2693 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2694 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2695 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2696 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
2697 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2698 case M68K_AND:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2699 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2700 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2701 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2702 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2703 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2704 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2705 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2706 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2707 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2708 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2709 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2710 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2711 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2712 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2713 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2714 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2715 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2716 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2717 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2718 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2719 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2720 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2721 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2722 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2723 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2724 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2725 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2726 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2727 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2728 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2729 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2730 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2731 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2732 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2733 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2734 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2735 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2736 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2737 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2738 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2739 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2740 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2741 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2742 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2743 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2744 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2745 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2746 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2747 }
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
2748 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
2749 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
2750 }
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2751 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
2752 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2753 case M68K_ASL:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2754 case M68K_LSL:
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
2755 //TODO: Check overflow flag behavior
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2756 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2757 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2758 case M68K_ASR:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2759 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2760 break;
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2761 case M68K_LSR:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2762 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
2763 break;
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2764 case M68K_BCHG:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2765 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2766 case M68K_BSET:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2767 case M68K_BTST:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2768 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67
534eb4976423 Fix BTST
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
2769 if (src_op.mode == MODE_IMMED) {
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2770 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2771 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2772 }
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2773 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2774 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2775 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2776 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2777 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2778 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2779 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2780 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2781 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2782 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2783 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2784 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2785 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2786 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2787 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2788 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2789 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2790 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2791 } else {
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2792 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2793 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2794 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2795 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2796 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2797 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2798 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2799 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2800 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2801 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2802 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2803 src_op.base = SCRATCH2;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2804 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2805 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2806 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2807 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2808 }
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2809 if (dst_op.mode == MODE_REG_DISPLACE8) {
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2810 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) {
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2811 if (src_op.mode == MODE_REG_DIRECT) {
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2812 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2813 } else {
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2814 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2815 src_op.mode = MODE_REG_DIRECT;
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2816 }
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2817 src_op.base = SCRATCH1;
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2818 }
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2819 dst = and_ir(dst, 31, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
2820 }
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2821 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2822 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2823 dst = bt_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2824 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2825 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2826 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2827 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2828 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2829 dst = bts_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2830 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2831 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2832 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2833 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2834 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2835 dst = btr_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2836 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2837 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2838 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2839 } else {
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2840 if (dst_op.mode == MODE_REG_DIRECT) {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2841 dst = btc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2842 } else {
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2843 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 122
diff changeset
2844 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2845 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2846 if (src_op.base == SCRATCH2) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2847 dst = pop_r(dst, SCRATCH2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2848 }
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2849 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2850 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2851 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2852 dst = setcc_r(dst, CC_NC, FLAG_Z);
128
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2853 if (inst->op != M68K_BTST) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents: 126
diff changeset
2854 dst = m68k_save_result(inst, dst, opts);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2855 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
2856 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
2857 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
2858 break;*/
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2859 case M68K_DIVS:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2860 case M68K_DIVU:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2861 //TODO: Trap on division by zero
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2862 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2863 dst = push_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2864 dst = push_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2865 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2866 dst = mov_rr(dst, dst_op.base, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2867 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2868 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2869 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2870 if (src_op.mode == MODE_IMMED) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2871 dst = mov_ir(dst, src_op.disp, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2872 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2873 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2874 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2875 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2876 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2877 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2878 } else if (src_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2879 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2880 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2881 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2882 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2883 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2884 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2885 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2886 dst = cdq(dst);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2887 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2888 dst = xor_rr(dst, RDX, RDX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2889 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2890 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2891 dst = idiv_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2892 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2893 dst = div_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2894 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2895 dst = cmp_ir(dst, 0x10000, RAX, SZ_D);
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2896 if (inst->op == M68K_DIVS) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2897 uint8_t * skip_sec_check = dst + 1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2898 dst = jcc(dst, CC_C, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2899 dst = cmp_ir(dst, -0x10000, RAX, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2900 norm_off = dst+1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2901 dst = jcc(dst, CC_LE, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2902 *skip_sec_check = dst - (skip_sec_check+1);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2903 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2904 norm_off = dst+1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2905 dst = jcc(dst, CC_NC, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
2906 }
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2907 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2908 dst = mov_rr(dst, RDX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2909 dst = shl_ir(dst, 16, dst_op.base, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2910 dst = mov_rr(dst, RAX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2911 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2912 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2913 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2914 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2915 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2916 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2917 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2918 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2919 dst = cmp_ir(dst, 0, RAX, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2920 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2921 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2922 end_off = dst+1;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2923 dst = jmp(dst, dst+2);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2924 *norm_off = dst - (norm_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2925 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2926 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2927 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2928 *end_off = dst - (end_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2929 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
2930 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2931 case M68K_EOR:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2932 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2933 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2934 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2935 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2936 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2937 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2938 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2939 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2940 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2941 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2942 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2943 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2944 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2945 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2946 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2947 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2948 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2949 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2950 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2951 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2952 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2953 break;
171
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2954 case M68K_EORI_CCR:
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2955 case M68K_EORI_SR:
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2956 dst = cycles(dst, 20);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2957 //TODO: If ANDI to SR, trap if not in supervisor mode
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2958 if (inst->src.params.immed & 0x1) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2959 dst = xor_ir(dst, 1, FLAG_C, SZ_B);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2960 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2961 if (inst->src.params.immed & 0x2) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2962 dst = xor_ir(dst, 1, FLAG_V, SZ_B);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2963 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2964 if (inst->src.params.immed & 0x4) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2965 dst = xor_ir(dst, 1, FLAG_Z, SZ_B);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2966 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2967 if (inst->src.params.immed & 0x8) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2968 dst = xor_ir(dst, 1, FLAG_N, SZ_B);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2969 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2970 if (inst->src.params.immed & 0x10) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2971 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2972 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2973 if (inst->op == M68K_ORI_SR) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2974 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2975 if (inst->src.params.immed & 0x700) {
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2976 dst = call(dst, (uint8_t *)do_sync);
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2977 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2978 }
f03db3db48fb Implement EORI CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 170
diff changeset
2979 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2980 case M68K_EXG:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2981 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2982 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2983 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2984 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2985 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2986 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2987 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2988 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2989 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2990 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2991 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2992 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2993 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2994 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2995 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2996 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2997 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2998 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
2999 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3000 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3001 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3002 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3003 case M68K_ILLEGAL:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3004 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3005 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3006 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3007 break;
105
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3008 case M68K_MOVE_FROM_SR:
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3009 //TODO: Trap if not in system mode
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3010 dst = call(dst, (uint8_t *)get_sr);
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3011 if (dst_op.mode == MODE_REG_DIRECT) {
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3012 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W);
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3013 } else {
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3014 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W);
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3015 }
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3016 dst = m68k_save_result(inst, dst, opts);
1a0fd122ca8f Implemented move from SR
Mike Pavone <pavone@retrodev.com>
parents: 104
diff changeset
3017 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3018 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3019 case M68K_MOVE_SR:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3020 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3021 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3022 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3023 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3024 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3025 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3026 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3027 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3028 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3029 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3030 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3031 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3032 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3033 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3034 }
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3035 dst = call(dst, (uint8_t *)do_sync);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3036 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3037 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3038 } else {
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3039 if (src_op.base != SCRATCH1) {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3040 if (src_op.mode == MODE_REG_DIRECT) {
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3041 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3042 } else {
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3043 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3044 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3045 }
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3046 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr));
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3047 dst = cycles(dst, 12);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3048
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3049 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3050 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3051 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3052 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3053 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3054 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3055 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3056 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3057 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3058 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3059 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3060 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3061 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3062 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3063 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3064 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3065 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3066 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3067 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3068 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3069 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
3070 break;
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3071 //case M68K_MOVEP:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3072 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3073 case M68K_MULU:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3074 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3075 if (src_op.mode == MODE_IMMED) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3076 //immediate value should already be sign extended to 32-bits
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3077 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : src_op.disp, SCRATCH1, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3078 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3079 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3080 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3081 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3082 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3083 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3084 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3085 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3086 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3087 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3088 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3089 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3090 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3091 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3092 dst_reg = dst_op.base;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3093 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3094 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3095 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3096 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3097 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3098 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3099 dst_reg = SCRATCH2;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3100 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3101 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3102 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3103 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3104 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3105 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3106 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3107 if (dst_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3108 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3109 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3110 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3111 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3112 dst = cmp_ir(dst, 0, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3113 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3114 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3115 break;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3116 //case M68K_NBCD:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3117 case M68K_NEG:
173
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3118 dst = cycles(dst, BUS);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3119 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3120 dst = neg_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3121 } else {
165
62b152811bae Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents: 162
diff changeset
3122 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3123 }
173
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3124 dst = setcc_r(dst, CC_C, FLAG_C);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3125 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3126 dst = setcc_r(dst, CC_S, FLAG_N);
173
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3127 dst = setcc_r(dst, CC_O, FLAG_V);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3128 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3129 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3130 break;
173
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3131 case M68K_NEGX:
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3132 dst = cycles(dst, BUS);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3133 if (dst_op.mode == MODE_REG_DIRECT) {
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3134 if (dst_op.base == SCRATCH1) {
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3135 dst = push_r(dst, SCRATCH2);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3136 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3137 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3138 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3139 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3140 dst = pop_r(dst, SCRATCH2);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3141 } else {
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3142 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3143 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3144 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3145 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3146 }
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3147 } else {
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3148 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3149 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3150 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3151 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3152 }
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3153 dst = setcc_r(dst, CC_C, FLAG_C);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3154 dst = jcc(dst, CC_NZ, dst+4);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3155 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3156 dst = setcc_r(dst, CC_S, FLAG_N);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3157 dst = setcc_r(dst, CC_O, FLAG_V);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3158 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3159 dst = m68k_save_result(inst, dst, opts);
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3160 break;
47b2796fb277 Implement negx
Mike Pavone <pavone@retrodev.com>
parents: 172
diff changeset
3161 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3162 case M68K_NOP:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3163 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3164 break;
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3165 case M68K_NOT:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3166 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3167 dst = not_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3168 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3169 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3170 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3171 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3172 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3173 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3174 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3175 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3176 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3177 case M68K_OR:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3178 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3179 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3180 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3181 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3182 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3183 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3184 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3185 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3186 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3187 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3188 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3189 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3190 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3191 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3192 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3193 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3194 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3195 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3196 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3197 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3198 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3199 break;
106
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3200 case M68K_ORI_CCR:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3201 case M68K_ORI_SR:
106
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3202 dst = cycles(dst, 20);
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3203 //TODO: If ANDI to SR, trap if not in supervisor mode
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3204 if (inst->src.params.immed & 0x1) {
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3205 dst = mov_ir(dst, 1, FLAG_C, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3206 }
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3207 if (inst->src.params.immed & 0x2) {
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3208 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3209 }
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3210 if (inst->src.params.immed & 0x4) {
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3211 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3212 }
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3213 if (inst->src.params.immed & 0x8) {
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3214 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3215 }
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3216 if (inst->src.params.immed & 0x10) {
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3217 dst = mov_irind(dst, 1, CONTEXT, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3218 }
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3219 if (inst->op == M68K_ORI_SR) {
106
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3220 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3221 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3222 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3223 }
106
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3224 }
1eba2b9455f8 Implement ORI to CCR/SR
Mike Pavone <pavone@retrodev.com>
parents: 105
diff changeset
3225 break;
122
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3226 /*case M68K_RESET:*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3227 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3228 case M68K_ROR:
122
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3229 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3230 if (inst->src.addr_mode == MODE_UNUSED) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3231 dst = cycles(dst, BUS);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3232 //Memory rotate
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3233 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3234 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3235 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3236 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3237 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3238 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3239 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3240 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3241 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3242 dst = m68k_save_result(inst, dst, opts);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3243 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3244 if (src_op.mode == MODE_IMMED) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3245 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3246 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3247 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3248 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3249 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3250 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3251 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3252 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3253 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3254 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3255 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3256 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3257 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3258 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3259 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3260 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3261 if (src_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3262 if (src_op.base != SCRATCH1) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3263 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3264 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3265 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3266 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3267 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3268 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3269 zero_off = dst+1;
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3270 dst = jcc(dst, CC_Z, dst+2);
122
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3271 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3272 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3273 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3274 norm_off = dst+1;
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3275 dst = jcc(dst, CC_L, dst+2);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3276 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3277 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3278 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3279 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3280 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3281 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3282 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3283 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3284 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3285 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3286 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3287 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3288 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3289 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3290 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3291 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3292 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3293 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3294 *norm_off = dst - (norm_off+1);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3295 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3296 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3297 dst = rol_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3298 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3299 dst = ror_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3300 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3301 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3302 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3303 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3304 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3305 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3306 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3307 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3308 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3309 end_off = dst + 1;
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3310 dst = jmp(dst, dst+2);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3311 *zero_off = dst - (zero_off+1);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3312 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3313 *end_off = dst - (end_off+1);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3314 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3315 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3316 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3317 } else {
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3318 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3319 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3320 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3321 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3322 }
0a6da6c7c463 Implemented ROL and ROR
Mike Pavone <pavone@retrodev.com>
parents: 121
diff changeset
3323 break;
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3324 case M68K_ROXL:
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3325 case M68K_ROXR:
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3326 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3327 if (inst->src.addr_mode == MODE_UNUSED) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3328 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3329 //Memory rotate
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3330 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3331 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3332 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3333 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3334 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3335 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3336 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3337 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3338 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3339 dst = setcc_r(dst, CC_S, FLAG_N);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3340 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3341 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3342 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3343 if (src_op.mode == MODE_IMMED) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3344 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3345 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3346 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3347 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3348 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3349 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3350 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3351 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3352 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3353 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3354 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3355 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3356 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3357 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3358 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3359 dst = setcc_r(dst, CC_C, FLAG_C);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3360 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3361 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3362 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3363 if (src_op.base != SCRATCH1) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3364 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3365 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3366 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3367 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3368 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3369 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3370 zero_off = dst+1;
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3371 dst = jcc(dst, CC_Z, dst+2);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3372 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3373 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3374 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3375 norm_off = dst+1;
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3376 dst = jcc(dst, CC_L, dst+2);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3377 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3378 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3379 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3380 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3381 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3382 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3383 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3384 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3385 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3386 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3387 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3388 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3389 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3390 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3391 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3392 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3393 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3394 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3395 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3396 *norm_off = dst - (norm_off+1);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3397 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3398 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3399 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3400 dst = rcl_clr(dst, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3401 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3402 dst = rcr_clr(dst, dst_op.base, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3403 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3404 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3405 if (inst->op == M68K_ROXL) {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3406 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3407 } else {
157
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents: 156
diff changeset
3408 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3409 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3410 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3411 dst = setcc_r(dst, CC_C, FLAG_C);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3412 dst = mov_rr(dst, FLAG_C, CONTEXT, SZ_B);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3413 end_off = dst + 1;
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3414 dst = jmp(dst, dst+2);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3415 *zero_off = dst - (zero_off+1);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3416 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3417 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3418 *end_off = dst - (end_off+1);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3419 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3420 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3421 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3422 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3423 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3424 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3425 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3426 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3427 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3428 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3429 case M68K_RTE:
170
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3430 //TODO: Trap if not in system mode
175
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3431 //Read saved SR
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3432 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3433 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3434 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3435 dst = call(dst, (uint8_t *)set_sr);
178
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents: 177
diff changeset
3436 //Read saved PC
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents: 177
diff changeset
3437 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents: 177
diff changeset
3438 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents: 177
diff changeset
3439 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
175
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3440 //Check if we've switched to user mode and swap stack pointers if needed
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3441 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3442 end_off = dst+1;
121
f848aad2abef Fix logic for switching between USP and SSP
Mike Pavone <pavone@retrodev.com>
parents: 119
diff changeset
3443 dst = jcc(dst, CC_C, dst+2);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3444 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3445 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3446 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3447 *end_off = dst - (end_off+1);
175
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3448 //Get native address, sync components, recalculate integer points and jump to returned address
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3449 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3450 dst = jmp_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3451 break;
170
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3452 case M68K_RTR:
175
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3453 //Read saved CCR
170
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3454 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3455 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3456 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3457 dst = call(dst, (uint8_t *)set_ccr);
175
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3458 //Read saved PC
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3459 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3460 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3461 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3462 //Get native address and jump to it
7504200cac86 Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
3463 dst = call(dst, (uint8_t *)m68k_native_addr);
170
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3464 dst = jmp_r(dst, SCRATCH1);
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3465 break;
7d1b04537377 Implement RTR
Mike Pavone <pavone@retrodev.com>
parents: 169
diff changeset
3466 /*case M68K_SBCD:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3467 case M68K_STOP:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
3468 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3469 case M68K_SUB:
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3470 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3471 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3472 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3473 if (dst_op.mode == MODE_REG_DIRECT) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3474 dst = sub_rr(dst, src_op.base, dst_op.base, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3475 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3476 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3477 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3478 } else if (src_op.mode == MODE_REG_DISPLACE8) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3479 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3480 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3481 if (dst_op.mode == MODE_REG_DIRECT) {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3482 dst = sub_ir(dst, src_op.disp, dst_op.base, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3483 } else {
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3484 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3485 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3486 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3487 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3488 dst = setcc_r(dst, CC_C, FLAG_C);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3489 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3490 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3491 dst = setcc_r(dst, CC_O, FLAG_V);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3492 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3493 }
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3494 dst = m68k_save_result(inst, dst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3495 break;
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3496 case M68K_SUBX:
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3497 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3498 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3499 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3500 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3501 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3502 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3503 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3504 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3505 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3506 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3507 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3508 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3509 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3510 } else {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3511 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3512 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3513 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3514 dst = setcc_r(dst, CC_C, FLAG_C);
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3515 dst = jcc(dst, CC_Z, dst+4);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3516 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3517 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3518 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3519 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3520 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 133
diff changeset
3521 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3522 case M68K_SWAP:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3523 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3524 if (src_op.mode == MODE_REG_DIRECT) {
129
691e4b147cea Fix swap
Mike Pavone <pavone@retrodev.com>
parents: 128
diff changeset
3525 dst = rol_ir(dst, 16, src_op.base, SZ_D);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3526 } else{
129
691e4b147cea Fix swap
Mike Pavone <pavone@retrodev.com>
parents: 128
diff changeset
3527 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3528 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3529 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3530 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3531 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3532 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3533 break;
152
79958b95526f Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
3534 //case M68K_TAS:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3535 case M68K_TRAP:
152
79958b95526f Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
3536 dst = mov_ir(dst, src_op.disp, SCRATCH2, SZ_D);
183
2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents: 182
diff changeset
3537 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
152
79958b95526f Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
3538 dst = jmp(dst, (uint8_t *)m68k_trap);
79958b95526f Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
3539 break;
79958b95526f Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
3540 //case M68K_TRAPV:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3541 case M68K_TST:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3542 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3543 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3544 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3545 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3546 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3547 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3548 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3549 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3550 dst = setcc_r(dst, CC_S, FLAG_N);
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
3551 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
3552 break;
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3553 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3554 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3555 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3556 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3557 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3558 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3559 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3560 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3561 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3562 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3563 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3564 } else {
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
3565 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3566 }
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 92
diff changeset
3567 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
3568 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
3569 default:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3570 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 150
diff changeset
3571 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op);
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
3572 exit(1);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3573 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3574 return dst;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3575 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3576
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3577 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context)
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3578 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3579 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3580 x86_68k_options * opts = context->options;
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3581 uint8_t * dst = opts->cur_code;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3582 uint8_t * dst_end = opts->code_end;
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3583 if(get_native_address(opts->native_code_map, address)) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3584 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3585 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3586 char disbuf[1024];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3587 uint16_t *encoded, *next;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3588 if ((address & 0xFFFFFF) < 0x400000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3589 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3590 } else if ((address & 0xFFFFFF) > 0xE00000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3591 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3592 } else {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3593 printf("attempt to translate non-memory address: %X\n", address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3594 exit(1);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3595 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3596 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3597 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3598 if (dst_end-dst < 128) {
102
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3599 if (dst_end-dst < 5) {
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3600 puts("out of code memory, not enough space for jmp to next chunk");
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3601 exit(1);
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3602 }
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3603 size_t size = 1024*1024;
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3604 opts->cur_code = alloc_code(&size);
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3605 opts->code_end = opts->cur_code + size;
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3606 jmp(dst, opts->cur_code);
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3607 dst = opts->cur_code;
bfaca67eeb78 allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents: 100
diff changeset
3608 dst_end = opts->code_end;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3609 }
159
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents: 158
diff changeset
3610 if (address >= 0x400000 && address < 0xE00000) {
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents: 158
diff changeset
3611 dst = xor_rr(dst, RDI, RDI, SZ_D);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents: 158
diff changeset
3612 dst = call(dst, (uint8_t *)exit);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents: 158
diff changeset
3613 break;
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents: 158
diff changeset
3614 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3615 uint8_t * existing = get_native_address(opts->native_code_map, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3616 if (existing) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3617 dst = jmp(dst, existing);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3618 break;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3619 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3620 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3621 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3622 encoded = next;
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3623 //m68k_disasm(&instbuf, disbuf);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
3624 //printf("%X: %s\n", instbuf.address, disbuf);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3625 dst = translate_m68k(dst, &instbuf, opts);
177
09761d4391e1 Make sure we bail out of translation after translating an invalid instruction
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
3626 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_INVALID && instbuf.op != M68K_TRAP && instbuf.op != M68K_RTS && instbuf.op != M68K_RTR && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3627 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3628 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3629 address = opts->deferred->address;
124
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3630 if ((address & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3631 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3632 } else if ((address & 0xFFFFFF) > 0xE00000) {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3633 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3634 } else {
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3635 printf("attempt to translate non-memory address: %X\n", address);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3636 exit(1);
da95566514f3 Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
3637 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3638 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3639 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3640 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3641 } while(encoded != NULL);
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3642 opts->cur_code = dst;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3643 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3644 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3645
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3646 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address)
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3647 {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3648 address &= 0xFFFFFF;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3649 uint8_t * ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3650 if (!ret) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3651 translate_m68k_stream(address, context);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3652 ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3653 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3654 return ret;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3655 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3656
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3657 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler)
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3658 {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3659 static uint8_t * bp_stub = NULL;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3660 uint8_t * native = get_native_address_trans(context, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3661 uint8_t * start_native = native;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3662 native = mov_ir(native, address, SCRATCH1, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3663 if (!bp_stub) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3664 x86_68k_options * opts = context->options;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3665 uint8_t * dst = opts->cur_code;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3666 uint8_t * dst_end = opts->code_end;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3667 if (dst_end - dst < 128) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3668 size_t size = 1024*1024;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3669 dst = alloc_code(&size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3670 opts->code_end = dst_end = dst + size;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3671 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3672 bp_stub = dst;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3673 native = call(native, bp_stub);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3674
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3675 //Calculate length of prologue
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3676 dst = check_cycles_int(dst, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3677 int check_int_size = dst-bp_stub;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3678 dst = bp_stub;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3679
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3680 //Save context and call breakpoint handler
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3681 dst = call(dst, (uint8_t *)m68k_save_context);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3682 dst = push_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3683 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3684 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3685 dst = call(dst, bp_handler);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3686 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3687 //Restore context
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3688 dst = call(dst, (uint8_t *)m68k_load_context);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3689 dst = pop_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3690 //do prologue stuff
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3691 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3692 uint8_t * jmp_off = dst+1;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3693 dst = jcc(dst, CC_NC, dst + 7);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3694 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3695 *jmp_off = dst - (jmp_off+1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3696 //jump back to body of translated instruction
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3697 dst = pop_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3698 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3699 dst = jmp_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3700 opts->cur_code = dst;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3701 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3702 native = call(native, bp_stub);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3703 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3704 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3705
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3706 void remove_breakpoint(m68k_context * context, uint32_t address)
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3707 {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3708 uint8_t * native = get_native_address(context->native_code_map, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3709 check_cycles_int(native, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3710 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
3711
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3712 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3713 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3714 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3715 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3716 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3717
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
3718 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
3719 {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3720 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3721 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3722 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
3723 start_68k_context(context, address);
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
3724 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
3725
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3726 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3727 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3728 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3729 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3730 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3731 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3732 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3733 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3734 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3735 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3736 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3737 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3738 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3739 opts->deferred = NULL;
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3740 size_t size = 1024 * 1024;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3741 opts->cur_code = alloc_code(&size);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
3742 opts->code_end = opts->cur_code + size;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3743 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3744
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3745 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3746 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3747 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3748 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3749 context->options = opts;
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
3750 context->int_cycle = 0xFFFFFFFF;
167
f6c7fea1ecf7 Initialize status register to proper value on startup
Mike Pavone <pavone@retrodev.com>
parents: 165
diff changeset
3751 context->status = 0x27;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3752 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
3753