Mercurial > repos > blastem
annotate vdp.c @ 333:f16136a3835d
Update Z80 vint timing
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Tue, 14 May 2013 00:40:10 -0700 |
| parents | 671a5be51522 |
| children | 4c91470e1a53 |
| rev | line source |
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1 #include "vdp.h" |
| 75 | 2 #include "blastem.h" |
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3 #include <stdlib.h> |
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4 #include <string.h> |
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5 |
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6 #define NTSC_ACTIVE 225 |
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7 #define PAL_ACTIVE 241 |
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8 #define BUF_BIT_PRIORITY 0x40 |
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9 #define MAP_BIT_PRIORITY 0x8000 |
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10 #define MAP_BIT_H_FLIP 0x800 |
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11 #define MAP_BIT_V_FLIP 0x1000 |
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12 |
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13 //Mode reg 1 |
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14 #define BIT_HINT_EN 0x10 |
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15 #define BIT_PAL_SEL 0x04 |
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16 #define BIT_HVC_LATCH 0x02 |
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17 #define BIT_DISP_DIS 0x01 |
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18 |
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19 //Mode reg 2 |
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20 #define BIT_DISP_EN 0x40 |
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21 #define BIT_VINT_EN 0x20 |
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22 #define BIT_DMA_ENABLE 0x10 |
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23 #define BIT_PAL 0x08 |
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24 #define BIT_MODE_5 0x04 |
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25 |
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26 //Mode reg 3 |
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27 #define BIT_EINT_EN 0x10 |
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28 #define BIT_VSCROLL 0x04 |
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29 |
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30 //Mode reg 4 |
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31 #define BIT_H40 0x01 |
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32 #define BIT_HILIGHT 0x8 |
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33 |
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34 #define SCROLL_BUFFER_SIZE 32 |
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35 #define SCROLL_BUFFER_DRAW 16 |
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36 |
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37 #define FIFO_SIZE 4 |
| 40 | 38 |
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39 #define MCLKS_SLOT_H40 16 |
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40 #define MCLKS_SLOT_H32 20 |
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41 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
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42 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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43 #define HSYNC_SLOT_H40 21 |
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44 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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45 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
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46 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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47 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
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48 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
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49 |
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50 void init_vdp_context(vdp_context * context) |
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51 { |
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52 memset(context, 0, sizeof(*context)); |
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53 context->vdpmem = malloc(VRAM_SIZE); |
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54 memset(context->vdpmem, 0, VRAM_SIZE); |
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55 context->framebuf = malloc(FRAMEBUF_SIZE); |
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56 memset(context->framebuf, 0, FRAMEBUF_SIZE); |
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57 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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58 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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59 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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60 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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61 context->sprite_draws = MAX_DRAWS; |
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62 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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63 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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64 } |
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65 |
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66 void render_sprite_cells(vdp_context * context) |
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67 { |
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68 if (context->cur_slot >= context->sprite_draws) { |
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69 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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70 |
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71 uint16_t dir; |
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72 int16_t x; |
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73 if (d->h_flip) { |
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74 x = d->x_pos + 7; |
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75 dir = -1; |
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76 } else { |
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77 x = d->x_pos; |
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78 dir = 1; |
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79 } |
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80 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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81 context->cur_slot--; |
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82 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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83 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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84 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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85 } |
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86 x += dir; |
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87 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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88 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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89 } |
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90 x += dir; |
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91 } |
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92 } |
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93 } |
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94 |
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95 void vdp_print_sprite_table(vdp_context * context) |
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96 { |
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97 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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98 uint16_t current_index = 0; |
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99 uint8_t count = 0; |
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100 do { |
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101 uint16_t address = current_index * 8 + sat_address; |
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102 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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103 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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104 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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105 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
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106 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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107 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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108 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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109 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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110 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
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111 current_index = link; |
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112 count++; |
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113 } while (current_index != 0 && count < 80); |
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114 } |
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115 |
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116 void vdp_print_reg_explain(vdp_context * context) |
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117 { |
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118 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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119 printf("**Mode Group**\n" |
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120 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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121 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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122 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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123 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
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124 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
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125 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
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126 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
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127 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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128 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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129 hscroll[context->regs[REG_MODE_3] & 0x3], |
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130 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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131 printf("\n**Table Group**\n" |
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132 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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133 "03: %.2X | Window Name Table: $%.4X\n" |
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134 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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135 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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136 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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137 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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138 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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139 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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140 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
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141 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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142 char * sizes[] = {"32", "64", "invalid", "128"}; |
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143 printf("\n**Misc Group**\n" |
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144 "07: %.2X | Backdrop Color: $%X\n" |
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145 "0A: %.2X | H-Int Counter: %u\n" |
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146 "0F: %.2X | Auto-increment: $%X\n" |
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147 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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148 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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149 context->regs[REG_HINT], context->regs[REG_HINT], |
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150 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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151 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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152 |
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153 //TODO: Window Group, DMA Group |
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154 } |
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155 |
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156 void scan_sprite_table(uint32_t line, vdp_context * context) |
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157 { |
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158 if (context->sprite_index && context->slot_counter) { |
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159 line += 1; |
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160 line &= 0xFF; |
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161 context->sprite_index &= 0x7F; |
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162 if (context->latched_mode & BIT_H40) { |
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163 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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164 context->sprite_index = 0; |
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165 return; |
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166 } |
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167 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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168 context->sprite_index = 0; |
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169 return; |
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170 } |
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171 //TODO: Read from SAT cache rather than from VRAM |
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172 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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173 uint16_t address = context->sprite_index * 8 + sat_address; |
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174 line += 128; |
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175 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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176 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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177 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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178 if (y <= line && line < (y + height)) { |
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179 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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180 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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181 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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182 context->sprite_info_list[context->slot_counter].y = y-128; |
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183 } |
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184 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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185 if (context->sprite_index && context->slot_counter) |
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186 { |
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187 address = context->sprite_index * 8 + sat_address; |
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188 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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189 height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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190 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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191 if (y <= line && line < (y + height)) { |
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192 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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193 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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194 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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180
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195 context->sprite_info_list[context->slot_counter].y = y-128; |
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196 } |
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197 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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198 } |
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199 } |
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200 } |
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201 |
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202 void read_sprite_x(uint32_t line, vdp_context * context) |
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203 { |
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204 if (context->cur_slot >= context->slot_counter) { |
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205 if (context->sprite_draws) { |
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206 line += 1; |
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207 line &= 0xFF; |
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208 //in tiles |
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209 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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210 //in pixels |
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211 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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212 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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213 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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214 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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215 uint8_t row; |
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216 if (tileinfo & MAP_BIT_V_FLIP) { |
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217 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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218 } else { |
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219 row = line-context->sprite_info_list[context->cur_slot].y; |
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220 } |
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221 uint16_t address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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222 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
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223 if (x) { |
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224 context->flags |= FLAG_CAN_MASK; |
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225 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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226 context->flags |= FLAG_MASKED; |
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227 } |
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228 |
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229 context->flags &= ~FLAG_DOT_OFLOW; |
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230 int16_t i; |
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231 if (context->flags & FLAG_MASKED) { |
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232 for (i=0; i < width && context->sprite_draws; i++) { |
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233 --context->sprite_draws; |
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234 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
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235 } |
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236 } else { |
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237 x -= 128; |
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238 int16_t base_x = x; |
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239 int16_t dir; |
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240 if (tileinfo & MAP_BIT_H_FLIP) { |
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241 x += (width-1) * 8; |
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242 dir = -8; |
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243 } else { |
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244 dir = 8; |
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245 } |
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246 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
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247 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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248 --context->sprite_draws; |
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249 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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250 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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251 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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252 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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253 } |
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254 } |
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255 if (i < width) { |
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256 context->flags |= FLAG_DOT_OFLOW; |
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257 } |
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258 context->cur_slot--; |
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259 } else { |
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260 context->flags |= FLAG_DOT_OFLOW; |
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261 } |
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262 } |
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263 } |
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264 |
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265 #define VRAM_READ 0 |
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266 #define VRAM_WRITE 1 |
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267 #define CRAM_READ 8 |
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268 #define CRAM_WRITE 3 |
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269 #define VSRAM_READ 4 |
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270 #define VSRAM_WRITE 5 |
| 75 | 271 #define DMA_START 0x20 |
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272 |
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273 void external_slot(vdp_context * context) |
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274 { |
| 75 | 275 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
| 276 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
| 277 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
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278 if(context->flags & FLAG_DMA_RUN) { |
| 75 | 279 uint16_t dma_len; |
| 280 switch(context->regs[REG_DMASRC_H] & 0xC0) | |
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281 { |
| 75 | 282 //68K -> VDP |
| 283 case 0: | |
| 284 case 0x40: | |
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285 switch(context->dma_cd & 0xF) |
| 75 | 286 { |
| 287 case VRAM_WRITE: | |
| 288 if (context->flags & FLAG_DMA_PROG) { | |
| 289 context->vdpmem[context->address ^ 1] = context->dma_val; | |
| 290 context->flags &= ~FLAG_DMA_PROG; | |
| 291 } else { | |
| 292 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 293 context->vdpmem[context->address] = context->dma_val >> 8; | |
| 294 context->flags |= FLAG_DMA_PROG; | |
| 295 } | |
| 296 break; | |
| 297 case CRAM_WRITE: | |
| 298 context->cram[(context->address/2) & (CRAM_SIZE-1)] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
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299 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles); |
| 75 | 300 break; |
| 301 case VSRAM_WRITE: | |
| 302 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 303 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 304 } | |
| 305 break; | |
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306 } |
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307 break; |
| 75 | 308 //Fill |
| 309 case 0x80: | |
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310 switch(context->dma_cd & 0xF) |
| 75 | 311 { |
| 312 case VRAM_WRITE: | |
| 313 //Charles MacDonald's VDP doc says that the low byte gets written first | |
| 142 | 314 context->vdpmem[context->address] = context->dma_val; |
| 315 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF); | |
| 75 | 316 break; |
| 317 case CRAM_WRITE: | |
| 318 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
| 319 break; | |
| 320 case VSRAM_WRITE: | |
| 321 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 322 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 323 } | |
| 324 break; | |
| 325 } | |
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326 break; |
| 75 | 327 //Copy |
| 328 case 0xC0: | |
| 329 if (context->flags & FLAG_DMA_PROG) { | |
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330 switch(context->dma_cd & 0xF) |
| 75 | 331 { |
| 332 case VRAM_WRITE: | |
| 333 context->vdpmem[context->address] = context->dma_val; | |
| 334 break; | |
| 335 case CRAM_WRITE: | |
| 336 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
| 337 break; | |
| 338 case VSRAM_WRITE: | |
| 339 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 340 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 341 } | |
| 342 break; | |
| 343 } | |
| 344 context->flags &= ~FLAG_DMA_PROG; | |
| 345 } else { | |
| 346 //I assume, that DMA copy copies from the same RAM as the destination | |
| 347 //but it's possible I'm mistaken | |
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348 switch(context->dma_cd & 0xF) |
| 75 | 349 { |
| 350 case VRAM_WRITE: | |
| 351 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
| 352 break; | |
| 353 case CRAM_WRITE: | |
| 354 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
| 355 break; | |
| 356 case VSRAM_WRITE: | |
| 357 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
| 358 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
| 359 } else { | |
| 360 context->dma_val = 0; | |
| 361 } | |
| 362 break; | |
| 363 } | |
| 364 context->flags |= FLAG_DMA_PROG; | |
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365 } |
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366 break; |
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367 } |
| 75 | 368 if (!(context->flags & FLAG_DMA_PROG)) { |
| 369 context->address += context->regs[REG_AUTOINC]; | |
| 370 context->regs[REG_DMASRC_L] += 1; | |
| 135 | 371 if (!context->regs[REG_DMASRC_L]) { |
| 372 context->regs[REG_DMASRC_M] += 1; | |
| 373 } | |
| 75 | 374 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
| 375 context->regs[REG_DMALEN_H] = dma_len >> 8; | |
| 376 context->regs[REG_DMALEN_L] = dma_len; | |
| 377 if (!dma_len) { | |
| 378 context->flags &= ~FLAG_DMA_RUN; | |
| 379 } | |
|
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380 } |
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381 } else { |
| 75 | 382 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
| 383 if (context->fifo_cur != start && start->cycle <= context->cycles) { | |
| 384 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { | |
| 385 context->flags |= FLAG_DMA_RUN; | |
| 386 context->dma_val = start->value; | |
| 138 | 387 context->address = start->address; //undo auto-increment |
|
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388 context->dma_cd = context->cd; |
| 75 | 389 } else { |
| 138 | 390 switch (start->cd & 0xF) |
| 75 | 391 { |
| 392 case VRAM_WRITE: | |
| 393 if (start->partial) { | |
| 394 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); | |
| 138 | 395 context->vdpmem[start->address ^ 1] = start->value; |
| 75 | 396 } else { |
| 397 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); | |
| 138 | 398 context->vdpmem[start->address] = start->value >> 8; |
| 75 | 399 start->partial = 1; |
| 400 //skip auto-increment and removal of entry from fifo | |
| 401 return; | |
| 402 } | |
| 403 break; | |
| 404 case CRAM_WRITE: | |
|
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405 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
| 138 | 406 context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value; |
| 75 | 407 break; |
| 408 case VSRAM_WRITE: | |
| 138 | 409 if (((start->address/2) & 63) < VSRAM_SIZE) { |
| 75 | 410 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
| 138 | 411 context->vsram[(start->address/2) & 63] = start->value; |
| 75 | 412 } |
| 413 break; | |
| 414 } | |
| 138 | 415 //context->address += context->regs[REG_AUTOINC]; |
| 75 | 416 } |
| 417 fifo_entry * cur = start+1; | |
| 418 if (cur < context->fifo_cur) { | |
| 419 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); | |
| 420 } | |
| 421 context->fifo_cur -= 1; | |
| 422 } else { | |
| 423 context->flags |= FLAG_UNUSED_SLOT; | |
| 424 } | |
|
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425 } |
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426 } |
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427 |
| 40 | 428 #define WINDOW_RIGHT 0x80 |
| 429 #define WINDOW_DOWN 0x80 | |
| 430 | |
|
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431 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
|
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432 { |
| 40 | 433 if (!vsram_off) { |
| 434 uint16_t left_col, right_col; | |
| 435 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
|
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436 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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437 right_col = 42; |
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438 } else { |
| 40 | 439 left_col = 0; |
| 440 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
| 441 if (right_col) { | |
| 442 right_col += 2; | |
| 443 } | |
| 444 } | |
|
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445 uint16_t top_line, bottom_line; |
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446 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
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447 top_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8; |
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448 bottom_line = 241; |
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449 } else { |
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450 top_line = 0; |
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451 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8; |
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452 } |
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453 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
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454 uint16_t address = context->regs[REG_WINDOW] << 10; |
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455 uint16_t line_offset, offset, mask; |
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456 if (context->latched_mode & BIT_H40) { |
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457 address &= 0xF000; |
|
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458 line_offset = (((line) / 8) * 64 * 2) & 0xFFF; |
|
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459 mask = 0x7F; |
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460 |
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461 } else { |
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462 address &= 0xF800; |
|
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463 line_offset = (((line) / 8) * 32 * 2) & 0xFFF; |
|
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464 mask = 0x3F; |
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465 } |
|
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466 offset = address + line_offset + (((column - 2) * 2) & mask); |
|
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467 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
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468 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
|
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469 offset = address + line_offset + (((column - 1) * 2) & mask); |
|
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470 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
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471 context->v_offset = (line) & 0x7; |
|
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472 context->flags |= FLAG_WINDOW; |
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473 return; |
| 40 | 474 } |
| 475 context->flags &= ~FLAG_WINDOW; | |
| 476 } | |
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477 uint16_t vscroll; |
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478 switch(context->regs[REG_SCROLL] & 0x30) |
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479 { |
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480 case 0: |
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481 vscroll = 0xFF; |
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482 break; |
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483 case 0x10: |
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484 vscroll = 0x1FF; |
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485 break; |
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486 case 0x20: |
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487 //TODO: Verify this behavior |
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488 vscroll = 0; |
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489 break; |
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490 case 0x30: |
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491 vscroll = 0x3FF; |
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492 break; |
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493 } |
|
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494 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? column : 0) + vsram_off] + line); |
|
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495 context->v_offset = vscroll & 0x7; |
|
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496 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
|
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497 vscroll /= 8; |
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498 uint16_t hscroll_mask; |
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499 uint16_t v_mul; |
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500 switch(context->regs[REG_SCROLL] & 0x3) |
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501 { |
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502 case 0: |
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503 hscroll_mask = 0x1F; |
|
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504 v_mul = 64; |
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505 break; |
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506 case 0x1: |
|
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507 hscroll_mask = 0x3F; |
|
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508 v_mul = 128; |
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509 break; |
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510 case 0x2: |
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511 //TODO: Verify this behavior |
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512 hscroll_mask = 0; |
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513 v_mul = 0; |
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514 break; |
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515 case 0x3: |
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|
516 hscroll_mask = 0x7F; |
|
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517 v_mul = 256; |
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518 break; |
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519 } |
| 28 | 520 uint16_t hscroll, offset; |
| 521 for (int i = 0; i < 2; i++) { | |
|
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522 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
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523 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
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524 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
| 28 | 525 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
| 526 if (i) { | |
| 527 context->col_2 = col_val; | |
| 528 } else { | |
| 529 context->col_1 = col_val; | |
| 530 } | |
| 531 } | |
|
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532 } |
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533 |
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534 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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535 { |
|
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|
536 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
|
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537 } |
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538 |
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539 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
|
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540 { |
|
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24
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|
541 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
|
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542 } |
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|
543 |
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544 void render_map(uint16_t col, uint8_t * tmp_buf, vdp_context * context) |
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545 { |
|
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6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
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546 uint16_t address = ((col & 0x7FF) << 5); |
|
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547 if (col & MAP_BIT_V_FLIP) { |
|
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548 address += 28 - 4 * context->v_offset; |
|
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549 } else { |
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550 address += 4 * context->v_offset; |
|
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551 } |
|
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552 uint16_t pal_priority = (col >> 9) & 0x70; |
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553 int32_t dir; |
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parents:
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554 if (col & MAP_BIT_H_FLIP) { |
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555 tmp_buf += 7; |
|
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556 dir = -1; |
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557 } else { |
|
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558 dir = 1; |
|
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|
559 } |
|
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changeset
|
560 for (uint32_t i=0; i < 4; i++, address++) |
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561 { |
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562 *tmp_buf = pal_priority | (context->vdpmem[address] >> 4); |
|
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|
563 tmp_buf += dir; |
|
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564 *tmp_buf = pal_priority | (context->vdpmem[address] & 0xF); |
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565 tmp_buf += dir; |
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566 } |
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567 } |
|
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|
568 |
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diff
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|
569 void render_map_1(vdp_context * context) |
|
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570 { |
|
39
3c69319269ef
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Mike Pavone <pavone@retrodev.com>
parents:
38
diff
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571 render_map(context->col_1, context->tmp_buf_a+SCROLL_BUFFER_DRAW, context); |
|
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572 } |
|
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|
573 |
|
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|
574 void render_map_2(vdp_context * context) |
|
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|
575 { |
|
39
3c69319269ef
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Mike Pavone <pavone@retrodev.com>
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38
diff
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|
576 render_map(context->col_2, context->tmp_buf_a+SCROLL_BUFFER_DRAW+8, context); |
|
20
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|
577 } |
|
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|
578 |
|
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changeset
|
579 void render_map_3(vdp_context * context) |
|
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|
580 { |
|
39
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Mike Pavone <pavone@retrodev.com>
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38
diff
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|
581 render_map(context->col_1, context->tmp_buf_b+SCROLL_BUFFER_DRAW, context); |
|
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changeset
|
582 } |
|
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
583 |
|
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parents:
diff
changeset
|
584 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
|
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|
585 { |
|
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Mike Pavone <pavone@retrodev.com>
parents:
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|
586 if (line >= 240) { |
|
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|
587 return; |
|
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diff
changeset
|
588 } |
|
39
3c69319269ef
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Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
589 render_map(context->col_2, context->tmp_buf_b+SCROLL_BUFFER_DRAW+8, context); |
|
20
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changeset
|
590 uint16_t *dst, *end; |
|
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parents:
diff
changeset
|
591 uint8_t *sprite_buf, *plane_a, *plane_b; |
|
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parents:
diff
changeset
|
592 if (col) |
|
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diff
changeset
|
593 { |
|
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diff
changeset
|
594 col-=2; |
|
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diff
changeset
|
595 dst = context->framebuf + line * 320 + col * 8; |
|
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diff
changeset
|
596 sprite_buf = context->linebuf + col * 8; |
|
43
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parents:
42
diff
changeset
|
597 uint16_t a_src; |
| 40 | 598 if (context->flags & FLAG_WINDOW) { |
| 599 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW; | |
|
43
3fc57e1a2c56
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Mike Pavone <pavone@retrodev.com>
parents:
42
diff
changeset
|
600 a_src = FBUF_SRC_W; |
| 40 | 601 } else { |
| 602 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW - (context->hscroll_a & 0xF); | |
|
43
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Mike Pavone <pavone@retrodev.com>
parents:
42
diff
changeset
|
603 a_src = FBUF_SRC_A; |
| 40 | 604 } |
|
39
3c69319269ef
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Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
605 plane_b = context->tmp_buf_b + SCROLL_BUFFER_DRAW - (context->hscroll_b & 0xF); |
| 30 | 606 end = dst + 16; |
|
43
3fc57e1a2c56
Add debug render mode and fix vertical flip bit for bg tiles
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42
diff
changeset
|
607 uint16_t src; |
| 30 | 608 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
|
230
d3266cee02c9
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diff
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|
609 |
|
d3266cee02c9
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191
diff
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|
610 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
|
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191
diff
changeset
|
611 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
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191
diff
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|
612 uint8_t pixel; |
|
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diff
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|
613 |
|
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diff
changeset
|
614 src = 0; |
|
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diff
changeset
|
615 uint8_t sprite_color = *sprite_buf & 0x3F; |
|
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diff
changeset
|
616 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
|
232
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Shadow and higlight operators were switched
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230
diff
changeset
|
617 if (sprite_color == 0x3F) { |
|
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diff
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|
618 src = FBUF_SHADOW; |
|
230
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diff
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|
619 } else { |
|
232
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diff
changeset
|
620 src = FBUF_HILIGHT; |
|
230
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191
diff
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|
621 } |
|
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191
diff
changeset
|
622 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
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|
623 pixel = *plane_a; |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
624 src |= a_src; |
|
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191
diff
changeset
|
625 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
626 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
627 src |= FBUF_SRC_B; |
|
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191
diff
changeset
|
628 } else if (*plane_a & 0xF) { |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
629 pixel = *plane_a; |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
630 src |= a_src; |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
631 } else if (*plane_b & 0xF){ |
|
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191
diff
changeset
|
632 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
633 src |= FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
634 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
635 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
636 src |= FBUF_SRC_BG; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
637 } |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
638 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
639 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
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191
diff
changeset
|
640 pixel = *sprite_buf; |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
641 src = FBUF_SRC_S; |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
642 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
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191
diff
changeset
|
643 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
644 src = a_src; |
|
d3266cee02c9
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191
diff
changeset
|
645 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
646 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
647 src = FBUF_SRC_B; |
|
233
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232
diff
changeset
|
648 } else { |
|
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232
diff
changeset
|
649 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
|
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232
diff
changeset
|
650 src = FBUF_SHADOW; |
|
230
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191
diff
changeset
|
651 } |
|
233
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232
diff
changeset
|
652 if (*sprite_buf & 0xF) { |
|
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232
diff
changeset
|
653 pixel = *sprite_buf; |
|
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232
diff
changeset
|
654 if (*sprite_buf & 0xF == 0xE) { |
|
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232
diff
changeset
|
655 src = FBUF_SRC_S; |
|
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232
diff
changeset
|
656 } else { |
|
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232
diff
changeset
|
657 src |= FBUF_SRC_S; |
|
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232
diff
changeset
|
658 } |
|
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|
659 } else if (*plane_a & 0xF) { |
|
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|
660 pixel = *plane_a; |
|
9d10669f2579
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|
661 src |= a_src; |
|
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|
662 } else if (*plane_b & 0xF){ |
|
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diff
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|
663 pixel = *plane_b; |
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232
diff
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|
664 src |= FBUF_SRC_B; |
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232
diff
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|
665 } else { |
|
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232
diff
changeset
|
666 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
9d10669f2579
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232
diff
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|
667 src |= FBUF_SRC_BG; |
|
9d10669f2579
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232
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changeset
|
668 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
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diff
changeset
|
669 } |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
670 } |
|
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Implemented shadow hilight mode.
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191
diff
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|
671 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
20
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|
672 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
673 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
674 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
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|
675 uint8_t pixel; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
676 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
677 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
678 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
679 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
680 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
681 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
682 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
683 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
684 src = FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
685 } else if (*sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
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|
686 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
687 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
688 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
689 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
690 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
691 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
692 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
693 src = FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
694 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
695 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
696 src = FBUF_SRC_BG; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
697 } |
|
291
eea3b118940d
Make sure all rendering operations mask CRAM with 0xEEE before using it
Mike Pavone <pavone@retrodev.com>
parents:
233
diff
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|
698 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
699 } |
|
20
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
700 } |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 } else { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 //dst = context->framebuf + line * 320; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 //sprite_buf = context->linebuf + col * 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 //end = dst + 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 |
| 40 | 709 uint16_t remaining; |
| 710 if (!(context->flags & FLAG_WINDOW)) { | |
| 711 remaining = context->hscroll_a & 0xF; | |
| 712 memcpy(context->tmp_buf_a + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_a + SCROLL_BUFFER_SIZE - remaining, remaining); | |
| 713 } | |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
714 remaining = context->hscroll_b & 0xF; |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
715 memcpy(context->tmp_buf_b + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_b + SCROLL_BUFFER_SIZE - remaining, remaining); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 external_slot(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
724 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
727 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
757 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 uint16_t address; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 uint32_t mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
776 case 0: |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
777 context->cur_slot = MAX_DRAWS-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
778 memset(context->linebuf, 0, LINEBUF_SIZE); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 case 2: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
782 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
783 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
784 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
785 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
786 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 //sprite attribute table scan starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 case 4: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
790 render_sprite_cells( context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 context->sprite_index = 0x80; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 context->slot_counter = MAX_SPRITES_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 case 13: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 case 14: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 case 19: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 //!HSYNC asserted |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 case 22: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
814 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 case 26: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 case 27: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case 28: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 case 31: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 case 32: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 case 33: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 case 34: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
831 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 case 35: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 mask = 0; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 if (context->regs[REG_MODE_3] & 0x2) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 mask |= 0xF8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 if (context->regs[REG_MODE_3] & 0x1) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 mask |= 0x7; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 line &= mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 address += line * 4; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
847 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 case 36: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 //!HSYNC high |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 case 37: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 case 38: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 case 39: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
854 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 case 40: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 read_map_scroll_a(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 case 41: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
861 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case 42: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 render_map_1(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 case 43: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 render_map_2(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 case 44: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 read_map_scroll_b(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 case 45: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
876 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 case 46: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 render_map_3(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 case 47: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 render_map_output(line, 0, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 //reverse context slot counter so it counts the number of sprite slots |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 //filled rather than the number of available slots |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
888 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
|
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
889 context->cur_slot = MAX_SPRITES_LINE-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 context->sprite_draws = MAX_DRAWS; |
|
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
891 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 COLUMN_RENDER_BLOCK(2, 48) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 COLUMN_RENDER_BLOCK(4, 56) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 COLUMN_RENDER_BLOCK(6, 64) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 COLUMN_RENDER_BLOCK(10, 80) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 COLUMN_RENDER_BLOCK(12, 88) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 COLUMN_RENDER_BLOCK(14, 96) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 COLUMN_RENDER_BLOCK(18, 112) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 COLUMN_RENDER_BLOCK(20, 120) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 COLUMN_RENDER_BLOCK(22, 128) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 COLUMN_RENDER_BLOCK(26, 144) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 COLUMN_RENDER_BLOCK(28, 152) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 COLUMN_RENDER_BLOCK(30, 160) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 COLUMN_RENDER_BLOCK(34, 176) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 COLUMN_RENDER_BLOCK(36, 184) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 COLUMN_RENDER_BLOCK(38, 192) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 case 208: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 case 209: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 default: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 //leftovers from HSYNC clock change nonsense |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 { |
| 37 | 925 uint16_t address; |
| 926 uint32_t mask; | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 case 0: |
| 37 | 931 context->cur_slot = MAX_DRAWS_H32-1; |
| 932 memset(context->linebuf, 0, LINEBUF_SIZE); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 case 2: |
| 37 | 935 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
936 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
937 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
938 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
939 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
940 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 break; |
| 37 | 942 //sprite attribute table scan starts |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 case 4: |
| 37 | 944 render_sprite_cells( context); |
| 945 context->sprite_index = 0x80; | |
| 946 context->slot_counter = MAX_SPRITES_LINE_H32; | |
| 947 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 case 13: |
| 37 | 958 render_sprite_cells(context); |
| 959 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 case 14: |
| 37 | 961 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 case 19: |
| 37 | 968 //HSYNC start |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 22: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 case 26: |
| 37 | 976 render_sprite_cells(context); |
| 977 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 case 27: |
| 37 | 980 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 case 28: |
| 37 | 983 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
| 984 mask = 0; | |
| 985 if (context->regs[REG_MODE_3] & 0x2) { | |
| 986 mask |= 0xF8; | |
| 987 } | |
| 988 if (context->regs[REG_MODE_3] & 0x1) { | |
| 989 mask |= 0x7; | |
| 990 } | |
| 991 line &= mask; | |
| 992 address += line * 4; | |
| 993 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
| 994 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
| 995 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 case 31: |
| 37 | 1000 case 32: |
| 1001 render_sprite_cells(context); | |
| 1002 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 break; |
| 37 | 1004 //!HSYNC high |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 case 33: |
| 37 | 1006 read_map_scroll_a(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 case 34: |
| 37 | 1009 render_sprite_cells(context); |
| 1010 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 case 35: |
| 37 | 1013 render_map_1(context); |
| 1014 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 case 36: |
| 37 | 1017 render_map_2(context); |
| 1018 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 case 37: |
| 37 | 1021 read_map_scroll_b(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 case 38: |
| 37 | 1024 render_sprite_cells(context); |
| 1025 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 case 39: |
| 37 | 1028 render_map_3(context); |
| 1029 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 case 40: |
| 37 | 1032 render_map_output(line, 0, context); |
| 1033 scan_sprite_table(line, context);//Just a guess | |
| 1034 //reverse context slot counter so it counts the number of sprite slots | |
| 1035 //filled rather than the number of available slots | |
| 1036 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
| 1037 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
| 1038 context->sprite_draws = MAX_DRAWS_H32; | |
| 1039 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 break; |
| 37 | 1041 COLUMN_RENDER_BLOCK(2, 41) |
| 1042 COLUMN_RENDER_BLOCK(4, 49) | |
| 1043 COLUMN_RENDER_BLOCK(6, 57) | |
| 1044 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
| 1045 COLUMN_RENDER_BLOCK(10, 73) | |
| 1046 COLUMN_RENDER_BLOCK(12, 81) | |
| 1047 COLUMN_RENDER_BLOCK(14, 89) | |
| 1048 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
| 1049 COLUMN_RENDER_BLOCK(18, 105) | |
| 1050 COLUMN_RENDER_BLOCK(20, 113) | |
| 1051 COLUMN_RENDER_BLOCK(22, 121) | |
| 1052 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
| 1053 COLUMN_RENDER_BLOCK(26, 137) | |
| 1054 COLUMN_RENDER_BLOCK(28, 145) | |
| 1055 COLUMN_RENDER_BLOCK(30, 153) | |
| 1056 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 case 169: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 case 170: |
| 37 | 1059 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 void latch_mode(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1068 int is_refresh(vdp_context * context, uint32_t slot) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1069 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1070 if (context->latched_mode & BIT_H40) { |
|
189
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
1071 //TODO: Figure out the exact behavior that reduces DMA slots for direct color DMA demos |
|
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1072 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210 || (slot < 6 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
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1073 } else { |
|
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1074 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
|
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1075 //These numbers are guesses based on H40 numbers |
|
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1076 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152 || (slot < 5 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
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|
1077 //The numbers below are the refresh slots during active display |
|
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1078 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
|
54
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diff
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|
1079 } |
|
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|
1080 } |
|
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|
1081 |
|
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1082 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
|
54
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|
1083 { |
|
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|
1084 if (line > 0) { |
|
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|
1085 line -= 1; |
|
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|
1086 uint16_t * start = NULL, *end = NULL; |
|
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|
1087 if (context->latched_mode & BIT_H40) { |
|
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|
1088 if (slot >= 50 && slot < 210) { |
|
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|
1089 uint32_t x = (slot-50)*2; |
|
54
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|
1090 start = context->framebuf + line * 320 + x; |
|
190
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|
1091 end = start + 2; |
|
54
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|
1092 } |
|
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|
1093 } else { |
|
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|
1094 if (slot >= 43 && slot < 171) { |
|
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|
1095 uint32_t x = (slot-43)*2; |
|
191
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|
1096 start = context->framebuf + line * 320 + x; |
|
190
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|
1097 end = start + 2; |
|
54
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diff
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|
1098 } |
|
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|
1099 } |
|
291
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Make sure all rendering operations mask CRAM with 0xEEE before using it
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|
1100 uint16_t color = (context->cram[context->regs[REG_BG_COLOR] & 0x3F] & 0xEEE); |
|
54
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diff
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|
1101 while (start != end) { |
|
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|
1102 *start = color; |
|
54
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diff
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|
1103 ++start; |
|
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diff
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|
1104 } |
|
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diff
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|
1105 } |
|
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|
1106 } |
|
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diff
changeset
|
1107 |
|
20
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parents:
diff
changeset
|
1108 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
|
f664eeb55cb4
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diff
changeset
|
1109 { |
|
f664eeb55cb4
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diff
changeset
|
1110 while(context->cycles < target_cycles) |
|
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diff
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|
1111 { |
|
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diff
changeset
|
1112 uint32_t line = context->cycles / MCLKS_LINE; |
|
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diff
changeset
|
1113 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
54
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diff
changeset
|
1114 if (!line) { |
|
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diff
changeset
|
1115 latch_mode(context); |
|
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43
diff
changeset
|
1116 } |
|
317
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291
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|
1117 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
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291
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changeset
|
1118 if (linecyc == 0) { |
|
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291
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|
1119 if (line <= 1 || line >= active_lines) { |
|
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291
diff
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|
1120 context->hint_counter = context->regs[REG_HINT]; |
|
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291
diff
changeset
|
1121 } else if (context->hint_counter) { |
|
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291
diff
changeset
|
1122 context->hint_counter--; |
|
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291
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|
1123 } else { |
|
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291
diff
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|
1124 context->flags2 |= FLAG2_HINT_PENDING; |
|
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changeset
|
1125 context->hint_counter = context->regs[REG_HINT]; |
|
e5e8b48ad157
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291
diff
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|
1126 } |
|
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Mike Pavone <pavone@retrodev.com>
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291
diff
changeset
|
1127 } else if(line == active_lines) { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1128 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
|
317
e5e8b48ad157
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291
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|
1129 if (linecyc == intcyc) { |
|
e5e8b48ad157
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291
diff
changeset
|
1130 context->flags2 |= FLAG2_VINT_PENDING; |
|
e5e8b48ad157
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291
diff
changeset
|
1131 } |
|
e5e8b48ad157
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291
diff
changeset
|
1132 } |
|
330
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|
1133 uint32_t inccycles, slot; |
|
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|
1134 if (context->latched_mode & BIT_H40){ |
|
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|
1135 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
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|
1136 slot = linecyc/MCLKS_SLOT_H40; |
|
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|
1137 inccycles = MCLKS_SLOT_H40; |
|
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|
1138 } else if(linecyc < MCLK_WEIRD_END) { |
|
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|
1139 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
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|
1140 { |
|
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diff
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|
1141 case 0: |
|
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|
1142 inccycles = 19; |
|
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|
1143 slot = 0; |
|
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|
1144 break; |
|
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|
1145 case 19: |
|
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|
1146 slot = 1; |
|
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|
1147 inccycles = 20; |
|
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changeset
|
1148 break; |
|
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|
1149 case 39: |
|
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|
1150 slot = 2; |
|
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|
1151 inccycles = 20; |
|
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diff
changeset
|
1152 break; |
|
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|
1153 case 59: |
|
332
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331
diff
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|
1154 slot = 3; |
|
330
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|
1155 inccycles = 20; |
|
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|
1156 break; |
|
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|
1157 case 79: |
|
332
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|
1158 slot = 4; |
|
330
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|
1159 inccycles = 18; |
|
57453d3d8be4
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|
1160 break; |
|
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|
1161 case 97: |
|
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|
1162 slot = 5; |
|
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changeset
|
1163 inccycles = 20; |
|
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changeset
|
1164 break; |
|
332
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331
diff
changeset
|
1165 case 117: |
|
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331
diff
changeset
|
1166 slot = 6; |
|
671a5be51522
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331
diff
changeset
|
1167 inccycles = 20; |
|
671a5be51522
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parents:
331
diff
changeset
|
1168 break; |
|
330
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diff
changeset
|
1169 case 137: |
|
332
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diff
changeset
|
1170 slot = 7; |
|
330
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diff
changeset
|
1171 inccycles = 20; |
|
57453d3d8be4
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329
diff
changeset
|
1172 break; |
|
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329
diff
changeset
|
1173 case 157: |
|
332
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331
diff
changeset
|
1174 slot = 8; |
|
330
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329
diff
changeset
|
1175 inccycles = 18; |
|
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1176 break; |
|
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1177 case 175: |
|
332
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1178 slot = 9; |
|
330
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1179 inccycles = 20; |
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1180 break; |
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1181 case 195: |
|
332
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1182 slot = 10; |
|
330
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1183 inccycles = 20; |
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1184 break; |
|
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1185 case 215: |
|
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1186 slot = 11; |
|
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1187 inccycles = 20; |
|
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1188 break; |
|
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1189 case 235: |
|
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1190 slot = 12; |
|
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1191 inccycles = 18; |
|
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1192 break; |
|
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1193 case 253: |
|
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1194 slot = 13; |
|
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1195 inccycles = 20; |
|
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1196 break; |
|
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|
1197 case 273: |
|
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1198 slot = 14; |
|
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1199 inccycles = 20; |
|
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|
1200 break; |
|
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|
1201 case 293: |
|
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1202 slot = 15; |
|
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|
1203 inccycles = 20; |
|
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|
1204 break; |
|
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|
1205 case 313: |
|
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|
1206 slot = 16; |
|
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|
1207 inccycles = 19; |
|
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|
1208 break; |
|
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|
1209 default: |
|
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|
1210 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
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|
1211 exit(1); |
|
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|
1212 } |
|
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|
1213 slot += HSYNC_SLOT_H40; |
|
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|
1214 } else { |
|
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|
1215 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
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|
1216 inccycles = MCLKS_SLOT_H40; |
|
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|
1217 } |
|
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|
1218 } else { |
|
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|
1219 inccycles = MCLKS_SLOT_H32; |
|
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1220 slot = linecyc/MCLKS_SLOT_H32; |
|
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|
1221 } |
|
329
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Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
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diff
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|
1222 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
|
20
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diff
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|
1223 //first sort-of active line is treated as 255 internally |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
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|
1224 //it's used for gathering sprite info for line |
|
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Mostly broken VDP core and savestate viewer
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diff
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|
1225 line = (line - 1) & 0xFF; |
|
f664eeb55cb4
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diff
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|
1226 |
|
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|
1227 //Convert to slot number |
|
f664eeb55cb4
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parents:
diff
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|
1228 if (context->latched_mode & BIT_H40){ |
|
330
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diff
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|
1229 vdp_h40(line, slot, context); |
|
20
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Mostly broken VDP core and savestate viewer
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diff
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|
1230 } else { |
|
330
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|
1231 vdp_h32(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1232 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1233 } else { |
|
330
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|
1234 if (!is_refresh(context, slot)) { |
|
54
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diff
changeset
|
1235 external_slot(context); |
|
3b79cbcf6846
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43
diff
changeset
|
1236 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1237 if (line < active_lines) { |
|
330
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diff
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|
1238 check_render_bg(context, line, slot); |
|
54
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43
diff
changeset
|
1239 } |
|
20
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1240 } |
|
330
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|
1241 context->cycles += inccycles; |
|
20
f664eeb55cb4
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parents:
diff
changeset
|
1242 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1243 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1244 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1245 uint32_t vdp_run_to_vblank(vdp_context * context) |
|
f664eeb55cb4
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diff
changeset
|
1246 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1247 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1248 vdp_run_context(context, target_cycles); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1249 return context->cycles; |
|
f664eeb55cb4
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diff
changeset
|
1250 } |
|
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Mostly broken VDP core and savestate viewer
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diff
changeset
|
1251 |
| 75 | 1252 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
| 1253 { | |
| 1254 for(;;) { | |
| 1255 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
| 1256 if (!dmalen) { | |
| 1257 dmalen = 0x10000; | |
| 1258 } | |
| 1259 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
| 1260 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
| 1261 //DMA copies take twice as long to complete since they require a read and a write | |
| 1262 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
| 1263 min_dma_complete *= 2; | |
| 1264 } | |
| 1265 min_dma_complete += context->cycles; | |
| 1266 if (target_cycles < min_dma_complete) { | |
| 1267 vdp_run_context(context, target_cycles); | |
| 1268 return; | |
| 1269 } else { | |
| 1270 vdp_run_context(context, min_dma_complete); | |
| 1271 if (!(context->flags & FLAG_DMA_RUN)) { | |
| 1272 return; | |
| 1273 } | |
| 1274 } | |
| 1275 } | |
| 1276 } | |
| 1277 | |
| 1278 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
|
54
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diff
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|
1279 { |
|
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents:
56
diff
changeset
|
1280 //printf("control port write: %X\n", value); |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1281 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1282 return -1; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1283 } |
|
54
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diff
changeset
|
1284 if (context->flags & FLAG_PENDING) { |
|
3b79cbcf6846
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43
diff
changeset
|
1285 context->address = (context->address & 0x3FFF) | (value << 14); |
|
3b79cbcf6846
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43
diff
changeset
|
1286 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
| 75 | 1287 context->flags &= ~FLAG_PENDING; |
|
87
60b5c9e2f4e0
vertical interrupts now work
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parents:
84
diff
changeset
|
1288 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
|
327
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323
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changeset
|
1289 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
|
1b00258b1f29
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323
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|
1290 // |
| 75 | 1291 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
| 1292 //DMA copy or 68K -> VDP, transfer starts immediately | |
| 1293 context->flags |= FLAG_DMA_RUN; | |
|
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
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109
diff
changeset
|
1294 context->dma_cd = context->cd; |
| 75 | 1295 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
|
327
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323
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changeset
|
1296 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
| 75 | 1297 return 1; |
|
327
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diff
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|
1298 } else { |
|
1b00258b1f29
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323
diff
changeset
|
1299 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
| 75 | 1300 } |
|
327
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parents:
323
diff
changeset
|
1301 } else { |
|
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
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323
diff
changeset
|
1302 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
| 75 | 1303 } |
|
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1304 } |
|
54
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43
diff
changeset
|
1305 } else { |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1306 if ((value & 0xC000) == 0x8000) { |
|
3b79cbcf6846
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43
diff
changeset
|
1307 //Register write |
|
3b79cbcf6846
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43
diff
changeset
|
1308 uint8_t reg = (value >> 8) & 0x1F; |
|
3b79cbcf6846
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diff
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|
1309 if (reg < VDP_REGS) { |
|
87
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84
diff
changeset
|
1310 //printf("register %d set to %X\n", reg, value & 0xFF); |
|
54
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43
diff
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|
1311 context->regs[reg] = value; |
|
151
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Implement MULU/MULS and DIVU/DIVS
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149
diff
changeset
|
1312 if (reg == REG_MODE_2) { |
|
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Implement MULU/MULS and DIVU/DIVS
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149
diff
changeset
|
1313 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
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diff
changeset
|
1314 } |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1315 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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diff
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|
1316 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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diff
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|
1317 context->flags |= FLAG_PENDING; |
|
3b79cbcf6846
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diff
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|
1318 context->address = (context->address &0xC000) | (value & 0x3FFF); |
|
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Get Flavio's color bar demo kind of sort of working
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diff
changeset
|
1319 context->cd = (context->cd &0x3C) | (value >> 14); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1320 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1321 } |
| 75 | 1322 return 0; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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diff
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|
1323 } |
|
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|
1324 |
|
149
139e5dcd6aa3
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diff
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|
1325 int vdp_data_port_write(vdp_context * context, uint16_t value) |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1326 { |
|
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
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56
diff
changeset
|
1327 //printf("data port write: %X\n", value); |
|
149
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|
1328 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
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diff
changeset
|
1329 return -1; |
|
139e5dcd6aa3
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diff
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|
1330 } |
|
139e5dcd6aa3
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143
diff
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|
1331 if (!(context->cd & 1)) { |
|
139e5dcd6aa3
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143
diff
changeset
|
1332 //ignore writes when cd is configured for read |
|
139e5dcd6aa3
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143
diff
changeset
|
1333 return 0; |
|
139e5dcd6aa3
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143
diff
changeset
|
1334 } |
|
54
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43
diff
changeset
|
1335 context->flags &= ~FLAG_PENDING; |
|
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
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108
diff
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|
1336 /*if (context->fifo_cur == context->fifo_end) { |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1337 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
|
109
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COmment out fifo full debug printf
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diff
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|
1338 }*/ |
|
54
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43
diff
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|
1339 while (context->fifo_cur == context->fifo_end) { |
|
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diff
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|
1340 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
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diff
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|
1341 } |
|
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diff
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|
1342 context->fifo_cur->cycle = context->cycles; |
| 138 | 1343 context->fifo_cur->address = context->address; |
|
54
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43
diff
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|
1344 context->fifo_cur->value = value; |
| 138 | 1345 context->fifo_cur->cd = context->cd; |
|
54
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43
diff
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|
1346 context->fifo_cur->partial = 0; |
|
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diff
changeset
|
1347 context->fifo_cur++; |
| 138 | 1348 context->address += context->regs[REG_AUTOINC]; |
|
149
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|
1349 return 0; |
|
54
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diff
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|
1350 } |
|
3b79cbcf6846
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diff
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|
1351 |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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diff
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|
1352 uint16_t vdp_control_port_read(vdp_context * context) |
|
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diff
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|
1353 { |
|
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|
1354 context->flags &= ~FLAG_PENDING; |
|
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diff
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|
1355 uint16_t value = 0x3400; |
|
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|
1356 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
|
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diff
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|
1357 value |= 0x200; |
|
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|
1358 } |
|
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|
1359 if (context->fifo_cur == context->fifo_end) { |
|
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|
1360 value |= 0x100; |
|
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diff
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|
1361 } |
|
317
e5e8b48ad157
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|
1362 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
e5e8b48ad157
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diff
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|
1363 value |- 0x80; |
|
e5e8b48ad157
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diff
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|
1364 } |
|
318
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Implement hblank flag in status register
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diff
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|
1365 uint32_t line= context->cycles / MCLKS_LINE; |
|
789f2f5f2277
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317
diff
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|
1366 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
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diff
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|
1367 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
|
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diff
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|
1368 value |= 0x8; |
|
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diff
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|
1369 } |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
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diff
changeset
|
1370 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
|
318
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diff
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|
1371 value |= 0x4; |
|
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|
1372 } |
|
149
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changeset
|
1373 if (context->flags & FLAG_DMA_RUN) { |
|
141
576f55711d8d
Fix DMA in progress flag in VDP status register
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138
diff
changeset
|
1374 value |= 0x2; |
| 75 | 1375 } |
|
317
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diff
changeset
|
1376 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
|
e5e8b48ad157
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291
diff
changeset
|
1377 value |= 0x1; |
|
e5e8b48ad157
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diff
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|
1378 } |
|
318
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Implement hblank flag in status register
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|
1379 //TODO: Sprite overflow, sprite collision, odd frame flag |
|
54
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|
1380 return value; |
|
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|
1381 } |
|
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|
1382 |
|
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|
1383 uint16_t vdp_data_port_read(vdp_context * context) |
|
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|
1384 { |
|
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|
1385 context->flags &= ~FLAG_PENDING; |
| 138 | 1386 if (context->cd & 1) { |
|
54
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|
1387 return 0; |
|
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|
1388 } |
|
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|
1389 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
|
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|
1390 context->flags &= ~FLAG_UNUSED_SLOT; |
|
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|
1391 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
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|
1392 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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|
1393 } |
|
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|
1394 uint16_t value = 0; |
| 138 | 1395 switch (context->cd & 0xF) |
|
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|
1396 { |
|
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|
1397 case VRAM_READ: |
|
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|
1398 value = context->vdpmem[context->address] << 8; |
|
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|
1399 context->flags &= ~FLAG_UNUSED_SLOT; |
|
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|
1400 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
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|
1401 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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|
1402 } |
|
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|
1403 value |= context->vdpmem[context->address ^ 1]; |
|
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|
1404 break; |
|
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|
1405 case CRAM_READ: |
|
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|
1406 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
|
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|
1407 break; |
|
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|
1408 case VSRAM_READ: |
|
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|
1409 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
|
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|
1410 value = context->vsram[context->address & 63]; |
|
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|
1411 } |
|
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|
1412 break; |
|
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|
1413 } |
|
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|
1414 context->address += context->regs[REG_AUTOINC]; |
|
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|
1415 return value; |
|
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|
1416 } |
|
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|
1417 |
| 137 | 1418 uint16_t vdp_hv_counter_read(vdp_context * context) |
| 1419 { | |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1420 //TODO: deal with clock adjustemnts handled in vdp_run_context |
| 137 | 1421 uint32_t line= context->cycles / MCLKS_LINE; |
| 1422 if (!line) { | |
| 1423 line = 0xFF; | |
| 1424 } else { | |
| 1425 line--; | |
| 1426 if (line > 0xEA) { | |
| 1427 line = (line + 0xFA) & 0xFF; | |
| 1428 } | |
| 1429 } | |
| 1430 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
| 1431 if (context->latched_mode & BIT_H40) { | |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1432 uint32_t slot; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1433 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1434 slot = linecyc/MCLKS_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1435 } else if(linecyc < MCLK_WEIRD_END) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1436 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1437 { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1438 case 0: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1439 slot = 0; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1440 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1441 case 19: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1442 slot = 1; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1443 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1444 case 39: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1445 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1446 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1447 case 59: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1448 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1449 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1450 case 79: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1451 slot = 3; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1452 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1453 case 97: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1454 slot = 4; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1455 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1456 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1457 slot = 5; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1458 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1459 case 137: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1460 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1461 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1462 case 157: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1463 slot = 7; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1464 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1465 case 175: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1466 slot = 8; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1467 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1468 case 195: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1469 slot = 9; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1470 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1471 case 215: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1472 slot = 11; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1473 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1474 case 235: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1475 slot = 12; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1476 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1477 case 253: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1478 slot = 13; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1479 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1480 case 273: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1481 slot = 14; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1482 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1483 case 293: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1484 slot = 15; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1485 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1486 case 313: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1487 slot = 16; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1488 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1489 default: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1490 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1491 exit(1); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1492 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1493 slot += HSYNC_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1494 } else { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1495 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1496 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1497 linecyc = slot * 2; |
| 137 | 1498 if (linecyc >= 86) { |
| 1499 linecyc -= 86; | |
| 1500 } else { | |
| 1501 linecyc += 334; | |
| 1502 } | |
| 1503 if (linecyc > 0x16C) { | |
| 1504 linecyc += 92; | |
| 1505 } | |
| 1506 } else { | |
| 1507 linecyc /= 10; | |
| 1508 if (linecyc >= 74) { | |
| 1509 linecyc -= 74; | |
| 1510 } else { | |
| 1511 linecyc += 268; | |
| 1512 } | |
| 1513 if (linecyc > 0x127) { | |
| 1514 linecyc += 170; | |
| 1515 } | |
| 1516 } | |
| 1517 linecyc &= 0xFF; | |
| 1518 return (line << 8) | linecyc; | |
| 1519 } | |
| 1520 | |
|
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1521 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1522 { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1523 context->cycles -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1524 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1525 if (start->cycle >= deduction) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1526 start->cycle -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1527 } else { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1528 start->cycle = 0; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1529 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1530 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1531 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1532 |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1533 uint32_t vdp_next_hint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1534 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1535 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1536 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1537 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1538 if (context->flags2 & FLAG2_HINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1539 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1540 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1541 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1542 uint32_t line = context->cycles / MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1543 if (line >= active_lines) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1544 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1545 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1546 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1547 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1548 if (!line) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1549 hcycle += MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1550 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1551 return hcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1552 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1553 |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1554 uint32_t vdp_next_vint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1555 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1556 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1557 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1558 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1559 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1560 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1561 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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1562 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
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1563 uint32_t vcycle = MCLKS_LINE * active_lines; |
|
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1564 if (context->latched_mode & BIT_H40) { |
|
331
de17e0352f27
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1565 vcycle += VINT_CYCLE_H40; |
|
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1566 } else { |
|
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1567 vcycle += VINT_CYCLE_H32; |
|
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1568 } |
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|
1569 if (vcycle < context->cycles) { |
|
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1570 return 0xFFFFFFFF; |
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1571 } |
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|
1572 return vcycle; |
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|
1573 } |
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|
1574 |
| 333 | 1575 uint32_t vdp_next_vint_z80(vdp_context * context) |
| 1576 { | |
| 1577 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
| 1578 uint32_t vcycle = MCLKS_LINE * active_lines; | |
| 1579 if (context->latched_mode & BIT_H40) { | |
| 1580 vcycle += VINT_CYCLE_H40; | |
| 1581 } else { | |
| 1582 vcycle += VINT_CYCLE_H32; | |
| 1583 } | |
| 1584 return vcycle; | |
| 1585 } | |
| 1586 | |
|
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|
1587 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
|
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|
1588 { |
|
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|
1589 if (int_num == 6) { |
|
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|
1590 context->flags2 &= ~FLAG2_VINT_PENDING; |
|
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|
1591 } else if(int_num ==4) { |
|
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|
1592 context->flags2 &= ~FLAG2_HINT_PENDING; |
|
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|
1593 } |
|
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|
1594 } |
|
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|
1595 |
|
20
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|
1596 #define GST_VDP_REGS 0xFA |
|
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Mostly broken VDP core and savestate viewer
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diff
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|
1597 #define GST_VDP_MEM 0x12478 |
|
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diff
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|
1598 |
|
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diff
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|
1599 void vdp_load_savestate(vdp_context * context, FILE * state_file) |
|
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|
1600 { |
|
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|
1601 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
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Mostly broken VDP core and savestate viewer
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|
1602 fseek(state_file, GST_VDP_REGS, SEEK_SET); |
|
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Mostly broken VDP core and savestate viewer
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diff
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|
1603 fread(context->regs, 1, VDP_REGS, state_file); |
|
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|
1604 latch_mode(context); |
|
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Mostly broken VDP core and savestate viewer
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diff
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|
1605 fread(tmp_buf, 1, sizeof(tmp_buf), state_file); |
|
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diff
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|
1606 for (int i = 0; i < CRAM_SIZE; i++) { |
|
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diff
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|
1607 context->cram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
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|
1608 } |
|
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|
1609 fread(tmp_buf, 2, VSRAM_SIZE, state_file); |
|
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diff
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|
1610 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
23
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Fix endianness of VSRAM when read from Genecyst save state
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diff
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|
1611 context->vsram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
20
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|
1612 } |
|
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|
1613 fseek(state_file, GST_VDP_MEM, SEEK_SET); |
|
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diff
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|
1614 fread(context->vdpmem, 1, VRAM_SIZE, state_file); |
|
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diff
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|
1615 } |
|
54
3b79cbcf6846
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diff
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|
1616 |
|
56
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diff
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|
1617 void vdp_save_state(vdp_context * context, FILE * outfile) |
|
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diff
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|
1618 { |
|
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diff
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|
1619 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
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|
1620 fseek(outfile, GST_VDP_REGS, SEEK_SET); |
|
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diff
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|
1621 fwrite(context->regs, 1, VDP_REGS, outfile); |
|
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diff
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|
1622 for (int i = 0; i < CRAM_SIZE; i++) { |
|
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diff
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|
1623 tmp_buf[i*2] = context->cram[i]; |
|
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|
1624 tmp_buf[i*2+1] = context->cram[i] >> 8; |
|
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diff
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|
1625 } |
|
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diff
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|
1626 fwrite(tmp_buf, 1, sizeof(tmp_buf), outfile); |
|
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diff
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|
1627 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
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diff
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|
1628 tmp_buf[i*2] = context->vsram[i]; |
|
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|
1629 tmp_buf[i*2+1] = context->vsram[i] >> 8; |
|
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|
1630 } |
|
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diff
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|
1631 fwrite(tmp_buf, 2, VSRAM_SIZE, outfile); |
|
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|
1632 fseek(outfile, GST_VDP_MEM, SEEK_SET); |
|
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|
1633 fwrite(context->vdpmem, 1, VRAM_SIZE, outfile); |
|
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54
diff
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|
1634 } |
|
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|
1635 |