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Fix bug in MED mapper protection bit implementation
author Michael Pavone <pavone@retrodev.com>
date Sun, 28 Apr 2024 23:33:11 -0700
parents 461fffc226e0
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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1 info
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2 prefix z80_
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3 opcode_size 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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4 extra_tables cb ed dded fded ddcb fdcb dd fd
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5 body z80_run_op
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6 sync_cycle z80_sync_cycle
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7 interrupt z80_interrupt
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8 include z80_util.c
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9 header z80.h
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10
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11 declare
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
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12 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider, uint32_t io_address_mask);
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
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13 z80_context * init_z80_context(z80_options *options);
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14 void z80_run(z80_context *context, uint32_t target_cycle);
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15 void z80_assert_reset(z80_context * context, uint32_t cycle);
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16 void z80_clear_reset(z80_context * context, uint32_t cycle);
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17 void z80_assert_busreq(z80_context * context, uint32_t cycle);
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18 void z80_clear_busreq(z80_context * context, uint32_t cycle);
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19 void z80_assert_nmi(z80_context *context, uint32_t cycle);
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20 uint8_t z80_get_busack(z80_context * context, uint32_t cycle);
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21 void z80_invalidate_code_range(z80_context *context, uint32_t start, uint32_t end);
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22 void z80_adjust_cycles(z80_context * context, uint32_t deduction);
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23 void z80_serialize(z80_context *context, serialize_buffer *buf);
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24 void z80_deserialize(deserialize_buffer *buf, void *vcontext);
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25 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler);
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26 void zremove_breakpoint(z80_context * context, uint16_t address);
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27 void z80_options_free(z80_options *opts);
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6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
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28 void z80_sync_cycle(z80_context *context, uint32_t target_cycle);
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29
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30 regs
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31 main 8 b c d e h l f a
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32 alt 8 b' c' d' e' h' l' f' a'
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33 i 8
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34 r 8
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35 rhigh 8
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36 iff1 8
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37 iff2 8
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38 imode 8
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39 sp 16
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40 ix 16
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41 iy 16
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42 pc 16
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43 wz 16
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44 nflag 8
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45 last_flag_result 8
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46 pvflag 8
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47 chflags 8
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48 zflag 8
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49 scratch1 16
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50 scratch2 16
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51 busreq 8
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52 busack 8
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53 reset 8
1735
ca2336469397 Get new Z80 core running in CPM harness
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54 io_map ptrmemmap_chunk
ca2336469397 Get new Z80 core running in CPM harness
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55 io_chunks 32
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56 io_mask 32
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57 int_cycle 32
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58 int_end_cycle 32
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59 int_value 8
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60 nmi_cycle 32
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61 system ptrvoid
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62 fastread ptr8 64
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63 fastwrite ptr8 64
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64 mem_pointers ptr8 4
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65
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66 flags
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67 register f
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68 S 7 sign last_flag_result.7
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69 Z 6 zero zflag
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70 Y 5 bit-5 last_flag_result.5
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71 H 4 half-carry chflags.3
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72 P 2 parity pvflag
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73 V 2 overflow pvflag
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74 X 3 bit-3 last_flag_result.3
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75 N 1 none nflag
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76 C 0 carry chflags.7
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77
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78
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79 z80_op_fetch
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80 cycles 1
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81 r += 1
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82 scratch1 = pc
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83 ocall read_8
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84 pc += 1
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85
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86 z80_run_op
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1dc718581aac Fix Z80 interrupts in Gen/MD mode when using new core. Disable CPU debug log in new Z80 core
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87 #printf "Z80: %X @ %d\n" pc cycles
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093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
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88 #printf "Z80: %X - A: %X, B: %X, C: %X D: %X, E: %X, H: %X, L: %X, SP: %X, IX: %X, IY: %X @ %d\n" pc a b c d e h l sp ix iy cycles
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89 z80_op_fetch
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90 dispatch scratch1
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91
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92 z80_interrupt
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93 if cycles >=U int_cycle
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94
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95 iff1 = 0
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96 iff2 = 0
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97 cycles 6
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98 update_sync
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99
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100 switch imode
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101 case 0
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102 dispatch int_value
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103
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104 case 1
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105 dispatch 0xFF
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106
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107 case 2
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108 pc = i << 8
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109 pc |= int_value
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110 #CD is call
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111 dispatch 0xCD
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112 end
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113
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114 else
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115 if cycles >=U nmi_cycle
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116
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117 nmi_cycle = 0xFFFFFFFF
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118 iff1 = 0
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119 local pch 8
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120 pch = pc >> 8
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121 meta high pch
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122 meta low pc
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123 z80_push
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124 pc = 0x66
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125 update_sync
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126
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127 end
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128 end
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
129
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
130
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
131 11001011 cb_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 dispatch scratch1 cb
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 11011101 dd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137 dispatch scratch1 dd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138
1712
0a9a88b3d061 Fix ED prefix in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1706
diff changeset
139 11101101 ed_prefix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141 dispatch scratch1 ed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 11111101 fd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145 dispatch scratch1 fd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
147 dd 11001011 ddcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
148 z80_calc_index ix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
149 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
150 scratch1 = pc
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
151 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
152 pc += 1
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
153 dispatch scratch1 ddcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
154
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
155 fd 11001011 fdcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
156 z80_calc_index iy
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
157 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
158 scratch1 = pc
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
159 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
160 pc += 1
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
161 dispatch scratch1 fdcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
162
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 z80_check_cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 arg cond 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 local invert 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 switch cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 case 0
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
168 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
169 invert = !zflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 case 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
172 meta istrue zflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 case 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
175 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
176 invert = ~chflags
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
177 invert &= 0x80
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 case 3
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
180 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
181 invert = chflags & 0x80
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183 case 4
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
184 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
185 invert = !pvflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187 case 5
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
188 meta istrue pvflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 case 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
191 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
192 invert = ~last_flag_result
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
193 invert &= 0x80
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 case 7
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
196 meta istrue invert
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
197 invert = 0x80 & last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 z80_fetch_hl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
201 scratch1 = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
202 scratch1 |= l
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 z80_store_hl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
206 scratch2 = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
207 scratch2 |= l
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
211 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
213 pc += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
216 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
218 wz = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
219 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
220 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
222 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
223 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
224 wz |= scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 z80_fetch_immed_reg16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
227 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
229 low = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
230 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
231 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
233 high = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
234 pc += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 z80_fetch_immed_to_reg16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
237 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
239 reg = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
240 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
241 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
243 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
244 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
245 reg |= scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 z80_fetch_hl
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
249 main.R = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 01DDDSSS ld_from_reg
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
252 main.D = main.S
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
254 dd 01DDD100 ld_from_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
255 invalid D 6
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
256 main.D = ix >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
257
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
258 dd 01100SSS ld_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
259 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
260 local tmp 16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
261 ix &= 0xFF
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
262 tmp = main.S << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
263 ix |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
264
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
265 dd 0110D10S ld_ixb_to_ixb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
266
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
267 dd 01DDD101 ld_from_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
268 invalid D 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
269 main.D = ix
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
270
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
271 dd 01101SSS ld_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
272 invalid S 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
273 ix &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
274 ix |= main.S
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
275
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
276 dd 01100101 ld_ixl_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
277 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
278 tmp = ix << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
279 ix &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
280 ix |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
281
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
282 dd 01101100 ld_ixh_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
283 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
284 tmp = ix >> 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
285 ix &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
286 ix |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
287
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
288 fd 01DDD100 ld_from_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
289 invalid D 6
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
290 main.D = iy >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
291
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
292 fd 01100SSS ld_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
293 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
294 local tmp 16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
295 iy &= 0xFF
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
296 tmp = main.S << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
297 iy |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
298
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
299 fd 0110D10S ld_iyb_to_iyb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
300
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
301 fd 01DDD101 ld_from_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
302 invalid D 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
303 main.D = iy
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
304
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
305 fd 01101SSS ld_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
306 invalid S 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
307 iy &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
308 iy |= main.S
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
309
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
310 fd 01100101 ld_iyl_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
311 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
312 tmp = iy << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
313 iy &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
314 iy |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
315
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
316 fd 01101100 ld_iyh_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
317 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
318 tmp = iy >> 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
319 iy &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
320 iy |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
321
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
322 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
323 arg index 16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
324 wz = index
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
325 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
326 sext 16 scratch1 scratch1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
327 wz += scratch1
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
328
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
329 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
330 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
331 z80_calc_index index
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
332 scratch1 = wz
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
333 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
334 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
335
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
336 z80_store_index
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
337 scratch2 = wz
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
338 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
339
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 dd 01RRR110 ld_from_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
341 z80_fetch_index ix
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
342 main.R = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 fd 01RRR110 ld_from_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
345 z80_fetch_index iy
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
346 main.R = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
350 main.R = scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
351
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
352 dd 00100110 ld_immed_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
353 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
354 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
355 ix &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
356 ix |= scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
357
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
358 dd 00101110 ld_immed_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
359 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
360 ix &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
361 ix |= scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
362
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
363 fd 00100110 ld_immed_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
364 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
365 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
366 iy &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
367 iy |= scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
368
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
369 fd 00101110 ld_immed_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
370 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
371 iy &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
372 iy |= scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 01110RRR ld_to_hl
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
375 scratch1 = main.R
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 dd 01110RRR ld_to_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
379 z80_calc_index ix
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
380 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
381 scratch1 = main.R
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
382 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 fd 01110RRR ld_to_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
386 z80_calc_index iy
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
387 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
388 scratch1 = main.R
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
389 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 z80_store_hl
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
395
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
396 dd 00110110 ld_to_ixd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
397 z80_calc_index ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
398 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
399 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
400 scratch2 = wz
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
401 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
402
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
403 fd 00110110 ld_to_iyd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
404 z80_calc_index iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
405 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
406 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
407 scratch2 = wz
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
408 ocall write_8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 00001010 ld_a_from_bc
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
411 wz = b << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
412 wz |= c
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
413 scratch1 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
414 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
416 a = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 00011010 ld_a_from_de
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
419 wz = d << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
420 wz |= e
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
421 scratch1 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
422 wz += 1
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
423 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
424 a = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
428 scratch1 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
429 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
431 a = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 00000010 ld_a_to_bc
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
434 local tmp 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
435 scratch2 = b << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
436 scratch2 |= c
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
437 scratch1 = a
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
438 tmp = c + 1
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
439 wz = a << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
440 wz |= tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 00010010 ld_a_to_de
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
444 local tmp 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
445 scratch2 = d << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
446 scratch2 |= e
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
447 scratch1 = a
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
448 tmp = e + 1
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
449 wz = a << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
450 wz |= tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 00110010 ld_a_to_immed
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
454 local tmp 16
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
456 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
457 scratch1 = a
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
458 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
460 wz &= 0xFF
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
461 tmp = a << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
462 wz |= tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 ed 01000111 ld_i_a
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
465 i = a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 ed 01001111 ld_r_a
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
469 r = a
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
470 rhigh = 0x80 & a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
473 ed 01011111 ld_a_r
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
474 cycles 1
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
475 a = 0x7F & r
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
476 a |= rhigh
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
477 update_flags SZYH0XN0
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
478 pvflag = iff2
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
479
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
480 ed 01010111 ld_a_i
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
481 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
482 a = i
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
483 update_flags SZYH0XN0
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
484 pvflag = iff2
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
485
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
515 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
517 low = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
518 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
519 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
521 high = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
522 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 meta low e
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
536 meta high d
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
546 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
548 reg = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
549 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
550 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
552 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
553 reg |= scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
554 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
570 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
571 scratch1 = l
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
573 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
574 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
575 scratch1 = h
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
577 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
579 dd 00100010 ld_ix_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
580 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
581 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
582 scratch1 = ix
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
583 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
584 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
585 scratch2 = wz
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
586 scratch1 = ix >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
587 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
588 wz += 1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
589
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
590 fd 00100010 ld_iy_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
591 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
592 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
593 scratch1 = iy
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
594 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
595 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
596 scratch2 = wz
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
597 scratch1 = iy >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
598 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
599 wz += 1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
600
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
603 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
604 scratch1 = low
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
606 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
607 scratch1 = high
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
608 scratch2 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
610 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 local sph 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
630 sph = sp >> 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
636 sp = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
637 sp |= l
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
638
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
639 dd 11111001 ld_sp_ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
640 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
641 sp = ix
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
642
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
643 fd 11111001 ld_sp_iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
644 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
645 sp = iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
649 sp -= 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
650 scratch2 = sp
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
651 scratch1 = high
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
653 sp -= 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
654 scratch2 = sp
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
655 scratch1 = low
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 local ixh 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
680 ixh = ix >> 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 local iyh 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
687 iyh = iy >> 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
695 sp += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
696 low = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
697 scratch1 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
698 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
699 sp += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
700 high = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
701
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
702 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
703 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
704 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
705 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
707 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
708 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
709 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
710 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
711
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
712 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
713 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
714 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
715 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
716
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
717 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
718 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
719 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
720 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
721
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
722 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
723 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
724 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
725 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
726 z80_pop
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
727 ixh <<= 8
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
728 ix |= ixh
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
730 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 z80_pop
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
735 iyh <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
736 iy |= iyh
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
737
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
738 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
739 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
740 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
741
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
742 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
743 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
744 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
745
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
746 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
747 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
748 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
749 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
750 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
751 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
752 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754 11100011 ex_sp_hl
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
755 scratch1 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
758 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
759 scratch2 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
760 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
761 scratch1 = sp + 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
762 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
763 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
764 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
765 scratch2 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
766 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
767 wz = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
768 wz |= l
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
769
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
770 dd 11100011 ex_sp_ix
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
771 scratch1 = sp
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
772 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
773 wz = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
774 scratch1 = ix
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
775 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
776 scratch2 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
777 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
778 scratch1 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
779 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
780 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
781 wz |= scratch1
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
782 scratch1 = ix >> 8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
783 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
784 scratch2 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
785 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
786 ix = wz
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
787
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
788 fd 11100011 ex_sp_iy
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
789 scratch1 = sp
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
790 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
791 wz = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
792 scratch1 = iy
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
793 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
794 scratch2 = sp
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
795 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
796 scratch1 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
797 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
798 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
799 wz |= scratch1
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
800 scratch1 = iy >> 8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
801 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
802 scratch2 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
803 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
804 iy = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
805
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
806 10000RRR add_reg
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
807 a += main.R
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
808 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
809
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
810 dd 10000100 add_ixh
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
811 scratch1 = ix >> 8
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
812 a += scratch1
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
813 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
814
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
815 dd 10000101 add_ixl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
816 scratch1 = ix & 0xFF
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
817 a += scratch1
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
818 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
819
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
820 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
821 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
822 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
823 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
824
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
825 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
826 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
827 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
828 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
829
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
830 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
831 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
832 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
833 update_flags SZYHVXN0C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
834
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
835 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
836 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
837 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
838 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
839
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
840 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
841 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
842 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
843 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
844
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
845 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
846 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
847 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
848 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
849
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
850 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
851 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
852 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
853 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
854 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
855 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
856 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
857 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
858 lsr hlt 8 h
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
859 cycles 7
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
860
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
861 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
862 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
863 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
864 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
865 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
866 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
867 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
868
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
869 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
870 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
871 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
872 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
873 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
874 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
875 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
876
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
877 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
878 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
879 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
880 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
881
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
882 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
883 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
884 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
885 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
886
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
887 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
888 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
889 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
890 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
891 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
892 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
893
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
894 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
895 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
896 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
897 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
898 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
899 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
900
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
901 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
902 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
903 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
904 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
905
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
906 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
907 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
908 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
909 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
910
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
911 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
912 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
913 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
914 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
915 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
916 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
917
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
918 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
919 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
920 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
921 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
922 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
923 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
924
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
925 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
926 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
927 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
928 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
929
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
930 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
931 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
932 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
933 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
934
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
935 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
936 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
937 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
938
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
939 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
940 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
941 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
942 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
943
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
944 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
945 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
946 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
947 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
948
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
949 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
950 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
951 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
952 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
953
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
954 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
955 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
956 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
957 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
958
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
959 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
960 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
961 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
962 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
963
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
964 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
965 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
966 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
967 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
968
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
969 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
970 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
971 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
972 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
973
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
974 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
975 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
976 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977 update_flags SZYHVXN0C
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
978
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
979 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
980 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
981 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
982 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
983 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
984 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
985 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
986 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
987 lsr hlt 8 h
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
988 cycles 7
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
989
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
990 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
991 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
992 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
993 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
994 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
995 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
996 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
997
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
998 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
999 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1000 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1001 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1002 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1003 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1004 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1005
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1006 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1007 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1008 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1009 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1010
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1011
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1012 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1013 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1014 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1015 z80_adc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1016
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1017 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1019 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1020
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1021 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1022 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1023 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1024 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1025
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1026 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1027 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1028 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1029 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1030
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1031 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1032 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1033 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1034 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1035
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1036 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1037 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1038 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1039 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1040
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1041 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1042 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1043 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1044 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1045
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1046 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1047 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1048 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1049 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1050
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1051 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1052 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1053 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1054 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1055
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1056 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1057 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1061 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1064
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1065 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1066 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1067 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1068 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1069
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1070 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1071 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1072 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1073 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1074
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1075 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1076 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1077 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1078 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1079
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1080 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1081 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1082 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1083 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1084
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1085
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1086 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1087 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1088 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1089 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1090
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1091 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1092 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1093 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1094 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1095
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1096 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1097 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1098 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1099 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1100
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1101 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1102 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1103 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1104 update_flags SZYHVXN1C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1105
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1106 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1107 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1108 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1109 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1110 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1111 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1112 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1113 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1114 lsr hlt 8 h
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1115 cycles 7
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1116
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1117 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1118 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1119 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1120 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1121 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1122 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1123 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1124
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1125 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1126 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1127 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1128 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1129 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1130 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1131 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1132
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1133 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1134 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1135 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1136 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1137
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1138
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1139 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1140 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1141 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1142 z80_sbc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1143
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1144 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1145 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1146 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1147
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1148 dd 10100100 and_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1149 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1150 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1151 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1152
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1153 dd 10100101 and_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1154 and ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1155 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1156
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1157 fd 10100100 and_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1158 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1159 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1160 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1161
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1162 fd 10100101 and_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1163 and iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1164 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1165
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1166 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1168 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1169 update_flags SZYH1PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1170
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1171 dd 10100110 and_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1172 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1173 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1174 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1175
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1176 fd 10100110 and_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1177 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1178 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1179 update_flags SZYH1PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1180
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1181 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1182 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1183 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1184 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1185
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1186 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1187 or a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1188 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1189
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1190 dd 10110100 or_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1191 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1192 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1193 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1194
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1195 dd 10110101 or_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1196 or ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1197 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1198
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1199 fd 10110100 or_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1200 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1201 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1202 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1203
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1204 fd 10110101 or_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1205 or iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1206 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1207
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1208 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1209 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1210 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1211 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1212
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1213 dd 10110110 or_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1214 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1215 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1216 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1217
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1218 fd 10110110 or_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1219 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1220 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1221 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1222
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1223 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1224 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1225 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1226 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1227
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1228 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1229 xor a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1230 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1231
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1232 dd 10101100 xor_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1233 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1234 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1235 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1236
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1237 dd 10101101 xor_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1238 xor ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1239 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1240
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1241 fd 10101100 xor_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1242 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1243 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1244 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1245
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1246 fd 10101101 xor_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1247 xor iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1248 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1249
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1250 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1251 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1252 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1253 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1254
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1255 dd 10101110 xor_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1256 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1257 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1258 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1259
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1260 fd 10101110 xor_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1261 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1262 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1263 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1264
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1265 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1266 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1267 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1268 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1269
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1270 10111RRR cp_reg
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1271 mov main.R last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1272 cmp main.R a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1273 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1274
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1275 dd 10111100 cp_ixh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1276 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1277 lsr ix 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1278 mov tmp last_flag_result
1743
a1663a83dcab Fixed cp ixh in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1742
diff changeset
1279 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1280 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1281
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1282 dd 10111101 cp_ixl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1283 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1284 mov ix tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1285 mov ix last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1286 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1287 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1288
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1289 fd 10111100 cp_iyh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1290 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1291 lsr iy 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1292 mov tmp last_flag_result
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1293 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1294 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1295
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1296 fd 10111101 cp_iyl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1297 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1298 mov iy tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1299 mov iy last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1300 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1301 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1302
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1303 10111110 cp_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1304 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1305 z80_fetch_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1306 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1307 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1308 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1309 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1310
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1311 dd 10111110 cp_ixd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1312 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1313 z80_fetch_index ix
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1314 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1315 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1316 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1317 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1318
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1319 fd 10111110 cp_iyd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1320 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1321 z80_fetch_index iy
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1322 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1323 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1324 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1325 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1326
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1327 11111110 cp_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1328 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1329 z80_fetch_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1330 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1331 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1332 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1333 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1334
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1335 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1336 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1337 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1338
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1339 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1340 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1341 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1342
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1343 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1344 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1345 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1346 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1347 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1348 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1349 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1350
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1351 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1352 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1353 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1354
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1355 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1356 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1357 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1358 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1359 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1360 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1361 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1362
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1363 00110100 inc_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1364 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1365 z80_fetch_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1366 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1367 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1368 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1369 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1370 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1371 mov tmp scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1372 cycles 1
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1373 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1374
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1375 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1376 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1377 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1378 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1379 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1380 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1381 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1382 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1383 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1384 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1385 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1386
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1387 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1388 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1389 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1390 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1391 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1392 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1393 add 1 tmp tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1394 update_flags SZYHVXN0
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1395 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1396 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1397 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1398
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1399 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1400 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1401 arg low 8
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
1402 cycles 2
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1403 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1404 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1405 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1406 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1407 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1408 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1409
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1410 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1411 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1412
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1413 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1414 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1415
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1416 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1417 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1418
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1419 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1420 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1421
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1422 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1423 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1424
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1425 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1426 add 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1427
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1428 00RRR101 dec_reg
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1429 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1430 update_flags SZYHVXN1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1431
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1432 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1433 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1434 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1435
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1436 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1437 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1438 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1439 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1440 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1441 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1442 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1443
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1444 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1445 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1446 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1447
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1448 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1449 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1450 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1451 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1452 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1453 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1454 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1455
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1456 00110101 dec_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1457 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1458 z80_fetch_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1459 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1460 #or add some syntax to force a certain size on an operation so they are unnecessary
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1461 mov scratch1 tmp
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1462 sub 1 tmp tmp
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1463 update_flags SZYHVXN1
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1464 mov tmp scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1465 cycles 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1466 z80_store_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1467
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1468 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1469 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1470 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1471 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1472 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1473 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1474 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1475 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1476 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1477 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1478 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1479
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1480 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1481 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1482 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1483 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1484 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1485 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1486 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1487 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1488 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1489 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1490 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1491
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1492 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1493 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1494 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1495 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1496 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1497 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1498 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1499 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1500 lsr word 8 high
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
1501 cycles 2
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1502
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1503 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1504 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1505
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1506 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1507 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1508
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1509 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1510 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1511
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1512 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1513 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1514
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1515 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1516 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1517
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1518 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1519 sub 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1520
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1521 00101111 cpl
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
1522 a = ~a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1523 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1524
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1525 ed 01DDD100 neg
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
1526 a = -a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1527 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1528
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1529 00111111 ccf
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1530 local tmp 8
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1531 and 0x80 last_flag_result last_flag_result
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1532 and 0x7F a tmp
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1533 or tmp last_flag_result last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1534 and 0x80 chflags chflags
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1535 lsr chflags 4 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1536 or tmp chflags chflags
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1537 xor 0x80 chflags chflags
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1538 update_flags N0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1539
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1540 00110111 scf
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1541 local tmp 8
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1542 and 0x80 last_flag_result last_flag_result
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1543 and 0x7F a tmp
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1544 or tmp last_flag_result last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1545 update_flags H0N0C1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1546
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1547 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1548
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1549 01110110 halt
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1550 cmp nmi_cycle cycles
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1551 if cycles >=U nmi_cycle
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1552
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1553 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1554 if cycles >=U int_cycle
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1555
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1556 if iff1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1557 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1558 pc -= 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1559 end
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1560
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1561 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1562 pc -= 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1563 end
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1564 end
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1565
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1566 11110011 di
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1567 iff1 = 0
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1568 iff2 = 0
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1569 update_sync
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1570
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1571 11111011 ei
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1572 iff1 = 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1573 iff2 = 1
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1574 update_sync
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1575
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1576 if cycles >=U int_cycle
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1577 int_cycle = cycles + 1
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1578 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1579
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1580 ed 01D00110 im0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1581 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1582
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1583 ed 01D10110 im1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1584 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1585
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1586 ed 01D11110 im2
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1587 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1588
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1589 ed 01D01110 im3
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1590 #some sources call this mode 0/1, but unclear
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1591 #if the behavior is really different from im 0
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1592 mov 0 imode
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1593
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1594 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1595 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1596 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1597
1726
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1598 11101001 jp_hl
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1599 lsl h 8 pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1600 or l pc pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1601
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1602 dd 11101001 jp_ix
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1603 mov ix pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1604
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1605 fd 11101001 jp_iy
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1606 mov iy pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1607
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1608 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1609 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1610 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1611 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1612 pc = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1613 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1614
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1615 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1616 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1617 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1618 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1619 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1620 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1621
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1622 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1623 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1624 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1625
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1626 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1627 sext 16 scratch1 scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1628 pc += scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1629 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1630 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1631
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1632 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1633 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1634 z80_fetch_immed
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1635 b -= 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1636
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1637 if b
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1638 sext 16 scratch1 scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1639 pc += scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1640 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1641 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1642
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1643
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1644 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1645 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1646 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1647 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1648 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1649 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1650 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1651 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1652
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1653 11CCC100 call_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1654 local pch 8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1655 z80_fetch_immed16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1656 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1657
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1658 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1659 pch = pc >> 8
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1660 meta high pch
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1661 meta low pc
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1662 z80_push
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1663 pc = wz
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1664 end
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1665
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1666 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1667 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1668 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1669 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1670 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1671 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1672 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1673 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1674
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1675 11001001 ret
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1676 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1677 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1678 meta low pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1679 z80_pop
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1680 lsl pch 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1681 or pch pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1682
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1683 ed 01001101 reti
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1684 local pch 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1685 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1686 meta high pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1687 meta low pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1688 z80_pop
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1689 lsl pch 8 pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1690 or pch pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1691
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1692 ed 01NN1101 retn
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1693 mov iff2 iff1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1694 local pch 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1695 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1696 meta high pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1697 meta low pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1698 z80_pop
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1699 lsl pch 8 pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1700 or pch pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1701
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1702 11CCC000 ret_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1703 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1704 cycles 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1705 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1706 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1707 meta high pch
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1708 meta low pc
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1709 z80_pop
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1710 pch = pch << 8
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1711 pc |= pch
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1712 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1713
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1714 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1715 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1716 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1717 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1718
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1719 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1720 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1721 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1722 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1723 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1724
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1725 z80_ini_ind
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1726 arg change 16
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1727 local tmp 8
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1728 cycles 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1729
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1730 lsl 8 b wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1731 or c wz wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1732 add change wz wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1733
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1734 sub 1 b b
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1735 update_flags SZYX
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1736
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1737 lsl b 8 scratch1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1738 or c scratch1 scratch1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1739 ocall io_read8
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1740
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1741 and 0x80 scratch1 nflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1742
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1743 mov wz tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1744 add tmp scratch1 tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1745 update_flags C
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1746
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1747 z80_store_hl
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1748
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1749 lsl h 8 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1750 or l scratch2 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1751 add change scratch2 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1752 mov scratch2 l
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1753 lsr scratch2 8 h
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1754
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1755 and 7 tmp tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1756 xor b tmp tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1757 update_flags P
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1758 lsr chflags 4 tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1759 or tmp chflags chflags
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1760
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1761 ed 10100010 ini
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1762 z80_ini_ind 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1763
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1764 ed 10110010 inir
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1765 z80_ini_ind 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1766 if zflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1767 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1768 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1769 cycles 5
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1770 end
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1771
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1772 ed 10101010 ind
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1773 z80_ini_ind -1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1774
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1775 ed 10111010 indr
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1776 z80_ini_ind -1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1777 if zflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1778 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1779 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1780 cycles 5
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1781 end
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1782
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1783 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1784 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1785 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1786 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1787 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1788
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1789 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1790 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1791 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1792 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1793 ocall io_write8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1794
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1795 z80_outi_outd
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1796 arg change 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1797 local tmp 8
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1798 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1799 z80_fetch_hl
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1800
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1801 and 0x80 scratch1 nflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1802
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1803 lsl h 8 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1804 or l scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1805 add change scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1806 mov scratch2 l
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1807 lsr scratch2 8 h
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1808
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1809 add l scratch1 tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1810 update_flags C
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1811 and 7 tmp tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1812
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1813 lsl b 8 scratch2
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1814 or c scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1815 ocall io_write8
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1816
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1817 sub 1 b b
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1818 update_flags SZYX
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1819
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1820 lsl 8 b wz
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1821 or c wz wz
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1822 add change wz wz
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1823
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1824 xor b tmp tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1825 update_flags P
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1826 lsr chflags 4 tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1827 or tmp chflags chflags
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1828
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1829 ed 10100011 outi
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1830 z80_outi_outd 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1831
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1832 ed 10110011 otir
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1833 z80_outi_outd 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1834 if zflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1835 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1836 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1837 cycles 5
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1838 end
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1839
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1840 ed 10101011 outd
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1841 z80_outi_outd -1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1842
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1843 ed 10111011 otdr
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1844 z80_outi_outd -1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1845 if zflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1846 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1847 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1848 cycles 5
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1849 end
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1850
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1851 00000111 rlca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1852 rol a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1853 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1854
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1855 00010111 rla
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1856 rlc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1857 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1858
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1859 00001111 rrca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1860 ror a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1861 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1862
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1863 00011111 rra
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1864 rrc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1865 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1866
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1867 cb 00000RRR rlc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1868 rol main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1869 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1870
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1871 cb 00000110 rlc_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1872 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1873 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1874 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1875 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1876 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1877 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1878 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1879
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1880 z80_rlc_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1881 arg tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1882 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1883 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1884 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1885 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1886 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1887 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1888 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1889 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1890
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1891 ddcb 00000110 rlc_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1892 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1893 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1894
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1895 ddcb 00000RRR rlc_ixd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1896 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1897
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1898 fdcb 00000110 rlc_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1899 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1900 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1901
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1902 fdcb 00000RRR rlc_iyd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1903 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1904
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1905 cb 00010RRR rl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1906 rlc main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1907 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1908
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1909 cb 00010110 rl_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1910 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1911 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1912 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1913 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1914 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1915 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1916 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1917
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1918 z80_rl_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1919 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1920 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1921 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1922 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1923 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1924 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1925 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1926 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1927 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1928
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1929 ddcb 00010110 rl_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1930 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1931 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1932
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1933 fdcb 00010110 rl_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1934 local tmp 8
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1935 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1936
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1937
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1938 ddcb 00010RRR rl_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1939 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1940
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1941 fdcb 00010RRR rl_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1942 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1943
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1944 cb 00001RRR rrc
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1945 ror main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1946 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1947
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1948 cb 00001110 rrc_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1949 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1950 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1951 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1952 ror tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1953 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1954 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1955 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1956
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1957 z80_rrc_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1958 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1959 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1960 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1961 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1962 mov scratch1 tmp
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1963 ror tmp 1 tmp
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1964 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1965 mov tmp scratch1
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1966 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1967
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1968 ddcb 00001110 rrc_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1969 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1970 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1971
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1972 ddcb 00001RRR rrc_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1973 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1974
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1975 fdcb 00001110 rrc_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1976 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1977 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1978
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1979 fdcb 00001RRR rrc_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1980 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1981
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1982 cb 00011RRR rr
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1983 rrc main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1984 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1985
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1986 cb 00011110 rr_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1987 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1988 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1989 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1990 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1991 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1992 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1993 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1994
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1995 z80_rr_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1996 arg tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1997 mov wz scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1998 ocall read_8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1999 cycles 1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2000 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2001 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2002 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2003 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2004 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2005
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2006 ddcb 00011110 rr_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2007 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2008 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2009
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2010 ddcb 00011RRR rr_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2011 z80_rr_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2012
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2013 fdcb 00011110 rr_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2014 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2015 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2016
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2017 fdcb 00011RRR rr_iyd_reg
1723
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2018 z80_rr_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2019
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2020 cb 00100RRR sla
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2021 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2022 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2023
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2024 cb 00100110 sla_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2025 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2026 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2027 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2028 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2029 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2030 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2031 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2032
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2033 z80_sla_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2034 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2035 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2036 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2037 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2038 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2039 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2040 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2041 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2042 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2043
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2044 ddcb 00100110 sla_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2045 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2046 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2047
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2048 ddcb 00100RRR sla_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2049 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2050
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2051 fdcb 00100110 sla_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2052 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2053 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2054
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2055 fdcb 00100RRR sla_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2056 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2057
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2058 cb 00101RRR sra
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2059 asr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2060 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2061
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2062 cb 00101110 sra_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2063 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2064 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2065 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2066 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2067 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2068 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2069 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2070
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2071 z80_sra_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2072 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2073 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2074 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2075 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2076 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2077 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2078 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2079 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2080 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2081
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2082 ddcb 00101110 sra_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2083 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2084 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2085
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2086 ddcb 00101RRR sra_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2087 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2088
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2089 fdcb 00101110 sra_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2090 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2091 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2092
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2093 fdcb 00101RRR sra_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2094 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2095
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2096 cb 00110RRR sll
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2097 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2098 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2099 or 1 main.R main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2100 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2101
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2102 cb 00110110 sll_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2103 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2104 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2105 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2106 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2107 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2108 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2109 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2110 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2111 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2112
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2113 z80_sll_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2114 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2115 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2116 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2117 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2118 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2119 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2120 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2121 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2122 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2123 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2124 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2125
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2126 ddcb 00110110 sll_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2127 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2128 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2129
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2130 ddcb 00110RRR sll_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2131 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2132
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2133 fdcb 00110110 sll_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2134 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2135 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2136
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2137 fdcb 00110RRR sll_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2138 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2139
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2140 cb 00111RRR srl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2141 lsr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2142 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2143
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2144 cb 00111110 srl_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2145 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2146 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2147 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2148 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2149 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2150 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2151 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2152
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2153 z80_srl_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2154 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2155 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2156 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2157 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2158 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2159 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2160 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2161 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2162 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2163
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2164 ddcb 00111110 srl_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2165 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2166 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2167
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2168 ddcb 00111RRR srl_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2169 z80_srl_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2170
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2171 fdcb 00111110 srl_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2172 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2173 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2174
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2175 fdcb 00111RRR srl_iyd_reg
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2176 z80_srl_index main.R
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2177
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2178 cb 01BBBRRR bit_reg
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2179 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2180 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2181 mov main.R last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2182 and main.R tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2183 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2184
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2185 cb 01BBB110 bit_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2186 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2187 z80_fetch_hl
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
2188 cycles 1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2189 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2190 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2191 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2192 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2193
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2194
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2195 ddcb 01BBBRRR bit_ixd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2196 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2197 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2198 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2199 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2200 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2201 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2202 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2203 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2204
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2205 fdcb 01BBBRRR bit_iyd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2206 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2207 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2208 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2209 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2210 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2211 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2212 and scratch1 tmp tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2213 update_flags SZH1PN0
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2214
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2215 cb 10BBBRRR res_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2216 local tmp 8
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2217 tmp = 1 << B
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2218 tmp = ~tmp
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2219 main.R &= tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2220
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2221 cb 10BBB110 res_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2222 z80_fetch_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2223 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2224 local tmp 8
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2225 tmp = 1 << B
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2226 tmp = ~tmp
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2227 scratch1 &= tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2228 z80_store_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2229
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2230 z80_res_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2231 arg bit 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2232 arg tmp 8
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2233 tmp = 1 << bit
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2234 tmp = ~tmp
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2235 scratch1 = wz
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2236 ocall read_8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2237 cycles 1
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2238 tmp &= scratch1
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2239 scratch1 = tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2240 z80_store_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2241
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2242 ddcb 10BBB110 res_ixd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2243 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2244 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2245
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2246 ddcb 10BBBRRR res_ixd_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2247 z80_res_index B main.R
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2248
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2249 fdcb 10BBB110 res_iyd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2250 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2251 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2252
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2253 fdcb 10BBBRRR res_iyd_reg
1729
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2254 z80_res_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2255
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2256 cb 11BBBRRR set_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2257 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2258 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2259 or main.R tmp main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2260
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2261 cb 11BBB110 set_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2262 z80_fetch_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2263 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2264 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2265 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2266 or scratch1 tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2267 z80_store_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2268
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2269 z80_set_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2270 arg bit 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2271 arg tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2272 lsl 1 bit tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2273 mov wz scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2274 ocall read_8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2275 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2276 or scratch1 tmp tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2277 mov tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2278 z80_store_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2279
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2280 ddcb 11BBB110 set_ixd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2281 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2282 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2283
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2284 ddcb 11BBBRRR set_ixd_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2285 z80_set_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2286
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2287 fdcb 11BBB110 set_iyd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2288 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2289 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2290
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2291 fdcb 11BBBRRR set_iyd_reg
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2292 z80_set_index B main.R
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2293
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2294 z80_fetch_mod_hl
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2295 local tmp 16
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2296 arg change 16
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2297 lsl h 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2298 or l tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2299 mov tmp scratch1
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2300 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2301 mov tmp l
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2302 lsr tmp 8 h
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2303 ocall read_8
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
2304 cycles 2
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2305
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2306 z80_ldd_ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2307 arg change 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2308 local tmp 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2309 local tmp8 8
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2310 z80_fetch_mod_hl change
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2311
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2312 add a scratch1 tmp8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2313 update_flags H0XN0
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2314
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2315 and 0x2 tmp8 tmp8
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2316 lsl tmp8 4 tmp8
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2317 and 0x88 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2318 or tmp8 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2319
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2320 lsl d 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2321 or e tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2322 mov tmp scratch2
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2323 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2324 mov tmp e
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2325 lsr tmp 8 d
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2326 ocall write_8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2327
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2328 lsl b 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2329 or c tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2330 sub 1 tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2331
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2332 mov tmp c
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2333 lsr tmp 8 b
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2334 mov c pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2335 or b pvflag pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2336
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2337
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2338 ed 10100000 ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2339 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2340
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2341 ed 10101000 ldd
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2342 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2343
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2344 ed 10110000 ldir
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2345 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2346 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2347 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2348 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2349 cycles 5
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2350 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2351
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2352 ed 10111000 lddr
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2353 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2354 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2355 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2356 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2357 cycles 5
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2358 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2359
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2360 z80_cpd_cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2361 local tmp 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2362 local tmp8 8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2363 local hf 8
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2364 arg change 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2365
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2366 z80_fetch_mod_hl change
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2367 sub scratch1 a tmp8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2368 update_flags SZHN1
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2369
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2370 lsr chflags 3 hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2371 and 1 hf hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2372
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2373 sub hf tmp8 tmp8
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2374 update_flags X
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2375
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2376 and 0x2 tmp8 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2377 lsl tmp8 4 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2378 and 0x88 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2379 or tmp8 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2380
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2381 lsl b 8 tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2382 or c tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2383 sub 1 tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2384
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2385 mov tmp c
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2386 lsr tmp 8 b
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2387 mov c pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2388 or b pvflag pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2389
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2390 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2391
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2392 ed 10100001 cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2393 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2394
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2395 ed 10101001 cpd
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2396 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2397
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2398 ed 10110001 cpir
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2399 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2400 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2401 if zflag
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2402 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2403 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2404 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2405 cycles 5
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2406 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2407 end
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2408
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2409 ed 10111001 cpdr
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2410 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2411 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2412 if zflag
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2413 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2414 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2415 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2416 cycles 5
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2417 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2418 end
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2419
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2420 00100111 daa
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2421 local diff 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2422 local tmp 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2423 local low 8
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2424 low = a & 0xF
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2425 tmp = chflags & 8
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2426 if tmp
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2427 diff = 6
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2428 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2429 if low >=U 0xA
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2430 diff = 6
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2431 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2432 diff = 0
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2433 end
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2434 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2435
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2436 tmp = chflags & 0x80
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2437 if tmp
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2438 diff |= 0x60
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2439 update_flags C1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2440 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2441 if a >=U 0x9A
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2442 diff |= 0x60
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2443 update_flags C1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2444 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2445 update_flags C0
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2446 end
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2447 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2448
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2449 if nflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2450 a -= diff
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2451 update_flags SZYHPX
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2452 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2453 a += diff
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2454 update_flags SZYHPX
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2455 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2456
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2457 dd OOOOOOOO dd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2458 dispatch O
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2459
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2460 fd OOOOOOOO fd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2461 dispatch O
1741
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2462
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2463 ed 01101111 rld
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2464 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2465 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2466 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2467 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2468
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2469 lsr scratch1 4 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2470
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2471 lsl scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2472
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2473 and 0xF a tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2474 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2475
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2476 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2477 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2478 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2479 z80_store_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2480
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2481 ed 01100111 rrd
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2482 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2483 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2484 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2485 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2486
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2487 and 0xF scratch1 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2488 lsr scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2489
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2490 lsl a 4 tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2491 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2492
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2493 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2494 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2495 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2496 z80_store_hl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
2497