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Fix default target. Ensure m68k.h and z80.h are built before anything else when no dep info is available
author Michael Pavone <pavone@retrodev.com>
date Mon, 31 Mar 2025 21:06:18 -0700
parents dbff641a33df
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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1 info
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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2 prefix z80_
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3 opcode_size 8
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0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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4 extra_tables cb ed dded fded ddcb fdcb dd fd
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5 body z80_run_op
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6 sync_cycle z80_sync_cycle
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7 interrupt z80_interrupt
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8 include z80_util.c
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9 header z80.h
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10
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48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
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11 declare
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12 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider, uint32_t io_address_mask);
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
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13 z80_context * init_z80_context(z80_options *options);
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14 void z80_run(z80_context *context, uint32_t target_cycle);
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15 void z80_assert_reset(z80_context * context, uint32_t cycle);
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16 void z80_clear_reset(z80_context * context, uint32_t cycle);
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17 void z80_assert_busreq(z80_context * context, uint32_t cycle);
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18 void z80_clear_busreq(z80_context * context, uint32_t cycle);
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19 void z80_assert_nmi(z80_context *context, uint32_t cycle);
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20 uint8_t z80_get_busack(z80_context * context, uint32_t cycle);
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21 void z80_invalidate_code_range(z80_context *context, uint32_t start, uint32_t end);
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22 void z80_adjust_cycles(z80_context * context, uint32_t deduction);
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23 void z80_serialize(z80_context *context, serialize_buffer *buf);
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24 void z80_deserialize(deserialize_buffer *buf, void *vcontext);
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25 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler);
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26 void zremove_breakpoint(z80_context * context, uint16_t address);
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27 void z80_options_free(z80_options *opts);
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6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
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28 void z80_sync_cycle(z80_context *context, uint32_t target_cycle);
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dbff641a33df Implement Z80/PSG clock speed test register bit
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29 void z80_clock_divider_updated(z80_options *options);
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30
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31 regs
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32 main 8 b c d e h l f a
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33 alt 8 b' c' d' e' h' l' f' a'
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34 i 8
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35 r 8
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3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
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36 rhigh 8
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37 iff1 8
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38 iff2 8
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39 imode 8
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40 sp 16
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41 ix 16
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42 iy 16
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43 pc 16
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44 wz 16
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45 nflag 8
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46 last_flag_result 8
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47 pvflag 8
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48 chflags 8
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49 zflag 8
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50 scratch1 16
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51 scratch2 16
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52 busreq 8
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53 busack 8
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54 reset 8
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ca2336469397 Get new Z80 core running in CPM harness
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55 io_map ptrmemmap_chunk
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56 io_chunks 32
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57 io_mask 32
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58 int_cycle 32
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59 int_end_cycle 32
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60 int_value 8
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61 nmi_cycle 32
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62 system ptrvoid
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63 fastread ptr8 64
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64 fastwrite ptr8 64
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65 mem_pointers ptr8 4
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66
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67 flags
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68 register f
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69 S 7 sign last_flag_result.7
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70 Z 6 zero zflag
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71 Y 5 bit-5 last_flag_result.5
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72 H 4 half-carry chflags.3
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73 P 2 parity pvflag
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74 V 2 overflow pvflag
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75 X 3 bit-3 last_flag_result.3
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76 N 1 none nflag
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77 C 0 carry chflags.7
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78
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79
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80 z80_op_fetch
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81 cycles 1
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82 r += 1
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83 scratch1 = pc
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84 ocall read_8
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85 pc += 1
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86
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87 z80_run_op
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1dc718581aac Fix Z80 interrupts in Gen/MD mode when using new core. Disable CPU debug log in new Z80 core
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88 #printf "Z80: %X @ %d\n" pc cycles
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89 #printf "Z80: %X - A: %X, B: %X, C: %X D: %X, E: %X, H: %X, L: %X, SP: %X, IX: %X, IY: %X @ %d\n" pc a b c d e h l sp ix iy cycles
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90 z80_op_fetch
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91 dispatch scratch1
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92
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93 z80_interrupt
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94 if cycles >=U nmi_cycle
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95
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96 nmi_cycle = 0xFFFFFFFF
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97 iff1 = 0
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98 local pch 8
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99 pch = pc >> 8
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100 meta high pch
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101 meta low pc
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102 z80_push
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103 pc = 0x66
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104 update_sync
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105
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106 else
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107 if iff1
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108 if cycles >=U int_cycle
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109
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110 iff1 = 0
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111 iff2 = 0
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112 cycles 6
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113 update_sync
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114
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115 switch imode
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116 case 0
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117 dispatch int_value
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118
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119 case 1
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120 dispatch 0xFF
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121
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122 case 2
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123 pc = i << 8
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124 pc |= int_value
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125 #CD is call
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126 dispatch 0xCD
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127 end
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128
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129 end
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130 end
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131 end
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132
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133
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134 11001011 cb_prefix
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diff changeset
135 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136 dispatch scratch1 cb
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 11011101 dd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 dispatch scratch1 dd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141
1712
0a9a88b3d061 Fix ED prefix in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1706
diff changeset
142 11101101 ed_prefix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 dispatch scratch1 ed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 11111101 fd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 dispatch scratch1 fd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
150 dd 11001011 ddcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
151 z80_calc_index ix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
152 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
153 scratch1 = pc
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
154 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
155 pc += 1
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
156 dispatch scratch1 ddcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
157
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
158 fd 11001011 fdcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
159 z80_calc_index iy
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
160 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
161 scratch1 = pc
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
162 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
163 pc += 1
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
164 dispatch scratch1 fdcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
165
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 z80_check_cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 arg cond 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 local invert 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 switch cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 case 0
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
171 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
172 invert = !zflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 case 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
175 meta istrue zflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 case 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
178 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
179 invert = ~chflags
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
180 invert &= 0x80
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182 case 3
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
183 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
184 invert = chflags & 0x80
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 case 4
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
187 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
188 invert = !pvflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 case 5
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
191 meta istrue pvflag
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 case 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
194 meta istrue invert
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
195 invert = ~last_flag_result
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
196 invert &= 0x80
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 case 7
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
199 meta istrue invert
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
200 invert = 0x80 & last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 z80_fetch_hl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
204 scratch1 = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
205 scratch1 |= l
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 z80_store_hl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
209 scratch2 = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
210 scratch2 |= l
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
214 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
216 pc += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
219 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
221 wz = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
222 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
223 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
225 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
226 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
227 wz |= scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 z80_fetch_immed_reg16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
230 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
232 low = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
233 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
234 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
236 high = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
237 pc += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 z80_fetch_immed_to_reg16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
240 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
242 reg = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
243 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
244 scratch1 = pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
246 pc += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
247 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
248 reg |= scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 z80_fetch_hl
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
252 main.R = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 01DDDSSS ld_from_reg
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
255 main.D = main.S
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
257 dd 01DDD100 ld_from_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
258 invalid D 6
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
259 main.D = ix >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
260
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
261 dd 01100SSS ld_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
262 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
263 local tmp 16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
264 ix &= 0xFF
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
265 tmp = main.S << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
266 ix |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
267
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
268 dd 0110D10S ld_ixb_to_ixb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
269
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
270 dd 01DDD101 ld_from_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
271 invalid D 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
272 main.D = ix
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
273
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
274 dd 01101SSS ld_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
275 invalid S 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
276 ix &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
277 ix |= main.S
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
278
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
279 dd 01100101 ld_ixl_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
280 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
281 tmp = ix << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
282 ix &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
283 ix |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
284
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
285 dd 01101100 ld_ixh_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
286 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
287 tmp = ix >> 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
288 ix &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
289 ix |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
290
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
291 fd 01DDD100 ld_from_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
292 invalid D 6
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
293 main.D = iy >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
294
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
295 fd 01100SSS ld_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
296 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
297 local tmp 16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
298 iy &= 0xFF
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
299 tmp = main.S << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
300 iy |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
301
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
302 fd 0110D10S ld_iyb_to_iyb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
303
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
304 fd 01DDD101 ld_from_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
305 invalid D 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
306 main.D = iy
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
307
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
308 fd 01101SSS ld_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
309 invalid S 6
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
310 iy &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
311 iy |= main.S
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
312
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
313 fd 01100101 ld_iyl_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
314 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
315 tmp = iy << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
316 iy &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
317 iy |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
318
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
319 fd 01101100 ld_iyh_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
320 local tmp 16
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
321 tmp = iy >> 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
322 iy &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
323 iy |= tmp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
324
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
325 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
326 arg index 16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
327 wz = index
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
328 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
329 sext 16 scratch1 scratch1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
330 wz += scratch1
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
331
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
332 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
333 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
334 z80_calc_index index
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
335 scratch1 = wz
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
336 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
337 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
338
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
339 z80_store_index
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
340 scratch2 = wz
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
341 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
342
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 dd 01RRR110 ld_from_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
344 z80_fetch_index ix
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
345 main.R = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 fd 01RRR110 ld_from_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
348 z80_fetch_index iy
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
349 main.R = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
353 main.R = scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
354
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
355 dd 00100110 ld_immed_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
356 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
357 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
358 ix &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
359 ix |= scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
360
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
361 dd 00101110 ld_immed_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
362 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
363 ix &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
364 ix |= scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
365
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
366 fd 00100110 ld_immed_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
367 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
368 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
369 iy &= 0xFF
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
370 iy |= scratch1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
371
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
372 fd 00101110 ld_immed_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
373 z80_fetch_immed
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
374 iy &= 0xFF00
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
375 iy |= scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 01110RRR ld_to_hl
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
378 scratch1 = main.R
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 dd 01110RRR ld_to_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
382 z80_calc_index ix
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
383 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
384 scratch1 = main.R
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
385 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 fd 01110RRR ld_to_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
389 z80_calc_index iy
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
390 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
391 scratch1 = main.R
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
392 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 z80_store_hl
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
398
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
399 dd 00110110 ld_to_ixd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
400 z80_calc_index ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
401 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
402 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
403 scratch2 = wz
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
404 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
405
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
406 fd 00110110 ld_to_iyd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
407 z80_calc_index iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
408 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
409 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
410 scratch2 = wz
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
411 ocall write_8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 00001010 ld_a_from_bc
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
414 wz = b << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
415 wz |= c
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
416 scratch1 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
417 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
419 a = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 00011010 ld_a_from_de
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
422 wz = d << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
423 wz |= e
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
424 scratch1 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
425 wz += 1
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
426 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
427 a = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
431 scratch1 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
432 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
434 a = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 00000010 ld_a_to_bc
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
437 local tmp 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
438 scratch2 = b << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
439 scratch2 |= c
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
440 scratch1 = a
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
441 tmp = c + 1
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
442 wz = a << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
443 wz |= tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 00010010 ld_a_to_de
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
447 local tmp 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
448 scratch2 = d << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
449 scratch2 |= e
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
450 scratch1 = a
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
451 tmp = e + 1
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
452 wz = a << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
453 wz |= tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 00110010 ld_a_to_immed
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
457 local tmp 16
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
459 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
460 scratch1 = a
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
461 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
463 wz &= 0xFF
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
464 tmp = a << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
465 wz |= tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 ed 01000111 ld_i_a
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
468 i = a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 ed 01001111 ld_r_a
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
472 r = a
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
473 rhigh = 0x80 & a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
476 ed 01011111 ld_a_r
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
477 cycles 1
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
478 a = 0x7F & r
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
479 a |= rhigh
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
480 update_flags SZYH0XN0
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
481 pvflag = iff2
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
482
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
483 ed 01010111 ld_a_i
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
484 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
485 a = i
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
486 update_flags SZYH0XN0
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
487 pvflag = iff2
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
488
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
518 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
520 low = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
521 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
522 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
524 high = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
525 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 meta low e
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
539 meta high d
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
549 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
551 reg = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
552 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
553 scratch1 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
555 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
556 reg |= scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
557 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
573 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
574 scratch1 = l
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
576 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
577 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
578 scratch1 = h
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
580 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
582 dd 00100010 ld_ix_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
583 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
584 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
585 scratch1 = ix
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
586 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
587 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
588 scratch2 = wz
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
589 scratch1 = ix >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
590 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
591 wz += 1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
592
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
593 fd 00100010 ld_iy_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
594 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
595 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
596 scratch1 = iy
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
597 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
598 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
599 scratch2 = wz
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
600 scratch1 = iy >> 8
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
601 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
602 wz += 1
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
603
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 z80_fetch_immed16
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
606 scratch2 = wz
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
607 scratch1 = low
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
609 wz += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
610 scratch1 = high
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
611 scratch2 = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
613 wz += 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 local sph 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
633 sph = sp >> 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
639 sp = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
640 sp |= l
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
641
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
642 dd 11111001 ld_sp_ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
643 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
644 sp = ix
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
645
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
646 fd 11111001 ld_sp_iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
647 cycles 2
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
648 sp = iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
652 sp -= 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
653 scratch2 = sp
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
654 scratch1 = high
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
656 sp -= 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
657 scratch2 = sp
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
658 scratch1 = low
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 local ixh 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
683 ixh = ix >> 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 local iyh 8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
690 iyh = iy >> 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
698 sp += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
699 low = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
700 scratch1 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
701 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
702 sp += 1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
703 high = scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
704
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
705 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
706 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
707 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
708 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
709
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
710 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
711 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
712 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
713 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
714
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
715 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
716 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
717 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
718 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
719
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
720 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
721 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
722 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
723 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
724
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
725 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
726 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
727 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729 z80_pop
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
730 ixh <<= 8
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
731 ix |= ixh
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
735 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
736 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
737 z80_pop
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
738 iyh <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
739 iy |= iyh
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
740
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
741 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
742 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
743 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
744
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
745 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
746 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
747 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
748
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
749 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
750 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
751 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
752 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
755 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757 11100011 ex_sp_hl
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
758 scratch1 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
759 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
760 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
761 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
762 scratch2 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
763 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
764 scratch1 = sp + 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
765 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
766 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
767 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
768 scratch2 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
769 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
770 wz = h << 8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
771 wz |= l
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
772
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
773 dd 11100011 ex_sp_ix
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
774 scratch1 = sp
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
775 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
776 wz = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
777 scratch1 = ix
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
778 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
779 scratch2 = sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
780 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
781 scratch1 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
782 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
783 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
784 wz |= scratch1
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
785 scratch1 = ix >> 8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
786 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
787 scratch2 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
788 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
789 ix = wz
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
790
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
791 fd 11100011 ex_sp_iy
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
792 scratch1 = sp
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
793 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
794 wz = scratch1
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
795 scratch1 = iy
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
796 cycles 1
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
797 scratch2 = sp
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
798 ocall write_8
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
799 scratch1 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
800 ocall read_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
801 scratch1 <<= 8
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
802 wz |= scratch1
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
803 scratch1 = iy >> 8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
804 cycles 2
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
805 scratch2 = sp + 1
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
806 ocall write_8
2440
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Michael Pavone <pavone@retrodev.com>
parents: 1766
diff changeset
807 iy = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
808
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
809 10000RRR add_reg
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
810 a += main.R
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
811 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
812
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
813 dd 10000100 add_ixh
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
814 scratch1 = ix >> 8
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
815 a += scratch1
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
816 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
817
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
818 dd 10000101 add_ixl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
819 scratch1 = ix & 0xFF
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
820 a += scratch1
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
821 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
822
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
823 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
824 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
825 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
826 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
827
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
828 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
829 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
830 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
831 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
832
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
833 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
834 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
835 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
836 update_flags SZYHVXN0C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
837
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
838 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
839 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
840 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
841 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
842
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
843 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
844 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
845 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
846 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
847
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
848 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
849 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
850 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
851 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
852
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
853 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
854 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
855 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
856 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
857 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
858 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
859 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
860 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
861 lsr hlt 8 h
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
862 cycles 7
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
863
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
864 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
865 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
866 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
867 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
868 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
869 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
870 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
871
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
872 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
873 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
874 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
875 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
876 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
877 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
878 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
879
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
880 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
881 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
882 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
883 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
884
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
885 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
886 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
887 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
888 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
889
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
890 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
891 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
892 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
893 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
894 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
895 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
896
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
897 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
898 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
899 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
900 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
901 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
902 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
903
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
904 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
905 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
906 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
907 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
908
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
909 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
910 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
911 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
912 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
913
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
914 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
915 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
916 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
917 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
918 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
919 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
920
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
921 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
922 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
923 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
924 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
925 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
926 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
927
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
928 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
929 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
930 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
931 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
932
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
933 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
934 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
935 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
936 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
937
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
938 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
939 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
940 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
941
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
942 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
943 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
944 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
945 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
946
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
947 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
948 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
949 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
950 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
951
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
952 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
953 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
954 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
955 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
956
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
957 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
958 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
959 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
960 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
961
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
962 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
963 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
964 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
965 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
966
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
967 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
968 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
969 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
970 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
971
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
972 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
973 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
974 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
975 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
976
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
979 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980 update_flags SZYHVXN0C
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
981
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
982 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
983 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
984 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
985 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
986 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
987 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
988 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
989 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
990 lsr hlt 8 h
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
991 cycles 7
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
992
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
993 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
994 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
995 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
996 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
997 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
998 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
999 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1000
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1001 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1002 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1003 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1004 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1005 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1006 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1007 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1008
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1009 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1010 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1011 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1012 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1013
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1014
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1015 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1016 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1017 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1018 z80_adc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1019
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1020 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1021 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1022 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1023
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1024 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1025 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1026 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1027 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1028
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1029 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1030 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1031 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1032 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1033
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1034 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1035 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1036 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1037 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1038
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1039 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1040 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1041 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1042 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1043
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1044 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1045 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1046 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1047 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1048
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1049 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1050 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1051 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1052 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1053
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1054 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1055 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1056 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1057 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1058
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1061 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1063
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1064 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1065 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1066 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1067
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1068 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1069 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1070 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1071 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1072
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1073 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1074 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1075 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1076 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1077
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1078 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1079 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1080 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1081 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1082
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1083 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1084 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1085 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1086 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1087
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1088
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1089 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1090 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1091 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1093
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1094 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1095 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1096 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1097 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1098
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1099 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1100 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1101 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1102 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1103
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1104 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1105 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1106 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1107 update_flags SZYHVXN1C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1108
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1109 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1110 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1111 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1112 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1113 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1114 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1115 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1116 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1117 lsr hlt 8 h
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1118 cycles 7
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1119
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1120 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1121 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1122 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1123 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1124 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1125 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1126 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1127
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1128 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1129 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1130 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1131 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1132 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1133 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1134 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1135
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1136 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1137 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1138 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1139 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1140
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1141
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1142 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1143 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1144 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1145 z80_sbc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1146
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1147 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1148 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1150
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1151 dd 10100100 and_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1152 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1153 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1154 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1155
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1156 dd 10100101 and_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1157 and ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1158 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1159
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1160 fd 10100100 and_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1161 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1162 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1163 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1164
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1165 fd 10100101 and_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1166 and iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1167 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1168
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1169 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1170 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1171 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1172 update_flags SZYH1PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1173
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1174 dd 10100110 and_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1175 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1176 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1177 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1178
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1179 fd 10100110 and_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1180 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1181 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1182 update_flags SZYH1PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1183
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1184 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1185 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1186 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1187 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1188
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1189 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1190 or a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1191 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1192
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1193 dd 10110100 or_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1194 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1195 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1196 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1197
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1198 dd 10110101 or_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1199 or ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1200 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1201
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1202 fd 10110100 or_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1203 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1204 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1205 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1206
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1207 fd 10110101 or_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1208 or iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1209 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1210
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1211 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1212 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1213 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1214 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1215
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1216 dd 10110110 or_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1217 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1218 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1219 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1220
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1221 fd 10110110 or_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1222 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1223 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1224 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1225
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1226 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1227 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1228 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1229 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1230
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1231 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1232 xor a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1233 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1234
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1235 dd 10101100 xor_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1236 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1237 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1238 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1239
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1240 dd 10101101 xor_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1241 xor ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1242 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1243
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1244 fd 10101100 xor_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1245 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1246 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1247 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1248
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1249 fd 10101101 xor_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1250 xor iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1251 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1252
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1253 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1254 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1255 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1256 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1257
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1258 dd 10101110 xor_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1259 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1260 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1261 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1262
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1263 fd 10101110 xor_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1264 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1265 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1266 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1267
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1268 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1269 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1270 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1271 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1272
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1273 10111RRR cp_reg
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1274 mov main.R last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1275 cmp main.R a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1276 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1277
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1278 dd 10111100 cp_ixh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1279 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1280 lsr ix 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1281 mov tmp last_flag_result
1743
a1663a83dcab Fixed cp ixh in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1742
diff changeset
1282 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1283 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1284
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1285 dd 10111101 cp_ixl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1286 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1287 mov ix tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1288 mov ix last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1289 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1290 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1291
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1292 fd 10111100 cp_iyh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1293 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1294 lsr iy 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1295 mov tmp last_flag_result
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1296 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1297 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1298
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1299 fd 10111101 cp_iyl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1300 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1301 mov iy tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1302 mov iy last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1303 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1304 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1305
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1306 10111110 cp_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1307 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1308 z80_fetch_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1309 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1310 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1311 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1312 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1313
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1314 dd 10111110 cp_ixd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1315 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1316 z80_fetch_index ix
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1317 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1318 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1319 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1320 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1321
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1322 fd 10111110 cp_iyd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1323 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1324 z80_fetch_index iy
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1325 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1326 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1327 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1328 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1329
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1330 11111110 cp_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1331 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1332 z80_fetch_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1333 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1334 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1335 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1336 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1337
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1338 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1339 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1340 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1341
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1342 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1343 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1344 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1345
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1346 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1347 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1348 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1349 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1350 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1351 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1352 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1353
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1354 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1355 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1356 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1357
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1358 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1359 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1360 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1361 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1362 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1363 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1364 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1365
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1366 00110100 inc_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1367 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1368 z80_fetch_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1369 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1370 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1371 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1372 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1373 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1374 mov tmp scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1375 cycles 1
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1376 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1377
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1378 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1379 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1380 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1381 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1382 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1383 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1384 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1385 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1386 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1387 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1388 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1389
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1390 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1391 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1392 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1393 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1394 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1395 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1396 add 1 tmp tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1397 update_flags SZYHVXN0
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1398 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1399 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1400 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1401
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1402 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1403 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1404 arg low 8
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
1405 cycles 2
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1406 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1407 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1408 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1409 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1410 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1411 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1412
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1413 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1414 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1415
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1416 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1417 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1418
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1419 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1420 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1421
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1422 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1423 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1424
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1425 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1426 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1427
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1428 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1429 add 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1430
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1431 00RRR101 dec_reg
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1432 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1433 update_flags SZYHVXN1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1434
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1435 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1436 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1437 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1438
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1439 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1440 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1441 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1442 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1443 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1444 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1445 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1446
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1447 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1448 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1449 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1450
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1451 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1452 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1453 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1454 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1455 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1456 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1457 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1458
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1459 00110101 dec_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1460 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1461 z80_fetch_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1462 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1463 #or add some syntax to force a certain size on an operation so they are unnecessary
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1464 mov scratch1 tmp
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1465 sub 1 tmp tmp
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1466 update_flags SZYHVXN1
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1467 mov tmp scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1468 cycles 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1469 z80_store_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1470
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1471 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1472 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1473 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1474 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1475 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1476 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1477 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1478 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1479 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1480 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1481 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1482
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1483 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1484 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1485 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1486 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1487 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1488 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1489 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1490 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1491 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1492 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1493 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1494
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1495 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1496 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1497 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1498 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1499 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1500 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1501 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1502 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1503 lsr word 8 high
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
1504 cycles 2
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1505
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1506 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1507 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1508
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1509 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1510 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1511
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1512 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1513 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1514
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1515 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1516 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1517
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1518 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1519 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1520
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1521 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1522 sub 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1523
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1524 00101111 cpl
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
1525 a = ~a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1526 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1527
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1528 ed 01DDD100 neg
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
1529 a = -a
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1530 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1531
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1532 00111111 ccf
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1533 local tmp 8
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1534 and 0x80 last_flag_result last_flag_result
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1535 and 0x7F a tmp
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1536 or tmp last_flag_result last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1537 and 0x80 chflags chflags
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1538 lsr chflags 4 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1539 or tmp chflags chflags
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1540 xor 0x80 chflags chflags
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1541 update_flags N0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1542
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1543 00110111 scf
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1544 local tmp 8
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1545 and 0x80 last_flag_result last_flag_result
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1546 and 0x7F a tmp
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1547 or tmp last_flag_result last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1548 update_flags H0N0C1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1549
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1550 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1551
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1552 01110110 halt
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1553 cmp nmi_cycle cycles
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1554 if cycles >=U nmi_cycle
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1555
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1556 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1557 if cycles >=U int_cycle
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1558
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1559 if iff1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1560 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1561 pc -= 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1562 end
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1563
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1564 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1565 pc -= 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1566 end
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1567 end
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1568
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1569 11110011 di
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1570 iff1 = 0
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1571 iff2 = 0
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1572 update_sync
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1573
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1574 11111011 ei
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1575 iff1 = 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1576 iff2 = 1
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1577 update_sync
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1578
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1579 if cycles >=U int_cycle
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1580 int_cycle = cycles + 1
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1581 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1582
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1583 ed 01D00110 im0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1584 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1585
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1586 ed 01D10110 im1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1587 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1588
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1589 ed 01D11110 im2
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1590 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1591
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1592 ed 01D01110 im3
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1593 #some sources call this mode 0/1, but unclear
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1594 #if the behavior is really different from im 0
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1595 mov 0 imode
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1596
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1597 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1598 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1599 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1600
1726
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1601 11101001 jp_hl
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1602 lsl h 8 pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1603 or l pc pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1604
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1605 dd 11101001 jp_ix
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1606 mov ix pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1607
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1608 fd 11101001 jp_iy
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1609 mov iy pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1610
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1611 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1612 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1613 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1614 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1615 pc = wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1616 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1617
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1618 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1619 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1620 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1621 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1622 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1623 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1624
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1625 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1626 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1627 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1628
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1629 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1630 sext 16 scratch1 scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1631 pc += scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1632 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1633 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1634
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1635 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1636 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1637 z80_fetch_immed
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1638 b -= 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1639
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1640 if b
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1641 sext 16 scratch1 scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1642 pc += scratch1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1643 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1644 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1645
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1646
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1647 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1648 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1649 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1650 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1651 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1652 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1653 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1654 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1655
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1656 11CCC100 call_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1657 local pch 8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1658 z80_fetch_immed16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1659 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1660
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1661 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1662 pch = pc >> 8
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1663 meta high pch
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1664 meta low pc
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1665 z80_push
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1666 pc = wz
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1667 end
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1668
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1669 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1670 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1671 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1672 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1673 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1674 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1675 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1676 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1677
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1678 11001001 ret
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1679 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1680 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1681 meta low pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1682 z80_pop
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1683 lsl pch 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1684 or pch pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1685
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1686 ed 01001101 reti
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1687 local pch 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1688 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1689 meta high pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1690 meta low pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1691 z80_pop
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1692 lsl pch 8 pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1693 or pch pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1694
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1695 ed 01NN1101 retn
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1696 mov iff2 iff1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1697 local pch 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1698 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1699 meta high pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1700 meta low pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1701 z80_pop
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1702 lsl pch 8 pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1703 or pch pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1704
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1705 11CCC000 ret_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1706 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1707 cycles 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1708 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1709 if istrue
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1710 meta high pch
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1711 meta low pc
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1712 z80_pop
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1713 pch = pch << 8
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1714 pc |= pch
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1715 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1716
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1717 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1718 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1719 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1720 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1721
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1722 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1723 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1724 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1725 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1726 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1727
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1728 z80_ini_ind
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1729 arg change 16
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1730 local tmp 8
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1731 cycles 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1732
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1733 lsl 8 b wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1734 or c wz wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1735 add change wz wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1736
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1737 sub 1 b b
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1738 update_flags SZYX
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1739
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1740 lsl b 8 scratch1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1741 or c scratch1 scratch1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1742 ocall io_read8
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1743
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1744 and 0x80 scratch1 nflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1745
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1746 mov wz tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1747 add tmp scratch1 tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1748 update_flags C
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1749
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1750 z80_store_hl
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1751
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1752 lsl h 8 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1753 or l scratch2 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1754 add change scratch2 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1755 mov scratch2 l
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1756 lsr scratch2 8 h
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1757
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1758 and 7 tmp tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1759 xor b tmp tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1760 update_flags P
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1761 lsr chflags 4 tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1762 or tmp chflags chflags
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1763
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1764 ed 10100010 ini
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1765 z80_ini_ind 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1766
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1767 ed 10110010 inir
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1768 z80_ini_ind 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1769 if zflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1770 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1771 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1772 cycles 5
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1773 end
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1774
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1775 ed 10101010 ind
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1776 z80_ini_ind -1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1777
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1778 ed 10111010 indr
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1779 z80_ini_ind -1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1780 if zflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1781 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1782 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1783 cycles 5
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1784 end
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1785
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1786 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1787 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1788 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1789 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1790 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1791
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1792 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1793 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1794 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1795 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1796 ocall io_write8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1797
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1798 z80_outi_outd
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1799 arg change 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1800 local tmp 8
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1801 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1802 z80_fetch_hl
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1803
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1804 and 0x80 scratch1 nflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1805
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1806 lsl h 8 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1807 or l scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1808 add change scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1809 mov scratch2 l
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1810 lsr scratch2 8 h
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1811
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1812 add l scratch1 tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1813 update_flags C
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1814 and 7 tmp tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1815
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1816 lsl b 8 scratch2
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1817 or c scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1818 ocall io_write8
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1819
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1820 sub 1 b b
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1821 update_flags SZYX
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1822
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1823 lsl 8 b wz
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1824 or c wz wz
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1825 add change wz wz
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1826
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1827 xor b tmp tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1828 update_flags P
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1829 lsr chflags 4 tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1830 or tmp chflags chflags
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1831
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1832 ed 10100011 outi
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1833 z80_outi_outd 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1834
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1835 ed 10110011 otir
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1836 z80_outi_outd 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1837 if zflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1838 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1839 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1840 cycles 5
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1841 end
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1842
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1843 ed 10101011 outd
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1844 z80_outi_outd -1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1845
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1846 ed 10111011 otdr
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1847 z80_outi_outd -1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1848 if zflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1849 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1850 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
1851 cycles 5
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1852 end
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1853
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1854 00000111 rlca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1855 rol a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1856 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1857
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1858 00010111 rla
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1859 rlc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1860 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1861
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1862 00001111 rrca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1863 ror a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1864 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1865
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1866 00011111 rra
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1867 rrc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1868 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1869
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1870 cb 00000RRR rlc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1871 rol main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1872 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1873
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1874 cb 00000110 rlc_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1875 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1876 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1877 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1878 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1879 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1880 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1881 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1882
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1883 z80_rlc_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1884 arg tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1885 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1886 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1887 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1888 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1889 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1890 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1891 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1892 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1893
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1894 ddcb 00000110 rlc_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1895 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1896 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1897
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1898 ddcb 00000RRR rlc_ixd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1899 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1900
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1901 fdcb 00000110 rlc_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1902 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1903 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1904
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1905 fdcb 00000RRR rlc_iyd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1906 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1907
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1908 cb 00010RRR rl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1909 rlc main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1910 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1911
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1912 cb 00010110 rl_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1913 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1914 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1915 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1916 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1917 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1918 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1919 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1920
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1921 z80_rl_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1922 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1923 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1924 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1925 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1926 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1927 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1928 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1929 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1930 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1931
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1932 ddcb 00010110 rl_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1933 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1934 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1935
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1936 fdcb 00010110 rl_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1937 local tmp 8
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1938 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1939
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1940
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1941 ddcb 00010RRR rl_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1942 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1943
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1944 fdcb 00010RRR rl_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1945 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1946
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1947 cb 00001RRR rrc
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1948 ror main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1949 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1950
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1951 cb 00001110 rrc_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1952 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1953 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1954 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1955 ror tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1956 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1957 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1958 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1959
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1960 z80_rrc_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1961 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1962 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1963 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1964 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1965 mov scratch1 tmp
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1966 ror tmp 1 tmp
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1967 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1968 mov tmp scratch1
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1969 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1970
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1971 ddcb 00001110 rrc_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1972 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1973 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1974
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1975 ddcb 00001RRR rrc_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1976 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1977
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1978 fdcb 00001110 rrc_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1979 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1980 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1981
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1982 fdcb 00001RRR rrc_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1983 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1984
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1985 cb 00011RRR rr
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1986 rrc main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1987 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1988
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1989 cb 00011110 rr_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1990 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1991 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1992 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1993 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1994 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1995 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1996 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1997
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1998 z80_rr_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1999 arg tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2000 mov wz scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2001 ocall read_8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2002 cycles 1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2003 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2004 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2005 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2006 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2007 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2008
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2009 ddcb 00011110 rr_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2010 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2011 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2012
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2013 ddcb 00011RRR rr_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2014 z80_rr_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2015
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2016 fdcb 00011110 rr_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2017 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2018 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2019
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2020 fdcb 00011RRR rr_iyd_reg
1723
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2021 z80_rr_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2022
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2023 cb 00100RRR sla
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2024 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2025 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2026
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2027 cb 00100110 sla_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2028 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2029 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2030 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2031 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2032 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2033 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2034 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2035
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2036 z80_sla_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2037 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2038 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2039 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2040 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2041 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2042 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2043 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2044 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2045 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2046
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2047 ddcb 00100110 sla_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2048 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2049 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2050
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2051 ddcb 00100RRR sla_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2052 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2053
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2054 fdcb 00100110 sla_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2055 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2056 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2057
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2058 fdcb 00100RRR sla_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2059 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2060
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2061 cb 00101RRR sra
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2062 asr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2063 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2064
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2065 cb 00101110 sra_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2066 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2067 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2068 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2069 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2070 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2071 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2072 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2073
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2074 z80_sra_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2075 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2076 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2077 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2078 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2079 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2080 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2081 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2082 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2083 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2084
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2085 ddcb 00101110 sra_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2086 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2087 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2088
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2089 ddcb 00101RRR sra_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2090 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2091
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2092 fdcb 00101110 sra_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2093 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2094 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2095
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2096 fdcb 00101RRR sra_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2097 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2098
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2099 cb 00110RRR sll
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2100 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2101 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2102 or 1 main.R main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2103 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2104
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2105 cb 00110110 sll_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2106 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2107 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2108 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2109 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2110 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2111 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2112 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2113 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2114 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2115
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2116 z80_sll_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2117 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2118 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2119 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2120 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2121 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2122 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2123 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2124 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2125 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2126 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2127 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2128
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2129 ddcb 00110110 sll_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2130 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2131 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2132
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2133 ddcb 00110RRR sll_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2134 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2135
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2136 fdcb 00110110 sll_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2137 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2138 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2139
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2140 fdcb 00110RRR sll_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2141 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2142
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2143 cb 00111RRR srl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2144 lsr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2145 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2146
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2147 cb 00111110 srl_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2148 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2149 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2150 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2151 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2152 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2153 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2154 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2155
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2156 z80_srl_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2157 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2158 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2159 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2160 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2161 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2162 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2163 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2164 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2165 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2166
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2167 ddcb 00111110 srl_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2168 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2169 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2170
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2171 ddcb 00111RRR srl_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2172 z80_srl_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2173
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2174 fdcb 00111110 srl_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2175 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2176 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2177
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2178 fdcb 00111RRR srl_iyd_reg
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2179 z80_srl_index main.R
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2180
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2181 cb 01BBBRRR bit_reg
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2182 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2183 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2184 mov main.R last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2185 and main.R tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2186 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2187
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2188 cb 01BBB110 bit_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2189 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2190 z80_fetch_hl
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
2191 cycles 1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2192 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2193 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2194 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2195 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2196
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2197
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2198 ddcb 01BBBRRR bit_ixd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2199 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2200 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2201 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2202 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2203 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2204 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2205 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2206 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2207
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2208 fdcb 01BBBRRR bit_iyd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2209 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2210 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2211 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2212 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2213 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2214 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2215 and scratch1 tmp tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2216 update_flags SZH1PN0
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2217
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2218 cb 10BBBRRR res_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2219 local tmp 8
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2220 tmp = 1 << B
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2221 tmp = ~tmp
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2222 main.R &= tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2223
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2224 cb 10BBB110 res_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2225 z80_fetch_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2226 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2227 local tmp 8
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2228 tmp = 1 << B
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2229 tmp = ~tmp
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2230 scratch1 &= tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2231 z80_store_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2232
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2233 z80_res_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2234 arg bit 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2235 arg tmp 8
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2236 tmp = 1 << bit
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2237 tmp = ~tmp
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2238 scratch1 = wz
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2239 ocall read_8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2240 cycles 1
2443
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2241 tmp &= scratch1
461fffc226e0 Sugar for unary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2442
diff changeset
2242 scratch1 = tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2243 z80_store_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2244
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2245 ddcb 10BBB110 res_ixd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2246 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2247 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2248
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2249 ddcb 10BBBRRR res_ixd_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2250 z80_res_index B main.R
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2251
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2252 fdcb 10BBB110 res_iyd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2253 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2254 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2255
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2256 fdcb 10BBBRRR res_iyd_reg
1729
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2257 z80_res_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2258
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2259 cb 11BBBRRR set_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2260 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2261 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2262 or main.R tmp main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2263
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2264 cb 11BBB110 set_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2265 z80_fetch_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2266 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2267 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2268 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2269 or scratch1 tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2270 z80_store_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2271
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2272 z80_set_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2273 arg bit 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2274 arg tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2275 lsl 1 bit tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2276 mov wz scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2277 ocall read_8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2278 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2279 or scratch1 tmp tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2280 mov tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2281 z80_store_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2282
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2283 ddcb 11BBB110 set_ixd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2284 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2285 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2286
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2287 ddcb 11BBBRRR set_ixd_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2288 z80_set_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2289
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2290 fdcb 11BBB110 set_iyd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2291 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2292 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2293
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2294 fdcb 11BBBRRR set_iyd_reg
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2295 z80_set_index B main.R
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2296
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2297 z80_fetch_mod_hl
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2298 local tmp 16
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2299 arg change 16
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2300 lsl h 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2301 or l tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2302 mov tmp scratch1
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2303 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2304 mov tmp l
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2305 lsr tmp 8 h
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2306 ocall read_8
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
2307 cycles 2
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2308
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2309 z80_ldd_ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2310 arg change 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2311 local tmp 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2312 local tmp8 8
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2313 z80_fetch_mod_hl change
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2314
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2315 add a scratch1 tmp8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2316 update_flags H0XN0
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2317
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2318 and 0x2 tmp8 tmp8
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2319 lsl tmp8 4 tmp8
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2320 and 0x88 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2321 or tmp8 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2322
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2323 lsl d 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2324 or e tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2325 mov tmp scratch2
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2326 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2327 mov tmp e
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2328 lsr tmp 8 d
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2329 ocall write_8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2330
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2331 lsl b 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2332 or c tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2333 sub 1 tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2334
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2335 mov tmp c
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2336 lsr tmp 8 b
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2337 mov c pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2338 or b pvflag pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2339
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2340
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2341 ed 10100000 ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2342 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2343
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2344 ed 10101000 ldd
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2345 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2346
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2347 ed 10110000 ldir
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2348 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2349 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2350 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2351 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2352 cycles 5
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2353 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2354
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2355 ed 10111000 lddr
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2356 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2357 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2358 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2359 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2360 cycles 5
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2361 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2362
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2363 z80_cpd_cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2364 local tmp 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2365 local tmp8 8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2366 local hf 8
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2367 arg change 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2368
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2369 z80_fetch_mod_hl change
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2370 sub scratch1 a tmp8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2371 update_flags SZHN1
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2372
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2373 lsr chflags 3 hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2374 and 1 hf hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2375
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2376 sub hf tmp8 tmp8
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2377 update_flags X
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2378
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2379 and 0x2 tmp8 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2380 lsl tmp8 4 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2381 and 0x88 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2382 or tmp8 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2383
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2384 lsl b 8 tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2385 or c tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2386 sub 1 tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2387
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2388 mov tmp c
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2389 lsr tmp 8 b
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2390 mov c pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2391 or b pvflag pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2392
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2393 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2394
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2395 ed 10100001 cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2396 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2397
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2398 ed 10101001 cpd
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2399 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2400
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2401 ed 10110001 cpir
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2402 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2403 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2404 if zflag
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2405 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2406 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2407 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2408 cycles 5
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2409 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2410 end
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2411
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2412 ed 10111001 cpdr
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2413 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2414 if pvflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2415 if zflag
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2416 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2417 wz = pc + 1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2418 pc -= 2
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2419 cycles 5
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2420 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2421 end
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2422
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2423 00100111 daa
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2424 local diff 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2425 local tmp 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2426 local low 8
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2427 low = a & 0xF
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2428 tmp = chflags & 8
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2429 if tmp
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2430 diff = 6
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2431 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2432 if low >=U 0xA
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2433 diff = 6
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2434 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2435 diff = 0
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2436 end
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2437 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2438
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2439 tmp = chflags & 0x80
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2440 if tmp
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2441 diff |= 0x60
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2442 update_flags C1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2443 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2444 if a >=U 0x9A
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2445 diff |= 0x60
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2446 update_flags C1
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2447 else
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2448 update_flags C0
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2449 end
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2450 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2451
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2452 if nflag
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2453 a -= diff
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2454 update_flags SZYHPX
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2455 else
2442
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2456 a += diff
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2441
diff changeset
2457 update_flags SZYHPX
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2458 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2459
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2460 dd OOOOOOOO dd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2461 dispatch O
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2462
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2463 fd OOOOOOOO fd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2464 dispatch O
1741
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2465
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2466 ed 01101111 rld
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2467 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2468 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2469 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2470 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2471
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2472 lsr scratch1 4 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2473
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2474 lsl scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2475
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2476 and 0xF a tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2477 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2478
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2479 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2480 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2481 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2482 z80_store_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2483
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2484 ed 01100111 rrd
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2485 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2486 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2487 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2488 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2489
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2490 and 0xF scratch1 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2491 lsr scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2492
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2493 lsl a 4 tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2494 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2495
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2496 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2497 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2498 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2499 z80_store_hl
2441
4435abe5db5e Sugar for binary operators in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents: 2440
diff changeset
2500
2652
224c7c1730fd Implement 2-byte ED-prefix NOP in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 2600
diff changeset
2501 ed XXXXXXXX ed_nop