repos/blastem: m68k_to_x86.c annotate

annotate m68k_to_x86.c @ 491:193ca779988e opengl

Close OpenGL feature branch

author	Mike Pavone <pavone@retrodev.com>
date	Sun, 27 Oct 2013 22:07:43 -0700
parents	b449af228c63
children	7f54f1773e84

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 457 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 457 diff changeset	2 Copyright 2013 Michael Pavone
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 457 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 457 diff changeset	5 */
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "m68k_to_x86.h"
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	8 #include "68kinst.h"
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	9 #include "mem.h"
211 464513050c85 Small bit of cleanup Mike Pavone <pavone@retrodev.com> parents: 210 diff changeset	10 #include "x86_backend.h"
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	11 #include <stdio.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	12 #include <stddef.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	13 #include <stdlib.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	14 #include <string.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define BUS 4
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	17 #define PREDEC_PENALTY 2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define CYCLES RAX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define LIMIT RBP
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	20 #define SCRATCH1 RCX
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	21 #define SCRATCH2 RDI
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 #define CONTEXT RSI
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 #define FLAG_N RBX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 #define FLAG_V BH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 #define FLAG_Z RDX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 #define FLAG_C DH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	29 char disasm_buf[1024];
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	30
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	31 m68k_context * sync_components(m68k_context * context, uint32_t address);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	32
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	33 void handle_cycle_limit();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	34 void m68k_save_context();
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	35 void m68k_load_context();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	36 void m68k_modified_ret_addr();
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	37 void m68k_native_addr();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	38 void m68k_native_addr_and_sync();
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	39 void m68k_invalid();
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	40 void m68k_retrans_stub();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	41 void set_sr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	42 void set_ccr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	43 void get_sr();
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	44 void do_sync();
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	45 void bcd_add();
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	46 void bcd_sub();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	47 void m68k_start_context(uint8_t * addr, m68k_context * context);
321 146c87616b05 Don't update interrupt mask on non-interrupt exceptions Mike Pavone <pavone@retrodev.com> parents: 319 diff changeset	48 void debug_print_sr();
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	49
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 uint8_t * cycles(uint8_t * dst, uint32_t num)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	52 dst = add_ir(dst, num, CYCLES, SZ_D);
118 d9ff99ef5533 cycles should return dst Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	53 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	55
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	56 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address, x86_68k_options * opts)
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	57 {
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	58 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	59 uint8_t * jmp_off = dst+1;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	60 dst = jcc(dst, CC_NC, dst + 7);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	61 dst = mov_ir(dst, address, SCRATCH1, SZ_D);
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	62 dst = call(dst, opts->handle_cycle_limit_int);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	63 *jmp_off = dst - (jmp_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	64 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	65 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	66
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	67 uint8_t * check_cycles(uint8_t * dst)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	68 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	69 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	70 uint8_t * jmp_off = dst+1;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	71 dst = jcc(dst, CC_NC, dst + 7);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	72 dst = call(dst, (uint8_t *)handle_cycle_limit);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	73 *jmp_off = dst - (jmp_off+1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	74 return dst;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	75 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	76
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 if (op->addr_mode == MODE_REG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 return opts->dregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 if (op->addr_mode == MODE_AREG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 return opts->aregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 return -1;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	87
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	88 //must be called with an m68k_op_info that uses a register
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	89 size_t reg_offset(m68k_op_info *op)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	90 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	91 if (op->addr_mode == MODE_REG) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	92 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	93 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	94 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	95 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	96
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	97 void print_regs_exit(m68k_context * context)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	99 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	100 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	101 printf("d%d: %X\n", i, context->dregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	102 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	103 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	104 printf("a%d: %X\n", i, context->aregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	105 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	106 exit(0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	107 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	108
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	109 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	110 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	111 int8_t reg = native_reg(&(inst->src), opts);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	112 uint8_t sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	113 int32_t dec_amount,inc_amount;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 if (reg >= 0) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	115 ea->mode = MODE_REG_DIRECT;
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	116 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	117 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	118 ea->base = SCRATCH1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	119 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	120 ea->base = reg;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	121 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	122 return out;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	124 switch (inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	125 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	126 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	127 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	128 //We only get one memory parameter, so if the dst operand is a register in memory,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	129 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	130 reg = native_reg(&(inst->dst), opts);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	131 if (reg >= 0 \|\| inst->dst.addr_mode == MODE_UNUSED \|\| !(inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	132 \|\| inst->op == M68K_EXG) {
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	133
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	134 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	135 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	136 ea->disp = reg_offset(&(inst->src));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	137 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	138 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	139 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	140 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	141 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	142 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	143 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	144 ea->base = SCRATCH1;
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	145 //we're explicitly handling the areg dest here, so we exit immediately
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	146 return out;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	147 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	148 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	149 case MODE_AREG_PREDEC:
216 0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	150 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 :1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	151 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	152 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
158 a2ab895d9708 Fix predec address mode when used as source Mike Pavone <pavone@retrodev.com> parents: 157 diff changeset	153 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	154 } else {
158 a2ab895d9708 Fix predec address mode when used as source Mike Pavone <pavone@retrodev.com> parents: 157 diff changeset	155 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	156 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	157 case MODE_AREG_INDIRECT:
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	158 case MODE_AREG_POSTINC:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	159 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	160 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	161 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	162 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	163 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	164 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	165 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	166 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	167 out = call(out, opts->read_8);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	168 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	169 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	170 out = call(out, opts->read_16);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	171 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	172 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	173 out = call(out, opts->read_32);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	174 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	175 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	176
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	177 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 182 diff changeset	178 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	179 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	180 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	181 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	182 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	183 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	184 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	185 ea->mode = MODE_REG_DIRECT;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	186 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	187 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	188 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	189 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	190 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	191 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	192 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	193 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	194 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	195 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	196 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	197 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	198 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	199 out = call(out, opts->read_8);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	200 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	201 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	202 out = call(out, opts->read_16);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	203 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	204 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	205 out = call(out, opts->read_32);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	206 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	207 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	208 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	209 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	210 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	211 case MODE_AREG_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	212 out = cycles(out, 6);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	213 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	214 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	215 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	216 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	217 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	218 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	219 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	220 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	221 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	222 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	223 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	224 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	225 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	226 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	227 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	228 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	229 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	230 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	231 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	232 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	233 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	234 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	235 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	236 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	237 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	238 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	239 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	240 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	241 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	242 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	243 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	244 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	245 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	246 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	247 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	248 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	249 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	250 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	251 }
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	252 switch (inst->extra.size)
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	253 {
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	254 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	255 out = call(out, opts->read_8);
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	256 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	257 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	258 out = call(out, opts->read_16);
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	259 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	260 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	261 out = call(out, opts->read_32);
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	262 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	263 }
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	264 ea->mode = MODE_REG_DIRECT;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	265 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	266 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	267 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	268 out = cycles(out, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	269 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	270 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	271 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	272 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	273 out = call(out, opts->read_8);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	274 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	275 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	276 out = call(out, opts->read_16);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	277 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	278 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	279 out = call(out, opts->read_32);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	280 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	281 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	282 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	283 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	284 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	285 case MODE_PC_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	286 out = cycles(out, 6);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	287 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	288 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	289 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	290 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	291 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	292 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	293 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	294 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	295 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	296 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	297 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	298 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	299 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	300 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	301 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	302 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	303 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	304 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	305 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	306 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	307 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	308 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	309 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	310 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	311 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	312 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	313 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	314 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	315 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	316 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	317 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	318 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	319 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	320 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	321 }
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	322 switch (inst->extra.size)
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	323 {
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	324 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	325 out = call(out, opts->read_8);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	326 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	327 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	328 out = call(out, opts->read_16);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	329 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	330 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	331 out = call(out, opts->read_32);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	332 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	333 }
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	334 ea->mode = MODE_REG_DIRECT;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	335 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	336 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	337 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	338 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	339 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	340 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	341 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	342 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	343 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	344 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	345 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	346 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	347 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	348 out = call(out, opts->read_8);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	349 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	350 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	351 out = call(out, opts->read_16);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	352 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	353 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	354 out = call(out, opts->read_32);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	355 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	356 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	357 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	358 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	359 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	360 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	361 case MODE_IMMEDIATE_WORD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	362 if (inst->variant != VAR_QUICK) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	363 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	364 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	365 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	366 ea->disp = inst->src.params.immed;
216 0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	367 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) {
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	368 ea->disp \|= 0xFFFF0000;
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	369 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	370 return out;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	371 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	372 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	373 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	374 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	375 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	376 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	377 if (ea->mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	378 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	379 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	380 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	381 ea->mode = MODE_REG_DIRECT;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	382 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	383 ea->base = SCRATCH1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	384 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	385 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	386 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	387
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	388 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	389 {
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	390 int8_t reg = native_reg(&(inst->dst), opts), sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	391 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	392 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	393 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	394 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	395 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	396 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	397 switch (inst->dst.addr_mode)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	399 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	400 case MODE_AREG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	401 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	402 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	403 ea->disp = reg_offset(&(inst->dst));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	404 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	405 case MODE_AREG_PREDEC:
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	406 if (inst->src.addr_mode == MODE_AREG_PREDEC) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	407 out = push_r(out, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	408 }
182 924af8b2f7a0 Fix -(a7) dest when size is byte Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	409 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	410 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	411 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	412 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	413 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	414 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	415 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	416 case MODE_AREG_POSTINC:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	417 if (fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	418 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	419 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	420 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	421 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	422 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	423 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	424 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	425 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	426 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	427 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	428 out = call(out, opts->read_8);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	429 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	430 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	431 out = call(out, opts->read_16);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	432 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	433 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	434 out = call(out, opts->read_32);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	435 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	436 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	437 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	438 if (inst->src.addr_mode == MODE_AREG_PREDEC) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	439 //restore src operand to SCRATCH2
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	440 out =pop_r(out, SCRATCH2);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	441 } else {
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	442 //save reg value in SCRATCH2 so we can use it to save the result in memory later
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	443 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	444 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	445 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	446 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	447 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	448 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	449
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	450 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
218 1abf8e967b33 Fix autoincrement on a7 when used as a destination in a byte sized instruction Mike Pavone <pavone@retrodev.com> parents: 216 diff changeset	451 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	452 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	453 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	454 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	455 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	456 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	457 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	458 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	459 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	460 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	461 case MODE_AREG_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	462 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	463 reg = fake_read ? SCRATCH2 : SCRATCH1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	464 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	465 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	466 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	467 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	468 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	469 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	470 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	471 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	472 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	473 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	474 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	475 out = call(out, opts->read_8);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	476 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	477 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	478 out = call(out, opts->read_16);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	479 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	480 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	481 out = call(out, opts->read_32);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	482 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	483 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	484 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	485 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	486 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	487 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	488 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	489 case MODE_AREG_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	490 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	491 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	492 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	493 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	494 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	495 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	496 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	497 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	498 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	499 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	500 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	501 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	502 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	503 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	504 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	505 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	506 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	507 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	508 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	509 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	510 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	511 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	512 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	513 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	514 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	515 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	516 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	517 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	518 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	519 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	520 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	521 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	522 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	523 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	524 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	525 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	526 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	527 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	528 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	529 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	530 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	531 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	532 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	533 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	534 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	535 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	536 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	537 out = call(out, opts->read_8);
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	538 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	539 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	540 out = call(out, opts->read_16);
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	541 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	542 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	543 out = call(out, opts->read_32);
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	544 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	545 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	546 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	547 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	548 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	549 ea->base = SCRATCH1;
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	550 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	551 case MODE_PC_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	552 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	553 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	554 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	555 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	556 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	557 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	558 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	559 out = call(out, opts->read_8);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	560 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	561 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	562 out = call(out, opts->read_16);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	563 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	564 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	565 out = call(out, opts->read_32);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	566 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	567 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	568 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	569 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	570 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	571 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	572 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	573 case MODE_PC_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	574 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	575 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	576 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	577 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	578 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	579 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	580 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	581 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	582 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	583 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	584 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	585 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	586 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	587 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	588 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	589 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	590 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	591 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	592 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	593 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	594 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	595 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	596 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	597 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	598 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	599 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	600 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	601 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	602 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	603 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	604 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	605 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	606 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	607 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	608 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	609 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	610 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	611 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	612 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	613 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	614 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	615 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	616 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	617 out = call(out, opts->read_8);
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	618 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	619 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	620 out = call(out, opts->read_16);
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	621 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	622 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	623 out = call(out, opts->read_32);
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	624 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	625 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	626 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	627 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	628 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	629 ea->base = SCRATCH1;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	630 break;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	631 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	632 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	633 //Add cycles for reading address from instruction stream
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	634 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS2 : BUS) : 0));
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	635 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	636 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	637 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	638 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	639 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	640 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	641 out = call(out, opts->read_8);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	642 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	643 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	644 out = call(out, opts->read_16);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	645 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	646 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	647 out = call(out, opts->read_32);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	648 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	649 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	650 out = pop_r(out, SCRATCH2);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	651 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	652 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	653 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	654 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	655 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	656 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	657 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	658 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	659 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	660 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	662
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	664 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	665 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	666 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	667 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	668 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	669 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	670 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	671 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	672 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	673 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	674 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	675 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	676 out = call(out, opts->write_8);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	677 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	678 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	679 out = call(out, opts->write_16);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	680 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	681 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	682 out = call(out, opts->write_32_lowfirst);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	683 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	684 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	685 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	686 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	687 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	688
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	689 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	690 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	691 address &= 0xFFFFFF;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	692 address /= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	693 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	694 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	695 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	696 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	697 uint32_t offset = address % NATIVE_CHUNK_SIZE;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	698 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET \|\| native_code_map[chunk].offsets[offset] == EXTENSION_WORD) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	699 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	700 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	701 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	702 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	703
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 228 diff changeset	704 uint8_t * get_native_from_context(m68k_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 228 diff changeset	705 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 228 diff changeset	706 return get_native_address(context->native_code_map, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 228 diff changeset	707 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 228 diff changeset	708
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	709 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	710 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	711 address &= 0xFFFFFF;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	712 address /= 2;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	713 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	714 if (!native_code_map[chunk].base) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	715 return 0;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	716 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	717 uint32_t offset = address % NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	718 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	719 return 0;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	720 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	721 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	722 --address;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	723 chunk = address / NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	724 offset = address % NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	725 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	726 return address*2;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	727 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	728
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	729 void map_native_address(m68k_context * context, uint32_t address, uint8_t * native_addr, uint8_t size, uint8_t native_size)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	730 {
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	731 native_map_slot * native_code_map = context->native_code_map;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	732 x86_68k_options * opts = context->options;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	733 address &= 0xFFFFFF;
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	734 if (address > 0xE00000) {
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	735 context->ram_code_flags[(address & 0xC000) >> 14] \|= 1 << ((address & 0x3800) >> 11);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	736 if (((address & 0x3FFF) + size) & 0xC000) {
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	737 context->ram_code_flags[((address+size) & 0xC000) >> 14] \|= 1 << (((address+size) & 0x3800) >> 11);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	738 }
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	739 uint32_t slot = (address & 0xFFFF)/1024;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	740 if (!opts->ram_inst_sizes[slot]) {
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	741 opts->ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	742 }
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	743 opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	744 }
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	745 address/= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	746 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	747 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	748 native_code_map[chunk].base = native_addr;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	749 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	750 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	751 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	752 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	753 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	754 for(address++,size-=2; size; address++,size-=2) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	755 chunk = address / NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	756 offset = address % NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	757 if (!native_code_map[chunk].base) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	758 native_code_map[chunk].base = native_addr;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	759 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	760 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	761 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	762 native_code_map[chunk].offsets[offset] = EXTENSION_WORD;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	763 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	764 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	765
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	766 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	767 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	768 if (address < 0xE00000) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	769 return 0;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	770 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	771 uint32_t slot = (address & 0xFFFF)/1024;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	772 return opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512];
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	773 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	774
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	775 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	776 {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	777 int8_t reg, flags_reg, sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	778 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	779 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	780 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	781 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	782 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	783 reg = native_reg(&(inst->dst), opts);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	784 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	785 //update statically set flags
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	786 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	787 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	788 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	789
216 0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	790 if (inst->dst.addr_mode != MODE_AREG) {
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	791 if (src.mode == MODE_REG_DIRECT) {
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	792 flags_reg = src.base;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	793 } else {
216 0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	794 if (reg >= 0) {
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	795 flags_reg = reg;
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	796 } else {
216 0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	797 if(src.mode == MODE_REG_DISPLACE8) {
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	798 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	799 } else {
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	800 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	801 }
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	802 src.mode = MODE_REG_DIRECT;
0b5ec22dcda2 Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source. Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	803 flags_reg = src.base = SCRATCH1;
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	804 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	805 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	806 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	807 uint8_t size = inst->extra.size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	808 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	809 {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	810 case MODE_AREG:
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	811 size = OPSIZE_LONG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	812 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	813 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	814 if (src.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	815 dst = mov_rr(dst, src.base, reg, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	816 } else if (src.mode == MODE_REG_DISPLACE8) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	817 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	818 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	819 dst = mov_ir(dst, src.disp, reg, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	820 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	821 } else if(src.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	822 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	823 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	824 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	825 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	826 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	827 dst = cmp_ir(dst, 0, flags_reg, size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	828 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	829 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	830 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	831 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	832 case MODE_AREG_PREDEC:
182 924af8b2f7a0 Fix -(a7) dest when size is byte Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	833 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	834 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	835 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	836 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	837 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	838 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	839 case MODE_AREG_INDIRECT:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	840 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	841 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	842 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	843 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	844 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	845 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	846 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	847 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	848 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	849 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	850 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	851 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	852 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	853 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	854 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	855 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	856 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	857 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	858 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	859 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	860 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	861 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	862 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	863 dst = call(dst, opts->write_8);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	864 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	865 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	866 dst = call(dst, opts->write_16);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	867 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	868 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	869 dst = call(dst, opts->write_32_highfirst);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	870 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	871 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	872 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
218 1abf8e967b33 Fix autoincrement on a7 when used as a destination in a byte sized instruction Mike Pavone <pavone@retrodev.com> parents: 216 diff changeset	873 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	874 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	875 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	876 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	877 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	878 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	879 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	880 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	881 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	882 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	883 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	884 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	885 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	886 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	887 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	888 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	889 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	890 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	891 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	892 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	893 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	894 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	895 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	896 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	897 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	898 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	899 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	900 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	901 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	902 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	903 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	904 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	905 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	906 dst = call(dst, opts->write_8);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	907 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	908 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	909 dst = call(dst, opts->write_16);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	910 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	911 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	912 dst = call(dst, opts->write_32_highfirst);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	913 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	914 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	915 break;
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	916 case MODE_AREG_INDEX_DISP8:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	917 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	918 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	919 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	920 } else {
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	921 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	922 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	923 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	924 if (inst->dst.params.regs.sec & 1) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	925 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	926 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	927 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	928 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	929 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	930 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	931 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	932 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	933 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	934 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	935 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	936 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	937 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	938 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	939 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	940 dst = push_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	941 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	942 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	943 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	944 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	945 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	946 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	947 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	948 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	949 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	950 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	951 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	952 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	953 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	954 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	955 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	956 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	957 dst = pop_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	958 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	959 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	960 if (inst->dst.params.regs.displacement) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	961 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	962 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	963 if (src.mode == MODE_REG_DIRECT) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	964 if (src.base != SCRATCH1) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	965 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	966 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	967 } else if (src.mode == MODE_REG_DISPLACE8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	968 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	969 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	970 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	971 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	972 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	973 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	974 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	975 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	976 }
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	977 switch (inst->extra.size)
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	978 {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	979 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	980 dst = call(dst, opts->write_8);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	981 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	982 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	983 dst = call(dst, opts->write_16);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	984 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	985 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	986 dst = call(dst, opts->write_32_highfirst);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	987 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	988 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	989 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	990 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	991 dst = cycles(dst, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	992 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	993 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	994 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	995 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	996 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	997 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	998 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	999 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1000 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1001 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1002 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1003 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1004 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1005 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1006 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1007 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1008 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1009 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1010 dst = call(dst, opts->write_8);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1011 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1012 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1013 dst = call(dst, opts->write_16);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1014 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1015 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1016 dst = call(dst, opts->write_32_highfirst);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1017 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1018 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1019 break;
196 f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1020 case MODE_PC_INDEX_DISP8:
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1021 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1022 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1023 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1024 if (inst->dst.params.regs.sec & 1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1025 if (inst->dst.params.regs.sec & 0x10) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1026 if (opts->aregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1027 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1028 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1029 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1030 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1031 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1032 if (opts->dregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1033 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1034 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1035 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1036 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1037 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1038 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1039 if (src.base == SCRATCH1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1040 dst = push_r(dst, SCRATCH1);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1041 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1042 if (inst->dst.params.regs.sec & 0x10) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1043 if (opts->aregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1044 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1045 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1046 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1047 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1048 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1049 if (opts->dregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1050 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1051 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1052 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1053 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1054 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1055 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1056 if (src.base == SCRATCH1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1057 dst = pop_r(dst, SCRATCH1);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1058 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1059 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1060 if (inst->dst.params.regs.displacement) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1061 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1062 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1063 if (src.mode == MODE_REG_DIRECT) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1064 if (src.base != SCRATCH1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1065 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1066 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1067 } else if (src.mode == MODE_REG_DISPLACE8) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1068 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1069 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1070 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1071 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1072 if (inst->dst.addr_mode != MODE_AREG) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1073 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1074 dst = setcc_r(dst, CC_Z, FLAG_Z);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1075 dst = setcc_r(dst, CC_S, FLAG_N);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1076 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1077 switch (inst->extra.size)
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1078 {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1079 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1080 dst = call(dst, opts->write_8);
196 f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1081 break;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1082 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1083 dst = call(dst, opts->write_16);
196 f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1084 break;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1085 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1086 dst = call(dst, opts->write_32_highfirst);
196 f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1087 break;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1088 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1089 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1090 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1091 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1092 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1093 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1094 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1095 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1096 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1097 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1098 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1099 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1100 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1101 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1102 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1103 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1104 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1105 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1106 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1107 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1108 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1109 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1110 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1111 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1112 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1113 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1114 case OPSIZE_BYTE:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1115 dst = call(dst, opts->write_8);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1116 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1117 case OPSIZE_WORD:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1118 dst = call(dst, opts->write_16);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1119 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1120 case OPSIZE_LONG:
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1121 dst = call(dst, opts->write_32_highfirst);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1122 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1123 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1124 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1125 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1126 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1127 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1128 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1129 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1130
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1131 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1132 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1133 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1134 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1135
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1136 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1137 {
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1138 int8_t bit,reg,sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1139 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1140 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1141 //reg to mem
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1142 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1143 int8_t dir;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1144 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1145 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1146 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1147 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1148 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1149 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1150 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1151 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1152 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1153 break;
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1154 case MODE_AREG_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1155 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1156 reg = SCRATCH2;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1157 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1158 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1159 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1160 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1161 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1162 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1163 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1164 case MODE_AREG_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1165 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1166 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1167 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1168 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1169 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1170 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1171 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1172 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1173 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1174 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1175 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1176 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1177 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1178 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1179 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1180 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1181 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1182 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1183 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1184 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1185 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1186 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1187 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1188 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1189 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1190 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1191 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1192 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1193 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1194 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1195 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1196 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1197 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1198 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1199 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1200 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1201 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1202 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1203 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1204 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1205 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1206 case MODE_PC_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1207 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1208 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1209 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1210 case MODE_PC_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1211 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1212 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1213 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1214 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1215 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1216 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1217 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1218 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1219 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1220 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1221 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1222 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1223 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1224 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1225 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1226 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1227 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1228 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1229 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1230 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1231 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1232 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1233 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1234 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1235 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1236 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1237 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1238 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1239 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1240 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1241 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1242 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1243 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1244 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1245 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1246 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1247 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1248 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1249 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1250 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1251 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1252 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1253 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1254 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1255 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1256 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1257 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1258 }
210 4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1259 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1260 reg = 15;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1261 dir = -1;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1262 } else {
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1263 reg = 0;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1264 dir = 1;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1265 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1266 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1267 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1268 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1269 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1270 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1271 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1272 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1273 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1274 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1275 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1276 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1277 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1278 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1279 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1280 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1281 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1282 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1283 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1284 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1285 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1286 if (inst->extra.size == OPSIZE_LONG) {
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1287 dst = call(dst, opts->write_32_lowfirst);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1288 } else {
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1289 dst = call(dst, opts->write_16);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1290 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1291 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1292 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1293 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1294 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1295 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1296 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1297 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1298 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1299 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1300 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1301 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1302 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1303 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1304 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1305 //mem to reg
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1306 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1307 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1308 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1309 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1310 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1311 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1312 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1313 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1314 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1315 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1316 break;
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1317 case MODE_AREG_DISPLACE:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1318 early_cycles += BUS;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1319 reg = SCRATCH2;
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1320 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1321 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1322 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1323 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1324 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1325 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1326 break;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1327 case MODE_AREG_INDEX_DISP8:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1328 early_cycles += 6;
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1329 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1330 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1331 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1332 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1333 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1334 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1335 if (inst->src.params.regs.sec & 1) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1336 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1337 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1338 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1339 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1340 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1341 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1342 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1343 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1344 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1345 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1346 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1347 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1348 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1349 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1350 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1351 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1352 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1353 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1354 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1355 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1356 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1357 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1358 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1359 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1360 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1361 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1362 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1363 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1364 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1365 if (inst->src.params.regs.displacement) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1366 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1367 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1368 break;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1369 case MODE_PC_DISPLACE:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1370 early_cycles += BUS;
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1371 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1372 break;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1373 case MODE_PC_INDEX_DISP8:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1374 early_cycles += 6;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1375 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1376 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1377 if (inst->src.params.regs.sec & 1) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1378 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1379 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1380 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1381 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1382 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1383 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1384 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1385 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1386 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1387 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1388 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1389 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1390 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1391 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1392 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1393 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1394 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1395 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1396 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1397 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1398 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1399 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1400 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1401 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1402 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1403 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1404 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1405 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1406 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1407 if (inst->src.params.regs.displacement) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1408 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1409 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1410 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1411 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1412 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1413 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1414 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1415 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1416 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1417 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1418 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1419 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1420 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1421 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1422 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1423 for(reg = 0; reg < 16; reg ++) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1424 if (inst->dst.params.immed & (1 << reg)) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1425 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1426 if (inst->extra.size == OPSIZE_LONG) {
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1427 dst = call(dst, opts->read_32);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1428 } else {
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1429 dst = call(dst, opts->read_16);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1430 }
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1431 if (inst->extra.size == OPSIZE_WORD) {
062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1432 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D);
062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1433 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1434 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1435 if (opts->aregs[reg-8] >= 0) {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1436 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1437 } else {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1438 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1439 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1440 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1441 if (opts->dregs[reg] >= 0) {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1442 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1443 } else {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1444 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1445 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1446 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1447 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1448 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1449 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1450 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1451 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1452 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1453 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1454 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1455 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1456 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1457 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1458 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1459 //prefetch
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1460 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1461 return dst;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1462 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1463
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1464 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1465 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1466 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1467 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1468 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1469 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1470 int8_t reg = native_reg(&(inst->dst), opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1471 if (reg >= 0) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1472 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1473 return xor_rr(dst, reg, reg, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1474 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1475 x86_ea dst_op;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1476 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1477 if (dst_op.mode == MODE_REG_DIRECT) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1478 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1479 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1480 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1481 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1482 dst = m68k_save_result(inst, dst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1483 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1484 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1485
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1486 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1487 {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1488 x86_ea dst_op;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1489 uint8_t dst_size = inst->extra.size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1490 inst->extra.size--;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1491 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1492 if (dst_op.mode == MODE_REG_DIRECT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1493 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1494 dst = cmp_ir(dst, 0, dst_op.base, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1495 } else {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1496 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1497 dst = cmp_ir(dst, 0, SCRATCH1, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1498 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1499 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1500 inst->extra.size = dst_size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1501 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1502 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1503 dst = setcc_r(dst, CC_Z, FLAG_Z);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1504 dst = setcc_r(dst, CC_S, FLAG_N);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1505 //M68K EXT only operates on registers so no need for a call to save result here
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1506 return dst;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1507 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1508
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1509 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1510 {
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1511 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1512 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1513 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1514 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1515 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1516 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1517 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1518 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1519 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1520 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1521 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1522 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1523 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1524 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1525 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1526 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1527 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1528 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1529 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1530 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1531 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1532 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1533 if (dst_reg >= 0) {
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1534 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1535 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1536 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1537 } else {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1538 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1539 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1540 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1541 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1542 } else {
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1543 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1544 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1545 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1546 } else {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1547 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1548 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1549 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1550 }
165 62b152811bae Fix certain address modes with lea when the destination is not a native register Mike Pavone <pavone@retrodev.com> parents: 162 diff changeset	1551 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1552 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1553 break;
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1554 case MODE_AREG_INDEX_DISP8:
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1555 dst = cycles(dst, 12);
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1556 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1557 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1558 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1559 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1560 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1561 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1562 if (inst->src.params.regs.sec & 1) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1563 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1564 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1565 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1566 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1567 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1568 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1569 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1570 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1571 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1572 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1573 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1574 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1575 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1576 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1577 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1578 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1579 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1580 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1581 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1582 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1583 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1584 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1585 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1586 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1587 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1588 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1589 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1590 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1591 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1592 if (inst->src.params.regs.displacement) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1593 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1594 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1595 if (dst_reg >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1596 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1597 } else {
165 62b152811bae Fix certain address modes with lea when the destination is not a native register Mike Pavone <pavone@retrodev.com> parents: 162 diff changeset	1598 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1599 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1600 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1601 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1602 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1603 if (dst_reg >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1604 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1605 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1606 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1607 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1608 break;
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1609 case MODE_PC_INDEX_DISP8:
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1610 dst = cycles(dst, BUS*3);
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1611 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1612 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1613 if (inst->src.params.regs.sec & 1) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1614 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1615 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1616 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1617 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1618 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1619 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1620 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1621 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1622 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1623 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1624 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1625 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1626 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1627 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1628 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1629 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1630 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1631 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1632 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1633 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1634 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1635 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1636 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1637 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1638 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1639 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1640 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1641 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1642 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1643 if (inst->src.params.regs.displacement) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1644 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1645 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1646 if (dst_reg >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1647 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1648 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1649 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1650 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1651 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1652 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1653 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1654 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1655 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1656 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1657 } else {
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1658 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1659 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1660 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1661 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1662 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1663 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1664 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1665 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1666 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1667 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1668
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1669 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1670 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1671 uint8_t sec_reg;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1672 switch(inst->src.addr_mode)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1673 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1674 case MODE_AREG_INDIRECT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1675 dst = cycles(dst, BUS);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1676 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1677 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1678 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1679 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1680 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1681 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1682 case MODE_AREG_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1683 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1684 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1685 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1686 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1687 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1688 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1689 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1690 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1691 case MODE_AREG_INDEX_DISP8:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1692 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1693 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1694 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1695 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1696 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1697 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1698 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1699 if (inst->src.params.regs.sec & 1) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1700 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1701 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1702 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1703 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1704 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1705 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1706 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1707 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1708 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1709 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1710 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1711 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1712 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1713 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1714 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1715 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1716 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1717 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1718 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1719 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1720 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1721 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1722 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1723 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1724 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1725 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1726 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1727 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1728 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1729 if (inst->src.params.regs.displacement) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1730 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1731 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1732 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1733 case MODE_PC_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1734 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1735 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1736 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1737 case MODE_ABSOLUTE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1738 case MODE_ABSOLUTE_SHORT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1739 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1740 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1741 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1742 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1743 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1744 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1745 exit(1);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1746 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1747 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1748 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1749 dst = call(dst, opts->write_32_lowfirst);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1750 return dst;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1751 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1752
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1753 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1754 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1755 int32_t disp = inst->src.params.immed;
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1756 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1757 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1758 dst = cycles(dst, 10);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1759 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1760 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1761 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1762 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1763 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1764 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	1765 dst = call(dst, opts->write_32_highfirst);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1766 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1767 if (!dest_addr) {
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1768 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1769 //dummy address to be replaced later
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1770 dest_addr = dst + 256;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1771 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1772 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1773 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1774 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1775 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1776 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1777 dst = jmp(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1778 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1779 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1780 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1781
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1782 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1783 {
156 3900cfde9dbb Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive) Mike Pavone <pavone@retrodev.com> parents: 155 diff changeset	1784 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1785 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1786 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1787 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1788 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1789 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1790 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1791 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1792 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1793 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1794 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1795 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1796 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1797 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1798 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1799 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1800 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1801 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1802 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1803 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1804 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1805 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1806 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1807 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1808 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1809 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1810 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1811 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1812 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1813 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1814 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1815 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1816 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1817 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1818 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1819 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1820 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1821 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1822 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1823 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1824 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1825 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1826 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1827 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1828 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1829 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1830 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1831 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1832 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1833 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1834 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1835 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1836 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1837 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1838 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1839 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1840 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1841 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1842 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1843 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1844 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1845 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1846 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1847
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1848 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1849 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1850 uint8_t cond = inst->extra.cond;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1851 x86_ea dst_op;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1852 inst->extra.size = OPSIZE_BYTE;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1853 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1854 if (cond == COND_TRUE \|\| cond == COND_FALSE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1855 if ((inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1856 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1857 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1858 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1859 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1860 if (dst_op.mode == MODE_REG_DIRECT) {
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1861 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1862 } else {
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1863 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1864 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1865 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1866 uint8_t cc = CC_NZ;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1867 switch (cond)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1868 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1869 case COND_HIGH:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1870 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1871 case COND_LOW_SAME:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1872 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1873 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1874 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1875 case COND_CARRY_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1876 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1877 case COND_CARRY_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1878 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1879 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1880 case COND_NOT_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1881 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1882 case COND_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1883 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1884 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1885 case COND_OVERF_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1886 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1887 case COND_OVERF_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1888 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1889 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1890 case COND_PLUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1891 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1892 case COND_MINUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1893 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1894 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1895 case COND_GREATER_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1896 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1897 case COND_LESS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1898 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1899 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1900 case COND_GREATER:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1901 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1902 case COND_LESS_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1903 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1904 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1905 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1906 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1907 }
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1908 uint8_t *true_off = dst + 1;
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1909 dst = jcc(dst, cc, dst+2);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1910 dst = cycles(dst, BUS);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1911 if (dst_op.mode == MODE_REG_DIRECT) {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1912 dst = mov_ir(dst, 0, dst_op.base, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1913 } else {
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1914 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1915 }
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1916 uint8_t *end_off = dst+1;
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1917 dst = jmp(dst, dst+2);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1918 *true_off = dst - (true_off+1);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1919 dst = cycles(dst, 6);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1920 if (dst_op.mode == MODE_REG_DIRECT) {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1921 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1922 } else {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1923 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1924 }
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1925 *end_off = dst - (end_off+1);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1926 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1927 dst = m68k_save_result(inst, dst, opts);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1928 return dst;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1929 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1930
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1931 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1932 {
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1933 uint8_t * dest_addr, sec_reg;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1934 uint32_t m68k_addr;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1935 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1936 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1937 case MODE_AREG_INDIRECT:
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1938 dst = cycles(dst, BUS*2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1939 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1940 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1941 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1942 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1943 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1944 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1945 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1946 break;
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1947 case MODE_AREG_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1948 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1949 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1950 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1951 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1952 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1953 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1954 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1955 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1956 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1957 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1958 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1959 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1960 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1961 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1962 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1963 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1964 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1965 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1966 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1967 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1968 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1969 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1970 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1971 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1972 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1973 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1974 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1975 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1976 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1977 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1978 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1979 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1980 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1981 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1982 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1983 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1984 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1985 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1986 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1987 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1988 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1989 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1990 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1991 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1992 dst = cycles(dst, 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1993 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1994 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1995 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1996 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1997 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1998 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1999 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2000 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2001 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2002 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2003 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2004 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2005 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2006 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2007 break;
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2008 case MODE_PC_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2009 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2010 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2011 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2012 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2013 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2014 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2015 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2016 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2017 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2018 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2019 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2020 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2021 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2022 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2023 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2024 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2025 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2026 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2027 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2028 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2029 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2030 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2031 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2032 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2033 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2034 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2035 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2036 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2037 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2038 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2039 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2040 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2041 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2042 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2043 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2044 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2045 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2046 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2047 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2048 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2049 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2050 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2051 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2052 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2053 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2054 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2055 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2056 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2057 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2058 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2059 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2060 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2061 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2062 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2063 dst = jmp_r(dst, SCRATCH1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2064 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2065 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2066 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2067 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2068 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode);
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 102 diff changeset	2069 exit(1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2070 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2071 return dst;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2072 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2073
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2074 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2075 {
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2076 uint8_t * dest_addr, sec_reg;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2077 uint32_t after;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2078 uint32_t m68k_addr;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2079 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2080 {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2081 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2082 dst = cycles(dst, BUS*2);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2083 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2084 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2085 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2086 }
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	2087 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	2088 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2089 dst = call(dst, opts->write_32_highfirst);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2090 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2091 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2092 } else {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2093 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2094 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2095 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2096 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2097 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2098 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2099 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2100 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2101 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2102 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2103 break;
174 a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2104 case MODE_AREG_DISPLACE:
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2105 dst = cycles(dst, BUS*2);
187 8e138da572ab Fix return address for areg displacement mode JSR Mike Pavone <pavone@retrodev.com> parents: 184 diff changeset	2106 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
174 a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2107 if (opts->flags & OPT_NATIVE_CALL_STACK) {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2108 dst = push_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2109 }
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2110 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2111 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2112 dst = call(dst, opts->write_32_highfirst);
174 a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2113 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2114 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2115 } else {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2116 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2117 }
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2118 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2119 dst = call(dst, (uint8_t *)m68k_native_addr);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2120 if (opts->flags & OPT_NATIVE_CALL_STACK) {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2121 dst = call_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2122 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2123 dst = pop_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2124 } else {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2125 dst = jmp_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2126 }
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2127 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2128 case MODE_AREG_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2129 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2130 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2131 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2132 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2133 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2134 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2135 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2136 dst = call(dst, opts->write_32_highfirst);
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2137 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2138 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2139 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2140 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2141 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2142 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2143 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2144 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2145 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2146 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2147 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2148 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2149 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2150 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2151 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2152 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2153 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2154 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2155 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2156 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2157 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2158 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2159 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2160 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2161 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2162 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2163 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2164 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2165 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2166 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2167 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2168 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2169 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2170 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2171 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2172 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2173 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2174 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2175 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2176 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2177 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2178 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2179 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2180 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2181 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2182 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2183 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2184 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2185 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2186 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2187 dst = cycles(dst, 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2188 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2189 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2190 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2191 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2192 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2193 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2194 dst = call(dst, opts->write_32_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2195 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2196 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2197 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2198 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2199 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2200 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2201 dest_addr = dst + 256;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2202 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2203 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2204 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2205 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2206 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2207 }
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2208 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2209 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2210 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2211 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2212 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2213 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2214 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2215 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2216 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2217 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2218 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2219 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2220 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2221 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2222 case MODE_PC_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2223 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2224 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2225 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2226 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2227 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2228 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2229 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2230 dst = call(dst, opts->write_32_highfirst);
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2231 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2232 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2233 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2234 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2235 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2236 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2237 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2238 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2239 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2240 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2241 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2242 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2243 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2244 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2245 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2246 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2247 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2248 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2249 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2250 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2251 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2252 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2253 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2254 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2255 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2256 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2257 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2258 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2259 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2260 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2261 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2262 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2263 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2264 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2265 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2266 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2267 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2268 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2269 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2270 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2271 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2272 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2273 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2274 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2275 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2276 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2277 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2278 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2279 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2280 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2281 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2282 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2283 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2284 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2285 dst = call(dst, opts->write_32_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2286 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2287 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2288 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2289 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2290 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2291 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2292 dest_addr = dst + 256;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2293 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2294 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2295 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2296 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2297 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2298 }
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2299 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2300 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2301 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2302 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2303 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2304 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2305 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2306 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2307 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2308 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2309 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2310 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2311 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2312 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2313 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2314 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2315 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode);
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2316 exit(1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2317 }
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2318 return dst;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2319 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2320
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2321 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2322 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2323 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2324 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2325 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2326 dst = call(dst, opts->read_32);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2327 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2328 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2329 dst = jcc(dst, CC_NZ, dst+3);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2330 dst = retn(dst);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2331 dst = jmp(dst, (char *)m68k_modified_ret_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2332 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2333 dst = call(dst, (uint8_t *)m68k_native_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2334 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2335 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2336 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2337 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2338
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2339 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2340 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2341 //best case duration
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2342 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2343 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2344 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2345 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2346 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2347 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2348 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2349 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2350 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2351 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2352 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2353 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2354 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2355 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2356 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2357 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2358 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2359 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2360 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2361 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2362 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2363 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2364 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2365 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2366 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2367 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2368 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2369 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2370 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2371 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2372 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2373 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2374 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2375 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2376 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2377 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2378 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2379 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2380 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2381 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2382 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2383 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2384 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2385 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2386 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2387 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2388 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2389 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2390 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2391 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2392 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2393 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2394 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2395 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2396 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2397 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2398 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2399 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2400 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2401 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2402 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2403 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2404 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2405 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2406 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2407 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2408 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2409 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2410 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2411 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2412 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2413 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2414 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2415 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2416 }
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2417 return dst;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2418 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2419
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2420 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2421 {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2422 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2423 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2424 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2425 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2426 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2427 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2428 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2429 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2430 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2431 }
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2432 dst = call(dst, opts->write_32_highfirst);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2433 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2434 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2435 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2436 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2437 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2438 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2439 //prefetch
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2440 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2441 return dst;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2442 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2443
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2444 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2445 {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2446 int8_t reg;
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2447 dst = cycles(dst, BUS*2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2448 if (inst->src.addr_mode == MODE_REG) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2449 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2450 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2451 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2452 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2453 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2454 if (inst->dst.params.regs.displacement) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2455 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2456 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2457 reg = native_reg(&(inst->src), opts);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2458 if (inst->extra.size == OPSIZE_LONG) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2459 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2460 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2461 dst = shr_ir(dst, 24, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2462 dst = push_r(dst, SCRATCH2);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2463 dst = call(dst, opts->write_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2464 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2465 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2466 dst = shr_ir(dst, 16, SCRATCH1, SZ_D);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	2467
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2468 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2469 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2470 dst = push_r(dst, SCRATCH2);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2471 dst = call(dst, opts->write_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2472 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2473 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2474 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2475 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2476 dst = push_r(dst, SCRATCH2);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2477 dst = call(dst, opts->write_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2478 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2479 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2480 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2481 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2482 dst = mov_rr(dst, reg, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2483 dst = shr_ir(dst, 8, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2484 dst = push_r(dst, SCRATCH2);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2485 dst = call(dst, opts->write_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2486 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2487 dst = mov_rr(dst, reg, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2488 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2489 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2490 dst = push_r(dst, SCRATCH2);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2491 dst = call(dst, opts->write_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2492 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2493 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2494 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2495 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2496 dst = call(dst, opts->write_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2497 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2498 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2499 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2500 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2501 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2502 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2503 if (inst->src.params.regs.displacement) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2504 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2505 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2506 reg = native_reg(&(inst->dst), opts);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2507 if (inst->extra.size == OPSIZE_LONG) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2508 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2509 dst = push_r(dst, SCRATCH1);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2510 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2511 dst = shl_ir(dst, 24, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2512 dst = mov_rr(dst, SCRATCH1, reg, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2513 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2514 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2515 dst = push_r(dst, SCRATCH1);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2516 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2517 dst = shl_ir(dst, 16, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2518 dst = or_rr(dst, SCRATCH1, reg, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2519 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2520 dst = push_r(dst, SCRATCH1);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2521 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2522 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2523 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2524 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2525 dst = push_r(dst, SCRATCH1);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2526 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2527 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2528 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2529 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2530 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2531 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2532 dst = push_r(dst, SCRATCH1);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2533 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2534 if (reg >= 0) {
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	2535
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2536 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2537 dst = mov_rr(dst, SCRATCH1, reg, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2538 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2539 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2540 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2541 dst = mov_rr(dst, SCRATCH1, reg, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2542 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2543 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2544 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2545 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	2546 dst = call(dst, opts->read_8);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2547 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2548 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2549 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2550 return dst;
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2551 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2552
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2553 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2554 {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2555 uint8_t size = inst->extra.size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2556 x86_ea src_op, dst_op;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2557 dst = translate_m68k_src(inst, &src_op, dst, opts);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2558 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2559 dst = push_r(dst, SCRATCH1);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2560 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2561 dst = pop_r(dst, SCRATCH2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2562 src_op.base = SCRATCH2;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2563 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2564 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2565 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2566 size = OPSIZE_LONG;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2567 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2568 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2569 dst = cycles(dst, BUS);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2570 if (src_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2571 if (dst_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2572 dst = cmp_rr(dst, src_op.base, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2573 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2574 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2575 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2576 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2577 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2578 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2579 if (dst_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2580 dst = cmp_ir(dst, src_op.disp, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2581 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2582 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2583 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2584 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2585 dst = setcc_r(dst, CC_C, FLAG_C);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2586 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2587 dst = setcc_r(dst, CC_S, FLAG_N);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2588 dst = setcc_r(dst, CC_O, FLAG_V);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2589 return dst;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2590 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2591
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2592 typedef uint8_t * (shift_ir_t)(uint8_t out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2593 typedef uint8_t * (shift_irdisp8_t)(uint8_t out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2594 typedef uint8_t * (shift_clr_t)(uint8_t out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2595 typedef uint8_t * (shift_clrdisp8_t)(uint8_t out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2596
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2597 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea src_op, x86_ea dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2598 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2599 uint8_t * end_off = NULL;
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2600 uint8_t * nz_off = NULL;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2601 uint8_t * z_off = NULL;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2602 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2603 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2604 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2605 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2606 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2607 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2608 if (src_op->mode == MODE_IMMED) {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2609 if (src_op->disp != 1 && inst->op == M68K_ASL) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2610 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2611 for (int i = 0; i < src_op->disp; i++) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2612 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2613 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2614 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2615 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2616 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2617 //dst = setcc_r(dst, CC_O, FLAG_V);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2618 dst = jcc(dst, CC_NO, dst+4);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2619 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2620 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2621 } else {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2622 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2623 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2624 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2625 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2626 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	2627 dst = setcc_r(dst, CC_O, FLAG_V);
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2628 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2629 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2630 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2631 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2632 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2633 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2634 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2635 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	2636
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2637 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2638 dst = and_ir(dst, 63, RCX, SZ_D);
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2639 nz_off = dst+1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2640 dst = jcc(dst, CC_NZ, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2641 //Flag behavior for shift count of 0 is different for x86 than 68K
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2642 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2643 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2644 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2645 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2646 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2647 dst = setcc_r(dst, CC_Z, FLAG_Z);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2648 dst = setcc_r(dst, CC_S, FLAG_N);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2649 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2650 //For other instructions, this flag will be set below
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2651 if (inst->op == M68K_ASL) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2652 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2653 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2654 z_off = dst+1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2655 dst = jmp(dst, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2656 *nz_off = dst - (nz_off + 1);
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2657 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2658 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2659 dst = add_rr(dst, RCX, CYCLES, SZ_D);
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2660 if (inst->op == M68K_ASL) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2661 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2662 //Easiest way to deal with this is to shift one bit at a time
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2663 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2664 uint8_t * loop_start = dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2665 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2666 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2667 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2668 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2669 }
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2670 //dst = setcc_r(dst, CC_O, FLAG_V);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2671 dst = jcc(dst, CC_NO, dst+4);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2672 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2673 dst = loop(dst, loop_start);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2674 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2675 //x86 shifts modulo 32 for operand sizes less than 64-bits
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2676 //but M68K shifts modulo 64, so we need to check for large shifts here
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2677 dst = cmp_ir(dst, 32, RCX, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2678 uint8_t * norm_shift_off = dst + 1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2679 dst = jcc(dst, CC_L, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2680 if (special) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2681 if (inst->extra.size == OPSIZE_LONG) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2682 uint8_t * neq_32_off = dst + 1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2683 dst = jcc(dst, CC_NZ, dst+2);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	2684
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2685 //set the carry bit to the lsb
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2686 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2687 dst = special(dst, 1, dst_op->base, SZ_D);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2688 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2689 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2690 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2691 dst = setcc_r(dst, CC_C, FLAG_C);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2692 dst = jmp(dst, dst+4);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2693 *neq_32_off = dst - (neq_32_off+1);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2694 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2695 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2696 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2697 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2698 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2699 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2700 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2701 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2702 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2703 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2704 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2705 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2706 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2707 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2708 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2709 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2710 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	2711
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2712 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2713 end_off = dst+1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2714 dst = jmp(dst, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2715 *norm_shift_off = dst - (norm_shift_off+1);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2716 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2717 dst = shift_clr(dst, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2718 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2719 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2720 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2721 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2722 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	2723
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2724 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2725 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2726 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2727 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2728 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2729 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2730 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2731 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2732 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2733 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2734 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2735 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2736 if (z_off) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2737 *z_off = dst - (z_off + 1);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2738 }
219 8d3c16071559 Fix overflow flag behavior for lsl/lsr/asr Mike Pavone <pavone@retrodev.com> parents: 218 diff changeset	2739 if (inst->op != M68K_ASL) {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2740 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2741 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2742 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2743 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2744 }
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	2745 return dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2746 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2747
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2748 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2749
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2750 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2751 {
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2752 uint8_t * end_off, zero_off, norm_off;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2753 uint8_t dst_reg;
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	2754 dst = check_cycles_int(dst, inst->address, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2755 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2756 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2757 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2758 return translate_m68k_lea(dst, inst, opts);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	2759 } else if(inst->op == M68K_PEA) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	2760 return translate_m68k_pea(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2761 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2762 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2763 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2764 return translate_m68k_bcc(dst, inst, opts);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2765 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2766 return translate_m68k_jmp(dst, inst, opts);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2767 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2768 return translate_m68k_jsr(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2769 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2770 return translate_m68k_rts(dst, inst, opts);
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2771 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2772 return translate_m68k_dbcc(dst, inst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2773 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2774 return translate_m68k_clr(dst, inst, opts);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2775 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2776 return translate_m68k_movem(dst, inst, opts);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2777 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2778 return translate_m68k_link(dst, inst, opts);
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2779 } else if(inst->op == M68K_EXT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2780 return translate_m68k_ext(dst, inst, opts);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2781 } else if(inst->op == M68K_SCC) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2782 return translate_m68k_scc(dst, inst, opts);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2783 } else if(inst->op == M68K_MOVEP) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2784 return translate_m68k_movep(dst, inst, opts);
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	2785 } else if(inst->op == M68K_INVALID) {
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	2786 if (inst->src.params.immed == 0x7100) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	2787 return retn(dst);
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	2788 }
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	2789 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D);
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	2790 return call(dst, (uint8_t *)m68k_invalid);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2791 } else if(inst->op == M68K_CMP) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2792 return translate_m68k_cmp(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2793 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2794 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2795 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2796 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2797 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2798 if (inst->dst.addr_mode != MODE_UNUSED) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	2799 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2800 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2801 uint8_t size;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2802 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2803 {
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2804 case M68K_ABCD:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2805 if (src_op.base != SCRATCH2) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2806 if (src_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2807 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2808 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2809 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2810 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2811 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2812 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2813 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2814 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2815 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2816 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2817 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2818 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2819 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2820 dst = jcc(dst, CC_NC, dst+5);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2821 dst = add_ir(dst, 1, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2822 dst = call(dst, (uint8_t *)bcd_add);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2823 dst = mov_rr(dst, CH, FLAG_C, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2824 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2825 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2826 dst = jcc(dst, CC_Z, dst+4);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2827 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2828 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2829 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2830 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2831 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2832 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2833 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2834 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2835 dst = m68k_save_result(inst, dst, opts);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2836 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2837 case M68K_ADD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2838 dst = cycles(dst, BUS);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2839 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2840 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2841 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2842 dst = add_rr(dst, src_op.base, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2843 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2844 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2845 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2846 } else if (src_op.mode == MODE_REG_DISPLACE8) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2847 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2848 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2849 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2850 dst = add_ir(dst, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2851 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2852 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2853 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2854 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2855 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2856 dst = setcc_r(dst, CC_C, FLAG_C);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2857 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2858 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2859 dst = setcc_r(dst, CC_O, FLAG_V);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2860 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2861 }
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2862 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2863 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2864 case M68K_ADDX:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2865 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2866 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2867 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2868 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2869 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2870 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2871 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2872 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2873 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2874 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2875 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2876 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2877 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2878 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2879 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2880 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2881 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2882 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2883 dst = jcc(dst, CC_Z, dst+4);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2884 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2885 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2886 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2887 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2888 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2889 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2890 case M68K_AND:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2891 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2892 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2893 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2894 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2895 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2896 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2897 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2898 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2899 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2900 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2901 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2902 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2903 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2904 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2905 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2906 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2907 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2908 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2909 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2910 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2911 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2912 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2913 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2914 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2915 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2916 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2917 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2918 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2919 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2920 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2921 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2922 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2923 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2924 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2925 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2926 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2927 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2928 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2929 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2930 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2931 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2932 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2933 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2934 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2935 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2936 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2937 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2938 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2939 }
321 146c87616b05 Don't update interrupt mask on non-interrupt exceptions Mike Pavone <pavone@retrodev.com> parents: 319 diff changeset	2940 //dst = call(dst, (uint8_t *)debug_print_sr);
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2941 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2942 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2943 }
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2944 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2945 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2946 case M68K_ASL:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2947 case M68K_LSL:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2948 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2949 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2950 case M68K_ASR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2951 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2952 break;
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2953 case M68K_LSR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2954 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2955 break;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2956 case M68K_BCHG:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2957 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2958 case M68K_BSET:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2959 case M68K_BTST:
457 6a315728fede Fix bit instruction timing Mike Pavone <pavone@retrodev.com> parents: 447 diff changeset	2960 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : (
6a315728fede Fix bit instruction timing Mike Pavone <pavone@retrodev.com> parents: 447 diff changeset	2961 inst->op == M68K_BTST ? 6 : (inst->op == M68K_BCLR ? 10 : 8))
6a315728fede Fix bit instruction timing Mike Pavone <pavone@retrodev.com> parents: 447 diff changeset	2962 );
67 534eb4976423 Fix BTST Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	2963 if (src_op.mode == MODE_IMMED) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2964 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2965 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2966 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2967 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2968 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2969 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2970 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2971 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2972 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2973 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2974 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2975 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2976 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2977 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2978 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2979 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2980 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2981 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2982 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2983 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2984 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2985 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2986 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2987 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2988 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2989 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2990 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2991 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2992 } else {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	2993 if (src_op.mode == MODE_REG_DISPLACE8 \|\| (inst->dst.addr_mode != MODE_REG && src_op.base != SCRATCH1 && src_op.base != SCRATCH2)) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2994 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2995 dst = push_r(dst, SCRATCH2);
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	2996 if (src_op.mode == MODE_REG_DIRECT) {
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	2997 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B);
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	2998 } else {
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	2999 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3000 }
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3001 src_op.base = SCRATCH2;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3002 } else {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3003 if (src_op.mode == MODE_REG_DIRECT) {
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3004 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3005 } else {
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3006 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3007 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3008 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3009 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3010 }
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3011 uint8_t size = inst->extra.size;
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3012 if (dst_op.mode == MODE_REG_DISPLACE8) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3013 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3014 if (src_op.mode == MODE_REG_DIRECT) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3015 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3016 } else {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3017 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3018 src_op.mode = MODE_REG_DIRECT;
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3019 }
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3020 src_op.base = SCRATCH1;
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3021 }
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3022 //b### with register destination is modulo 32
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3023 //x86 with a memory destination isn't modulo anything
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3024 //so use an and here to force the value to be modulo 32
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3025 dst = and_ir(dst, 31, SCRATCH1, SZ_D);
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3026 } else if(inst->dst.addr_mode != MODE_REG) {
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3027 //b### with memory destination is modulo 8
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3028 //x86-64 doesn't support 8-bit bit operations
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3029 //so we fake it by forcing the bit number to be modulo 8
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3030 dst = and_ir(dst, 7, src_op.base, SZ_D);
71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3031 size = SZ_D;
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3032 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3033 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3034 if (dst_op.mode == MODE_REG_DIRECT) {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3035 dst = bt_rr(dst, src_op.base, dst_op.base, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3036 } else {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3037 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3038 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3039 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3040 if (dst_op.mode == MODE_REG_DIRECT) {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3041 dst = bts_rr(dst, src_op.base, dst_op.base, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3042 } else {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3043 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3044 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3045 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3046 if (dst_op.mode == MODE_REG_DIRECT) {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3047 dst = btr_rr(dst, src_op.base, dst_op.base, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3048 } else {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3049 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3050 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3051 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3052 if (dst_op.mode == MODE_REG_DIRECT) {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3053 dst = btc_rr(dst, src_op.base, dst_op.base, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3054 } else {
221 71f6b76639db Fix modulo on bit operations with a memory destination Mike Pavone <pavone@retrodev.com> parents: 219 diff changeset	3055 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3056 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3057 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3058 if (src_op.base == SCRATCH2) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3059 dst = pop_r(dst, SCRATCH2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3060 }
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3061 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3062 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3063 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3064 dst = setcc_r(dst, CC_NC, FLAG_Z);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3065 if (inst->op != M68K_BTST) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3066 dst = m68k_save_result(inst, dst, opts);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3067 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3068 break;
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3069 case M68K_CHK:
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3070 {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3071 dst = cycles(dst, 6);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3072 if (dst_op.mode == MODE_REG_DIRECT) {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3073 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3074 } else {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3075 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3076 }
324 4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3077 uint32_t isize;
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3078 switch(inst->src.addr_mode)
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3079 {
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3080 case MODE_AREG_DISPLACE:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3081 case MODE_AREG_INDEX_DISP8:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3082 case MODE_ABSOLUTE_SHORT:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3083 case MODE_PC_INDEX_DISP8:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3084 case MODE_PC_DISPLACE:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3085 case MODE_IMMEDIATE:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3086 isize = 4;
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3087 break;
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3088 case MODE_ABSOLUTE:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3089 isize = 6;
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3090 break;
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3091 default:
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3092 isize = 2;
4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3093 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3094 uint8_t * passed = dst+1;
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3095 dst = jcc(dst, CC_GE, dst+2);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3096 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3097 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D);
324 4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3098 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D);
348 3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	3099 dst = jmp(dst, opts->trap);
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3100 *passed = dst - (passed+1);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3101 if (dst_op.mode == MODE_REG_DIRECT) {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3102 if (src_op.mode == MODE_REG_DIRECT) {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3103 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3104 } else if(src_op.mode == MODE_REG_DISPLACE8) {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3105 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3106 } else {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3107 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3108 }
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3109 } else if(dst_op.mode == MODE_REG_DISPLACE8) {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3110 if (src_op.mode == MODE_REG_DIRECT) {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3111 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3112 } else {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3113 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3114 }
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3115 }
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3116 passed = dst+1;
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3117 dst = jcc(dst, CC_LE, dst+2);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3118 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3119 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D);
324 4f2711899866 Fix retrun address calculation for CHK exceptions Mike Pavone <pavone@retrodev.com> parents: 321 diff changeset	3120 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D);
348 3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	3121 dst = jmp(dst, opts->trap);
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3122 *passed = dst - (passed+1);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3123 dst = cycles(dst, 4);
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3124 break;
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3125 }
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3126 case M68K_DIVS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3127 case M68K_DIVU:
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3128 {
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3129 //TODO: cycle exact division
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3130 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140);
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3131 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3132 dst = push_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3133 dst = push_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3134 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3135 dst = mov_rr(dst, dst_op.base, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3136 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3137 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3138 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3139 if (src_op.mode == MODE_IMMED) {
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3140 dst = mov_ir(dst, (src_op.disp & 0x8000) && inst->op == M68K_DIVS ? src_op.disp \| 0xFFFF0000 : src_op.disp, SCRATCH2, SZ_D);
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3141 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3142 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3143 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3144 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3145 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3146 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3147 } else if (src_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3148 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3149 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3150 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3151 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3152 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3153 }
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3154 dst = cmp_ir(dst, 0, SCRATCH2, SZ_D);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3155 uint8_t * not_zero = dst+1;
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3156 dst = jcc(dst, CC_NZ, dst+2);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3157 dst = pop_r(dst, RAX);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3158 dst = pop_r(dst, RDX);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3159 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3160 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
348 3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	3161 dst = jmp(dst, opts->trap);
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3162 *not_zero = dst - (not_zero+1);
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3163 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3164 dst = cdq(dst);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3165 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3166 dst = xor_rr(dst, RDX, RDX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3167 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3168 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3169 dst = idiv_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3170 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3171 dst = div_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3172 }
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3173 uint8_t * skip_sec_check;
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3174 if (inst->op == M68K_DIVS) {
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3175 dst = cmp_ir(dst, 0x8000, RAX, SZ_D);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3176 skip_sec_check = dst + 1;
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3177 dst = jcc(dst, CC_GE, dst+2);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3178 dst = cmp_ir(dst, -0x8000, RAX, SZ_D);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3179 norm_off = dst+1;
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3180 dst = jcc(dst, CC_L, dst+2);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3181 } else {
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3182 dst = cmp_ir(dst, 0x10000, RAX, SZ_D);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3183 norm_off = dst+1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3184 dst = jcc(dst, CC_NC, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3185 }
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3186 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3187 dst = mov_rr(dst, RDX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3188 dst = shl_ir(dst, 16, dst_op.base, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3189 dst = mov_rr(dst, RAX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3190 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3191 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3192 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3193 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3194 }
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3195 dst = cmp_ir(dst, 0, RAX, SZ_W);
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3196 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3197 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3198 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3199 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3200 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3201 end_off = dst+1;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3202 dst = jmp(dst, dst+2);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3203 *norm_off = dst - (norm_off + 1);
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3204 if (inst->op == M68K_DIVS) {
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3205 *skip_sec_check = dst - (skip_sec_check+1);
1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3206 }
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3207 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3208 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3209 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3210 *end_off = dst - (end_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3211 break;
228 1ed81ef2a3a2 Fix overflow detection in divs. Fix negative immediate source for divs Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	3212 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3213 case M68K_EOR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3214 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3215 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3216 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3217 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3218 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3219 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3220 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3221 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3222 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3223 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3224 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3225 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3226 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3227 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3228 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3229 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3230 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3231 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3232 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3233 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3234 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3235 break;
171 f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3236 case M68K_EORI_CCR:
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3237 case M68K_EORI_SR:
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3238 dst = cycles(dst, 20);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3239 //TODO: If ANDI to SR, trap if not in supervisor mode
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3240 if (inst->src.params.immed & 0x1) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3241 dst = xor_ir(dst, 1, FLAG_C, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3242 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3243 if (inst->src.params.immed & 0x2) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3244 dst = xor_ir(dst, 1, FLAG_V, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3245 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3246 if (inst->src.params.immed & 0x4) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3247 dst = xor_ir(dst, 1, FLAG_Z, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3248 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3249 if (inst->src.params.immed & 0x8) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3250 dst = xor_ir(dst, 1, FLAG_N, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3251 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3252 if (inst->src.params.immed & 0x10) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3253 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3254 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3255 if (inst->op == M68K_ORI_SR) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3256 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
321 146c87616b05 Don't update interrupt mask on non-interrupt exceptions Mike Pavone <pavone@retrodev.com> parents: 319 diff changeset	3257 //dst = call(dst, (uint8_t *)debug_print_sr);
171 f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3258 if (inst->src.params.immed & 0x700) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3259 dst = call(dst, (uint8_t *)do_sync);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3260 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3261 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3262 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3263 case M68K_EXG:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3264 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3265 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3266 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3267 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3268 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3269 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3270 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3271 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3272 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3273 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3274 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3275 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3276 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3277 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3278 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3279 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3280 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3281 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3282 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3283 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3284 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3285 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3286 case M68K_ILLEGAL:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3287 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3288 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3289 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3290 break;
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3291 case M68K_MOVE_FROM_SR:
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3292 //TODO: Trap if not in system mode
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3293 dst = call(dst, (uint8_t *)get_sr);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3294 if (dst_op.mode == MODE_REG_DIRECT) {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3295 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3296 } else {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3297 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3298 }
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3299 dst = m68k_save_result(inst, dst, opts);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3300 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3301 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3302 case M68K_MOVE_SR:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3303 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3304 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3305 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3306 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3307 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3308 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3309 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3310 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3311 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3312 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3313 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3314 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3315 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3316 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3317 }
321 146c87616b05 Don't update interrupt mask on non-interrupt exceptions Mike Pavone <pavone@retrodev.com> parents: 319 diff changeset	3318 //dst = call(dst, (uint8_t *)debug_print_sr);
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3319 dst = call(dst, (uint8_t *)do_sync);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3320 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3321 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3322 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3323 if (src_op.base != SCRATCH1) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3324 if (src_op.mode == MODE_REG_DIRECT) {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3325 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3326 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3327 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3328 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3329 }
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3330 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr));
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3331 dst = cycles(dst, 12);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3332
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3333 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3334 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3335 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3336 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3337 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3338 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3339 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3340 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3341 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3342 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3343 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3344 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3345 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3346 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3347 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3348 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3349 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3350 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3351 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3352 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3353 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3354 break;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3355 //case M68K_MOVEP:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3356 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3357 case M68K_MULU:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3358 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3359 if (src_op.mode == MODE_IMMED) {
223 17534fb7c4f5 Fix muls with a negative immediate source. Mike Pavone <pavone@retrodev.com> parents: 221 diff changeset	3360 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : ((src_op.disp & 0x8000) ? src_op.disp \| 0xFFFF0000 : src_op.disp), SCRATCH1, SZ_D);
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3361 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3362 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3363 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3364 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3365 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3366 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3367 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3368 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3369 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3370 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3371 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3372 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3373 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3374 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3375 dst_reg = dst_op.base;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3376 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3377 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3378 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3379 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3380 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3381 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3382 dst_reg = SCRATCH2;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3383 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3384 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3385 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3386 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3387 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3388 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3389 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3390 if (dst_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3391 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3392 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3393 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3394 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3395 dst = cmp_ir(dst, 0, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3396 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3397 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3398 break;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3399 //case M68K_NBCD:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3400 case M68K_NEG:
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3401 dst = cycles(dst, BUS);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3402 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3403 dst = neg_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3404 } else {
165 62b152811bae Fix certain address modes with lea when the destination is not a native register Mike Pavone <pavone@retrodev.com> parents: 162 diff changeset	3405 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3406 }
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3407 dst = setcc_r(dst, CC_C, FLAG_C);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3408 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3409 dst = setcc_r(dst, CC_S, FLAG_N);
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3410 dst = setcc_r(dst, CC_O, FLAG_V);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3411 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3412 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3413 break;
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3414 case M68K_NEGX:
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3415 dst = cycles(dst, BUS);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3416 if (dst_op.mode == MODE_REG_DIRECT) {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3417 if (dst_op.base == SCRATCH1) {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3418 dst = push_r(dst, SCRATCH2);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3419 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3420 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3421 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3422 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3423 dst = pop_r(dst, SCRATCH2);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3424 } else {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3425 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3426 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3427 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3428 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3429 }
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3430 } else {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3431 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3432 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3433 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3434 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3435 }
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3436 dst = setcc_r(dst, CC_C, FLAG_C);
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3437 dst = jcc(dst, CC_Z, dst+4);
922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3438 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3439 dst = setcc_r(dst, CC_S, FLAG_N);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3440 dst = setcc_r(dst, CC_O, FLAG_V);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3441 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3442 dst = m68k_save_result(inst, dst, opts);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3443 break;
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3444 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3445 case M68K_NOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3446 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3447 break;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3448 case M68K_NOT:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3449 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3450 dst = not_r(dst, dst_op.base, inst->extra.size);
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3451 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3452 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3453 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3454 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3455 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3456
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3457 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3458 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3459 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3460 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3461 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3462 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3463 case M68K_OR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3464 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3465 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3466 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3467 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3468 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3469 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3470 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3471 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3472 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3473 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3474 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3475 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3476 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3477 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3478 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3479 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3480 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3481 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3482 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3483 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3484 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3485 break;
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3486 case M68K_ORI_CCR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3487 case M68K_ORI_SR:
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3488 dst = cycles(dst, 20);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3489 //TODO: If ANDI to SR, trap if not in supervisor mode
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3490 if (inst->src.params.immed & 0x1) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3491 dst = mov_ir(dst, 1, FLAG_C, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3492 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3493 if (inst->src.params.immed & 0x2) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3494 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3495 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3496 if (inst->src.params.immed & 0x4) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3497 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3498 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3499 if (inst->src.params.immed & 0x8) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3500 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3501 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3502 if (inst->src.params.immed & 0x10) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3503 dst = mov_irind(dst, 1, CONTEXT, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3504 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3505 if (inst->op == M68K_ORI_SR) {
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3506 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
321 146c87616b05 Don't update interrupt mask on non-interrupt exceptions Mike Pavone <pavone@retrodev.com> parents: 319 diff changeset	3507 //dst = call(dst, (uint8_t *)debug_print_sr);
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3508 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3509 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3510 }
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3511 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3512 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3513 case M68K_RESET:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3514 dst = call(dst, (uint8_t *)m68k_save_context);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3515 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3516 dst = call(dst, (uint8_t *)print_regs_exit);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3517 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3518 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3519 case M68K_ROR:
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3520 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3521 if (inst->src.addr_mode == MODE_UNUSED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3522 dst = cycles(dst, BUS);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3523 //Memory rotate
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3524 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3525 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3526 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3527 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3528 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3529 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3530 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3531 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3532 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3533 dst = m68k_save_result(inst, dst, opts);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3534 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3535 if (src_op.mode == MODE_IMMED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3536 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3537 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3538 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3539 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3540 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3541 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3542 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3543 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3544 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3545 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3546 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3547 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3548 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3549 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3550 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3551 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3552 if (src_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3553 if (src_op.base != SCRATCH1) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3554 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3555 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3556 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3557 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3558 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3559 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3560 zero_off = dst+1;
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3561 dst = jcc(dst, CC_Z, dst+2);
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3562 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3563 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3564 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3565 norm_off = dst+1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3566 dst = jcc(dst, CC_L, dst+2);
442 1a48b31f5316 Fix carry flag on rotate when the register provided rotate bit count is exactly 32 Mike Pavone <pavone@retrodev.com> parents: 440 diff changeset	3567 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3568 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3569 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3570 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3571 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3572 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3573 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3574 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3575 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3576 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3577 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3578 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3579 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3580 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3581 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3582 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3583 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3584 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3585 *norm_off = dst - (norm_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3586 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3587 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3588 dst = rol_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3589 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3590 dst = ror_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3591 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3592 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3593 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3594 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3595 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3596 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3597 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3598 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3599 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3600 end_off = dst + 1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3601 dst = jmp(dst, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3602 *zero_off = dst - (zero_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3603 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3604 *end_off = dst - (end_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3605 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3606 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3607 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3608 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3609 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3610 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3611 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3612 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3613 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3614 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3615 case M68K_ROXL:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3616 case M68K_ROXR:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3617 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3618 if (inst->src.addr_mode == MODE_UNUSED) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3619 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3620 //Memory rotate
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3621 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3622 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3623 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3624 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3625 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3626 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3627 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3628 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3629 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3630 dst = setcc_r(dst, CC_S, FLAG_N);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3631 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3632 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3633 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3634 if (src_op.mode == MODE_IMMED) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3635 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3636 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3637 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3638 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3639 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3640 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3641 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3642 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3643 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3644 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3645 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3646 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3647 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3648 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3649 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3650 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3651 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3652 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3653 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3654 if (src_op.base != SCRATCH1) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3655 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3656 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3657 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3658 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3659 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3660 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3661 zero_off = dst+1;
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3662 dst = jcc(dst, CC_Z, dst+2);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3663 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3664 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3665 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3666 norm_off = dst+1;
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3667 dst = jcc(dst, CC_L, dst+2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3668 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3669 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3670 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3671 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3672 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3673 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3674 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3675 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3676 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3677 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3678 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3679 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3680 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3681 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3682 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3683 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3684 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3685 }
225 7348057e7a8c Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest. Mike Pavone <pavone@retrodev.com> parents: 223 diff changeset	3686 dst = setcc_rind(dst, CC_C, CONTEXT);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3687 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3688 *norm_off = dst - (norm_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3689 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3690 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3691 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3692 dst = rcl_clr(dst, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3693 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3694 dst = rcr_clr(dst, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3695 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3696 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3697 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3698 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3699 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3700 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3701 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3702 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3703 dst = setcc_r(dst, CC_C, FLAG_C);
225 7348057e7a8c Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest. Mike Pavone <pavone@retrodev.com> parents: 223 diff changeset	3704 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3705 end_off = dst + 1;
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3706 dst = jmp(dst, dst+2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3707 *zero_off = dst - (zero_off+1);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3708 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3709 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3710 *end_off = dst - (end_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3711 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3712 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3713 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3714 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3715 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3716 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3717 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3718 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3719 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3720 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3721 case M68K_RTE:
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3722 //TODO: Trap if not in system mode
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3723 //Read saved SR
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3724 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	3725 dst = call(dst, opts->read_16);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3726 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3727 dst = call(dst, (uint8_t *)set_sr);
178 48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3728 //Read saved PC
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3729 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	3730 dst = call(dst, opts->read_32);
178 48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3731 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3732 //Check if we've switched to user mode and swap stack pointers if needed
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3733 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3734 end_off = dst+1;
121 f848aad2abef Fix logic for switching between USP and SSP Mike Pavone <pavone@retrodev.com> parents: 119 diff changeset	3735 dst = jcc(dst, CC_C, dst+2);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3736 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3737 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3738 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3739 *end_off = dst - (end_off+1);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3740 //Get native address, sync components, recalculate integer points and jump to returned address
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3741 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3742 dst = jmp_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3743 break;
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3744 case M68K_RTR:
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3745 //Read saved CCR
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3746 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	3747 dst = call(dst, opts->read_16);
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3748 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3749 dst = call(dst, (uint8_t *)set_ccr);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3750 //Read saved PC
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3751 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	3752 dst = call(dst, opts->read_32);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3753 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3754 //Get native address and jump to it
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3755 dst = call(dst, (uint8_t *)m68k_native_addr);
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3756 dst = jmp_r(dst, SCRATCH1);
7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3757 break;
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3758 case M68K_SBCD:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3759 if (src_op.base != SCRATCH2) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3760 if (src_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3761 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3762 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3763 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3764 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3765 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3766 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3767 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3768 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3769 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3770 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3771 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3772 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3773 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3774 dst = jcc(dst, CC_NC, dst+5);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3775 dst = sub_ir(dst, 1, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3776 dst = call(dst, (uint8_t *)bcd_sub);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3777 dst = mov_rr(dst, CH, FLAG_C, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3778 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3779 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3780 dst = jcc(dst, CC_Z, dst+4);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3781 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3782 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3783 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3784 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3785 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3786 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3787 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3788 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3789 dst = m68k_save_result(inst, dst, opts);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3790 break;
446 1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3791 case M68K_STOP: {
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3792 //TODO: Trap if not in system mode
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3793 //manual says 4 cycles, but it has to be at least 8 since it's a 2-word instruction
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3794 //possibly even 12 since that's how long MOVE to SR takes
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3795 dst = cycles(dst, BUS*2);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3796 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3797 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3798 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3799 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3800 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3801 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3802 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3803 //leave supervisor mode
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3804 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3805 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3806 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3807 }
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3808 uint8_t * loop_top = dst;
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3809 dst = call(dst, (uint8_t *)do_sync);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3810 dst = cmp_rr(dst, LIMIT, CYCLES, SZ_D);
e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3811 uint8_t * normal_cycle_up = dst + 1;
e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3812 dst = jcc(dst, CC_A, dst+2);
e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3813 dst = cycles(dst, BUS);
e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3814 uint8_t * after_cycle_up = dst + 1;
e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3815 dst = jmp(dst, dst+2);
e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3816 *normal_cycle_up = dst - (normal_cycle_up + 1);
446 1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3817 dst = mov_rr(dst, LIMIT, CYCLES, SZ_D);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3818 *after_cycle_up = dst - (after_cycle_up+1);
446 1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3819 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3820 dst = jcc(dst, CC_C, loop_top);
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3821 break;
1e828ed04a7c Implement 68K stop instruction Mike Pavone <pavone@retrodev.com> parents: 443 diff changeset	3822 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3823 case M68K_SUB:
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3824 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3825 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3826 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3827 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3828 dst = sub_rr(dst, src_op.base, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3829 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3830 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3831 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3832 } else if (src_op.mode == MODE_REG_DISPLACE8) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3833 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3834 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3835 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3836 dst = sub_ir(dst, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3837 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3838 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3839 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3840 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3841 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3842 dst = setcc_r(dst, CC_C, FLAG_C);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3843 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3844 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3845 dst = setcc_r(dst, CC_O, FLAG_V);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3846 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3847 }
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3848 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3849 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3850 case M68K_SUBX:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3851 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3852 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3853 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3854 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3855 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3856 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3857 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3858 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3859 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3860 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3861 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3862 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3863 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3864 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3865 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3866 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3867 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3868 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3869 dst = jcc(dst, CC_Z, dst+4);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3870 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3871 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3872 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3873 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3874 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3875 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3876 case M68K_SWAP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3877 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3878 if (src_op.mode == MODE_REG_DIRECT) {
129 691e4b147cea Fix swap Mike Pavone <pavone@retrodev.com> parents: 128 diff changeset	3879 dst = rol_ir(dst, 16, src_op.base, SZ_D);
443 9ac3828ea560 Fix sign flag on swap Mike Pavone <pavone@retrodev.com> parents: 442 diff changeset	3880 dst = cmp_ir(dst, 0, src_op.base, SZ_D);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3881 } else{
129 691e4b147cea Fix swap Mike Pavone <pavone@retrodev.com> parents: 128 diff changeset	3882 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D);
443 9ac3828ea560 Fix sign flag on swap Mike Pavone <pavone@retrodev.com> parents: 442 diff changeset	3883 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, SZ_D);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3884 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3885
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3886 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3887 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3888 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3889 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3890 break;
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3891 //case M68K_TAS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3892 case M68K_TRAP:
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 225 diff changeset	3893 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D);
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 182 diff changeset	3894 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
348 3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	3895 dst = jmp(dst, opts->trap);
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3896 break;
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3897 //case M68K_TRAPV:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3898 case M68K_TST:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3899 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3900 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3901 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3902 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3903 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3904 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3905 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3906 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3907 dst = setcc_r(dst, CC_S, FLAG_N);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3908 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3909 break;
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3910 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3911 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3912 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3913 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3914 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3915 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3916 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3917 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	3918 dst = call(dst, opts->read_32);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3919 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3920 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3921 } else {
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	3922 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3923 }
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	3924 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3925 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3926 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3927 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3928 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op);
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3929 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3930 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3931 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3932 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3933
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3934 uint8_t m68k_is_terminal(m68kinst * inst)
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3935 {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3936 return inst->op == M68K_RTS \|\| inst->op == M68K_RTE \|\| inst->op == M68K_RTR \|\| inst->op == M68K_JMP
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3937 \|\| inst->op == M68K_TRAP \|\| inst->op == M68K_ILLEGAL \|\| inst->op == M68K_INVALID \|\| inst->op == M68K_RESET
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3938 \|\| (inst->op == M68K_BCC && inst->extra.cond == COND_TRUE);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3939 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3940
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3941 void m68k_handle_deferred(m68k_context * context)
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3942 {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3943 x86_68k_options * opts = context->options;
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3944 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3945 if (opts->deferred) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3946 translate_m68k_stream(opts->deferred->address, context);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3947 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3948 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	3949
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3950 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3951 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3952 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3953 x86_68k_options * opts = context->options;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3954 uint8_t * dst = opts->cur_code;
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	3955 uint8_t * dst_end = opts->code_end;
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	3956 address &= 0xFFFFFF;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3957 if(get_native_address(opts->native_code_map, address)) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3958 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3959 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3960 char disbuf[1024];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3961 uint16_t encoded, next;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3962 if ((address & 0xFFFFFF) < 0x400000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3963 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3964 } else if ((address & 0xFFFFFF) > 0xE00000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3965 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3966 } else {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3967 printf("attempt to translate non-memory address: %X\n", address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3968 exit(1);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3969 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3970 do {
197 7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 196 diff changeset	3971 if (opts->address_log) {
7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 196 diff changeset	3972 fprintf(opts->address_log, "%X\n", address);
7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 196 diff changeset	3973 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3974 do {
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3975 if (dst_end-dst < MAX_NATIVE_SIZE) {
102 bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3976 if (dst_end-dst < 5) {
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3977 puts("out of code memory, not enough space for jmp to next chunk");
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3978 exit(1);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3979 }
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3980 size_t size = 1024*1024;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3981 opts->cur_code = alloc_code(&size);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3982 opts->code_end = opts->cur_code + size;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3983 jmp(dst, opts->cur_code);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3984 dst = opts->cur_code;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3985 dst_end = opts->code_end;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3986 }
159 c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3987 if (address >= 0x400000 && address < 0xE00000) {
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3988 dst = xor_rr(dst, RDI, RDI, SZ_D);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3989 dst = call(dst, (uint8_t *)exit);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3990 break;
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3991 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3992 uint8_t * existing = get_native_address(opts->native_code_map, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3993 if (existing) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3994 dst = jmp(dst, existing);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3995 break;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3996 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3997 next = m68k_decode(encoded, &instbuf, address);
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	3998 if (instbuf.op == M68K_INVALID) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	3999 instbuf.src.params.immed = *encoded;
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	4000 }
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4001 uint16_t m68k_size = (next-encoded)*2;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4002 address += m68k_size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4003 encoded = next;
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	4004 //m68k_disasm(&instbuf, disbuf);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	4005 //printf("%X: %s\n", instbuf.address, disbuf);
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4006 uint8_t * after = translate_m68k(dst, &instbuf, opts);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4007 map_native_address(context, instbuf.address, dst, m68k_size, after-dst);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4008 dst = after;
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4009 } while(!m68k_is_terminal(&instbuf));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 228 diff changeset	4010 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4011 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4012 address = opts->deferred->address;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4013 if ((address & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4014 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4015 } else if ((address & 0xFFFFFF) > 0xE00000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4016 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4017 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4018 printf("attempt to translate non-memory address: %X\n", address);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4019 exit(1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	4020 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4021 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4022 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4023 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4024 } while(encoded != NULL);
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4025 opts->cur_code = dst;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4026 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4027 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4028
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4029 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address)
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4030 {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4031 address &= 0xFFFFFF;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4032 uint8_t * ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4033 if (!ret) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4034 translate_m68k_stream(address, context);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4035 ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4036 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4037 return ret;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4038 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4039
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4040 void * m68k_retranslate_inst(uint32_t address, m68k_context * context)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4041 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4042 x86_68k_options * opts = context->options;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4043 uint8_t orig_size = get_native_inst_size(opts, address);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4044 uint8_t * orig_start = get_native_address(context->native_code_map, address);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4045 uint32_t orig = address;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4046 address &= 0xFFFF;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4047 uint8_t * dst = opts->cur_code;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4048 uint8_t * dst_end = opts->code_end;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4049 uint16_t after, inst = context->mem_pointers[1] + address/2;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4050 m68kinst instbuf;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4051 after = m68k_decode(inst, &instbuf, orig);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4052 if (orig_size != MAX_NATIVE_SIZE) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4053 if (dst_end - dst < 128) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4054 size_t size = 1024*1024;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4055 dst = alloc_code(&size);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4056 opts->code_end = dst_end = dst + size;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4057 opts->cur_code = dst;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4058 }
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4059 deferred_addr * orig_deferred = opts->deferred;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4060 uint8_t * native_end = translate_m68k(dst, &instbuf, opts);
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4061 uint8_t is_terminal = m68k_is_terminal(&instbuf);
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4062 if ((native_end - dst) <= orig_size) {
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4063 uint8_t * native_next;
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4064 if (!is_terminal) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4065 native_next = get_native_address(context->native_code_map, orig + (after-inst)*2);
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4066 }
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4067 if (is_terminal \|\| (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5))) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4068 remove_deferred_until(&opts->deferred, orig_deferred);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4069 native_end = translate_m68k(orig_start, &instbuf, opts);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4070 if (!is_terminal) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4071 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4072 while (native_end < orig_start + orig_size) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4073 *(native_end++) = 0x90; //NOP
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4074 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4075 } else {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4076 jmp(native_end, native_next);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4077 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4078 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4079 m68k_handle_deferred(context);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4080 return orig_start;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4081 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4082 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4083
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4084 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4085 opts->cur_code = dst+MAX_NATIVE_SIZE;
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4086 jmp(orig_start, dst);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4087 if (!m68k_is_terminal(&instbuf)) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4088 jmp(native_end, get_native_address_trans(context, orig + (after-inst)*2));
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4089 }
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4090 m68k_handle_deferred(context);
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4091 return dst;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4092 } else {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4093 dst = translate_m68k(orig_start, &instbuf, opts);
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4094 if (!m68k_is_terminal(&instbuf)) {
0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4095 dst = jmp(dst, get_native_address_trans(context, orig + (after-inst)*2));
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4096 }
319 0bcab0475a7f Port instruction retranslation improvements from Z80 core to M68K core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	4097 m68k_handle_deferred(context);
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4098 return orig_start;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4099 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4100 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4101
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4102 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4103 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4104 uint32_t inst_start = get_instruction_start(context->native_code_map, address \| 0xFF0000);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4105 if (inst_start) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4106 uint8_t * dst = get_native_address(context->native_code_map, inst_start);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4107 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4108 dst = jmp(dst, (uint8_t *)m68k_retrans_stub);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4109 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4110 return context;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4111 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4112
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4113 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler)
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4114 {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4115 static uint8_t * bp_stub = NULL;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4116 uint8_t * native = get_native_address_trans(context, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4117 uint8_t * start_native = native;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4118 native = mov_ir(native, address, SCRATCH1, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4119 if (!bp_stub) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4120 x86_68k_options * opts = context->options;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4121 uint8_t * dst = opts->cur_code;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4122 uint8_t * dst_end = opts->code_end;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4123 if (dst_end - dst < 128) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4124 size_t size = 1024*1024;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4125 dst = alloc_code(&size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4126 opts->code_end = dst_end = dst + size;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4127 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4128 bp_stub = dst;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4129 native = call(native, bp_stub);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4130
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4131 //Calculate length of prologue
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4132 dst = check_cycles_int(dst, address, opts);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4133 int check_int_size = dst-bp_stub;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4134 dst = bp_stub;
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4135
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4136 //Save context and call breakpoint handler
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4137 dst = call(dst, (uint8_t *)m68k_save_context);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4138 dst = push_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4139 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4140 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4141 dst = call(dst, bp_handler);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4142 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4143 //Restore context
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4144 dst = call(dst, (uint8_t *)m68k_load_context);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4145 dst = pop_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4146 //do prologue stuff
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4147 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4148 uint8_t * jmp_off = dst+1;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4149 dst = jcc(dst, CC_NC, dst + 7);
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4150 dst = call(dst, opts->handle_cycle_limit_int);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4151 *jmp_off = dst - (jmp_off+1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4152 //jump back to body of translated instruction
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4153 dst = pop_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4154 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4155 dst = jmp_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4156 opts->cur_code = dst;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4157 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4158 native = call(native, bp_stub);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4159 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4160 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4161
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4162 void remove_breakpoint(m68k_context * context, uint32_t address)
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4163 {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4164 uint8_t * native = get_native_address(context->native_code_map, address);
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4165 check_cycles_int(native, address, context->options);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4166 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4167
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4168 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4169 {
424 7e8e179116af Add support for loading GST format savestates Mike Pavone <pavone@retrodev.com> parents: 423 diff changeset	4170 uint8_t * addr = get_native_address_trans(context, address);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4171 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4172 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4173
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4174 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4175 {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4176 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4177 context->aregs[7] = context->mem_pointers[0][0] << 16 \| context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4178 uint32_t address = context->mem_pointers[0][2] << 16 \| context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4179 start_68k_context(context, address);
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4180 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4181
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4182 typedef enum {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4183 READ_16,
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4184 READ_8,
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4185 WRITE_16,
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4186 WRITE_8
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4187 } ftype;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4188
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4189 uint8_t * gen_mem_fun(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type)
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4190 {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4191 uint8_t * dst = opts->cur_code;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4192 uint8_t * start = dst;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4193 dst = check_cycles(dst);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4194 dst = cycles(dst, BUS);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4195 dst = and_ir(dst, 0xFFFFFF, SCRATCH1, SZ_D);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4196 uint8_t lb_jcc = NULL, ub_jcc = NULL;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4197 uint8_t is_write = fun_type == WRITE_16 \|\| fun_type == WRITE_8;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4198 uint8_t adr_reg = is_write ? SCRATCH2 : SCRATCH1;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4199 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4200 uint8_t size = (fun_type == READ_16 \|\| fun_type == WRITE_16) ? SZ_W : SZ_B;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4201 for (uint32_t chunk = 0; chunk < num_chunks; chunk++)
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4202 {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4203 if (memmap[chunk].start > 0) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4204 dst = cmp_ir(dst, memmap[chunk].start, adr_reg, SZ_D);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4205 lb_jcc = dst + 1;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4206 dst = jcc(dst, CC_C, dst+2);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4207 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4208 if (memmap[chunk].end < 0x1000000) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4209 dst = cmp_ir(dst, memmap[chunk].end, adr_reg, SZ_D);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4210 ub_jcc = dst + 1;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4211 dst = jcc(dst, CC_NC, dst+2);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4212 }
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4213
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4214 if (memmap[chunk].mask != 0xFFFFFF) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4215 dst = and_ir(dst, memmap[chunk].mask, adr_reg, SZ_D);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4216 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4217 void * cfun;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4218 switch (fun_type)
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4219 {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4220 case READ_16:
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4221 cfun = memmap[chunk].read_16;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4222 break;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4223 case READ_8:
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4224 cfun = memmap[chunk].read_8;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4225 break;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4226 case WRITE_16:
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4227 cfun = memmap[chunk].write_16;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4228 break;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4229 case WRITE_8:
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4230 cfun = memmap[chunk].write_8;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4231 break;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4232 default:
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4233 cfun = NULL;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4234 }
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4235 if(memmap[chunk].buffer && memmap[chunk].flags & access_flag) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4236 if (memmap[chunk].flags & MMAP_PTR_IDX) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4237 if (memmap[chunk].flags & MMAP_FUNC_NULL) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4238 dst = cmp_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void) memmap[chunk].ptr_index, SZ_Q);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4239 uint8_t * not_null = dst+1;
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4240 dst = jcc(dst, CC_NZ, dst+2);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4241 dst = call(dst, (uint8_t *)m68k_save_context);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4242 if (is_write) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4243 //SCRATCH2 is RDI, so no need to move it there
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4244 dst = mov_rr(dst, SCRATCH1, RDX, size);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4245 } else {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4246 dst = push_r(dst, CONTEXT);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4247 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4248 }
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4249 dst = test_ir(dst, 8, RSP, SZ_D);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4250 uint8_t *adjust_rsp = dst+1;
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4251 dst = jcc(dst, CC_NZ, dst+2);
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4252 dst = call(dst, cfun);
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4253 uint8_t *no_adjust = dst+1;
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4254 dst = jmp(dst, dst+2);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4255 *adjust_rsp = dst - (adjust_rsp + 1);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4256 dst = sub_ir(dst, 8, RSP, SZ_Q);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4257 dst = call(dst, cfun);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4258 dst = add_ir(dst, 8, RSP, SZ_Q);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4259 *no_adjust = dst - (no_adjust + 1);
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4260 if (is_write) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4261 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4262 } else {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4263 dst = pop_r(dst, CONTEXT);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4264 dst = mov_rr(dst, RAX, SCRATCH1, size);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4265 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4266 dst = jmp(dst, (uint8_t *)m68k_load_context);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4267
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4268 *not_null = dst - (not_null + 1);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4269 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4270 if (size == SZ_B) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4271 dst = xor_ir(dst, 1, adr_reg, SZ_D);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4272 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4273 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void) memmap[chunk].ptr_index, adr_reg, SZ_Q);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4274 if (is_write) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4275 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, size);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4276
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4277 } else {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4278 dst = mov_rindr(dst, SCRATCH1, SCRATCH1, size);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4279 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4280 } else {
352 8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4281 uint8_t tmp_size = size;
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4282 if (size == SZ_B) {
352 8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4283 if ((memmap[chunk].flags & MMAP_ONLY_ODD) \|\| (memmap[chunk].flags & MMAP_ONLY_EVEN)) {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4284 dst = bt_ir(dst, 0, adr_reg, SZ_D);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4285 uint8_t * good_addr = dst + 1;
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4286 dst = jcc(dst, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, dst+2);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4287 if (!is_write) {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4288 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4289 }
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4290 dst = retn(dst);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4291 *good_addr = dst - (good_addr + 1);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4292 dst = shr_ir(dst, 1, adr_reg, SZ_D);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4293 } else {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4294 dst = xor_ir(dst, 1, adr_reg, SZ_D);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4295 }
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4296 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) \|\| (memmap[chunk].flags & MMAP_ONLY_EVEN)) {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4297 tmp_size = SZ_B;
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4298 dst = shr_ir(dst, 1, adr_reg, SZ_D);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4299 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4300 dst = shr_ir(dst, 8, SCRATCH1, SZ_W);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4301 }
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4302 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4303 if ((int64_t)memmap[chunk].buffer <= 0x7FFFFFFF && (int64_t)memmap[chunk].buffer >= -2147483648) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4304 if (is_write) {
352 8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4305 dst = mov_rrdisp32(dst, SCRATCH1, SCRATCH2, (int64_t)memmap[chunk].buffer, tmp_size);
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4306 } else {
352 8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4307 dst = mov_rdisp32r(dst, SCRATCH1, (int64_t)memmap[chunk].buffer, SCRATCH1, tmp_size);
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4308 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4309 } else {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4310 if (is_write) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4311 dst = push_r(dst, SCRATCH1);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4312 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH1, SZ_Q);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4313 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_Q);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4314 dst = pop_r(dst, SCRATCH1);
352 8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4315 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, tmp_size);
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4316 } else {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4317 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH2, SZ_Q);
352 8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4318 dst = mov_rindexr(dst, SCRATCH2, SCRATCH1, 1, SCRATCH1, tmp_size);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4319 }
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4320 }
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4321 if (size != tmp_size && !is_write) {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4322 if (memmap[chunk].flags & MMAP_ONLY_EVEN) {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4323 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4324 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B);
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4325 } else {
8c3409585130 Finish SRAM support for games without a SEGA mapper Mike Pavone <pavone@retrodev.com> parents: 351 diff changeset	4326 dst = or_ir(dst, 0xFF00, SCRATCH1, SZ_W);
351 2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4327 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4328 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4329 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4330 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4331 dst = mov_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4332 dst = shr_ir(dst, 11, SCRATCH1, SZ_D);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4333 dst = bt_rrdisp32(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, ram_code_flags), SZ_D);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4334 uint8_t * not_code = dst+1;
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4335 dst = jcc(dst, CC_NC, dst+2);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4336 dst = call(dst, (uint8_t *)m68k_save_context);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4337 dst = call(dst, (uint8_t *)m68k_handle_code_write);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4338 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4339 dst = call(dst, (uint8_t *)m68k_load_context);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4340 *not_code = dst - (not_code+1);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4341 }
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4342 dst = retn(dst);
2f264d2a60c2 Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper. Mike Pavone <pavone@retrodev.com> parents: 350 diff changeset	4343 } else if (cfun) {
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4344 dst = call(dst, (uint8_t *)m68k_save_context);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4345 if (is_write) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4346 //SCRATCH2 is RDI, so no need to move it there
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4347 dst = mov_rr(dst, SCRATCH1, RDX, size);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4348 } else {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4349 dst = push_r(dst, CONTEXT);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4350 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4351 }
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4352 dst = test_ir(dst, 8, RSP, SZ_D);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4353 uint8_t *adjust_rsp = dst+1;
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4354 dst = jcc(dst, CC_NZ, dst+2);
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4355 dst = call(dst, cfun);
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4356 uint8_t *no_adjust = dst+1;
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4357 dst = jmp(dst, dst+2);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4358 *adjust_rsp = dst - (adjust_rsp + 1);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4359 dst = sub_ir(dst, 8, RSP, SZ_Q);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4360 dst = call(dst, cfun);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4361 dst = add_ir(dst, 8, RSP, SZ_Q);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4362 *no_adjust = dst - (no_adjust+1);
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4363 if (is_write) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4364 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4365 } else {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4366 dst = pop_r(dst, CONTEXT);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4367 dst = mov_rr(dst, RAX, SCRATCH1, size);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4368 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4369 dst = jmp(dst, (uint8_t *)m68k_load_context);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4370 } else {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4371 //Not sure the best course of action here
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4372 if (!is_write) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4373 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4374 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4375 dst = retn(dst);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4376 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4377 if (lb_jcc) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4378 *lb_jcc = dst - (lb_jcc+1);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4379 lb_jcc = NULL;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4380 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4381 if (ub_jcc) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4382 *ub_jcc = dst - (ub_jcc+1);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4383 ub_jcc = NULL;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4384 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4385 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4386 if (!is_write) {
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4387 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4388 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4389 dst = retn(dst);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4390 opts->cur_code = dst;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4391 return start;
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4392 }
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4393
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4394 void init_x86_68k_opts(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4395 {
440 306986209cba Fix 68K test harness Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4396 memset(opts, 0, sizeof(*opts));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4397 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4398 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4399 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4400 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4401 opts->dregs[2] = R12;
423 8e136187c0e0 Use the registers that were freed up by the memory map function changes Mike Pavone <pavone@retrodev.com> parents: 352 diff changeset	4402 opts->dregs[3] = R8;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4403 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4404 opts->aregs[1] = R14;
423 8e136187c0e0 Use the registers that were freed up by the memory map function changes Mike Pavone <pavone@retrodev.com> parents: 352 diff changeset	4405 opts->aregs[2] = R9;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4406 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4407 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4408 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4409 opts->deferred = NULL;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4410 size_t size = 1024 * 1024;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4411 opts->cur_code = alloc_code(&size);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4412 opts->code_end = opts->cur_code + size;
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4413 opts->ram_inst_sizes = malloc(sizeof(uint8_t ) 64);
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4414 memset(opts->ram_inst_sizes, 0, sizeof(uint8_t ) 64);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4415
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4416 opts->read_16 = gen_mem_fun(opts, memmap, num_chunks, READ_16);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4417 opts->read_8 = gen_mem_fun(opts, memmap, num_chunks, READ_8);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4418 opts->write_16 = gen_mem_fun(opts, memmap, num_chunks, WRITE_16);
91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4419 opts->write_8 = gen_mem_fun(opts, memmap, num_chunks, WRITE_8);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4420
350 91aa2aa05e68 Refactor code gen for read/write functions Mike Pavone <pavone@retrodev.com> parents: 348 diff changeset	4421 uint8_t * dst = opts->cur_code;
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4422
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4423 opts->read_32 = dst;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4424 dst = push_r(dst, SCRATCH1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4425 dst = call(dst, opts->read_16);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4426 dst = mov_rr(dst, SCRATCH1, SCRATCH2, SZ_W);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4427 dst = pop_r(dst, SCRATCH1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4428 dst = push_r(dst, SCRATCH2);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4429 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4430 dst = call(dst, opts->read_16);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4431 dst = pop_r(dst, SCRATCH2);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4432 dst = movzx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4433 dst = shl_ir(dst, 16, SCRATCH2, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4434 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4435 dst = retn(dst);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4436
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4437 opts->write_32_lowfirst = dst;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4438 dst = push_r(dst, SCRATCH2);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4439 dst = push_r(dst, SCRATCH1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4440 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4441 dst = call(dst, opts->write_16);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4442 dst = pop_r(dst, SCRATCH1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4443 dst = pop_r(dst, SCRATCH2);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4444 dst = shr_ir(dst, 16, SCRATCH1, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4445 dst = jmp(dst, opts->write_16);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4446
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4447 opts->write_32_highfirst = dst;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4448 dst = push_r(dst, SCRATCH1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4449 dst = push_r(dst, SCRATCH2);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4450 dst = shr_ir(dst, 16, SCRATCH1, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4451 dst = call(dst, opts->write_16);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4452 dst = pop_r(dst, SCRATCH2);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4453 dst = pop_r(dst, SCRATCH1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4454 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4455 dst = jmp(dst, opts->write_16);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4456
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4457 opts->handle_cycle_limit_int = dst;
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4458 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4459 uint8_t * do_int = dst+1;
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4460 dst = jcc(dst, CC_NC, dst+2);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4461 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4462 uint8_t * skip_sync = dst+1;
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4463 dst = jcc(dst, CC_C, dst+2);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4464 dst = call(dst, (uint8_t *)m68k_save_context);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4465 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4466 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D);
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4467 dst = test_ir(dst, 8, RSP, SZ_D);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4468 uint8_t *adjust_rsp = dst+1;
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4469 dst = jcc(dst, CC_NZ, dst+2);
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4470 dst = call(dst, (uint8_t *)sync_components);
485 b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4471 uint8_t *no_adjust = dst+1;
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4472 dst = jmp(dst, dst+2);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4473 *adjust_rsp = dst - (adjust_rsp + 1);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4474 dst = sub_ir(dst, 8, RSP, SZ_Q);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4475 dst = call(dst, (uint8_t *)sync_components);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4476 dst = add_ir(dst, 8, RSP, SZ_Q);
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	4477 *no_adjust = dst - (no_adjust+1);
347 b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4478 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4479 dst = jmp(dst, (uint8_t *)m68k_load_context);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4480 *skip_sync = dst - (skip_sync+1);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4481 dst = retn(dst);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4482 *do_int = dst - (do_int+1);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4483 //set target cycle to sync cycle
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4484 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), LIMIT, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4485 //swap USP and SSP if not already in supervisor mode
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4486 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4487 uint8_t *already_supervisor = dst+1;
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4488 dst = jcc(dst, CC_C, dst+2);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4489 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4490 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4491 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4492 *already_supervisor = dst - (already_supervisor+1);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4493 //save PC
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4494 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4495 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4496 dst = call(dst, opts->write_32_lowfirst);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4497 //save status register
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4498 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4499 dst = call(dst, (uint8_t *)get_sr);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4500 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4501 dst = call(dst, opts->write_16);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4502 //update status register
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4503 dst = and_irdisp8(dst, 0xF8, CONTEXT, offsetof(m68k_context, status), SZ_B);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4504 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_B);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4505 dst = or_ir(dst, 0x20, SCRATCH1, SZ_B);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4506 dst = or_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, status), SZ_B);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4507 //calculate interrupt vector address
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4508 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4509 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, int_ack), SZ_W);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4510 dst = shl_ir(dst, 2, SCRATCH1, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4511 dst = add_ir(dst, 0x60, SCRATCH1, SZ_D);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4512 dst = call(dst, opts->read_32);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4513 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4514 dst = cycles(dst, 24);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4515 //discard function return address
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4516 dst = pop_r(dst, SCRATCH2);
b24556b45d1e Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	4517 dst = jmp_r(dst, SCRATCH1);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4518
348 3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4519 opts->trap = dst;
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4520 dst = push_r(dst, SCRATCH2);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4521 //swap USP and SSP if not already in supervisor mode
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4522 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4523 already_supervisor = dst+1;
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4524 dst = jcc(dst, CC_C, dst+2);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4525 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4526 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4527 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4528 *already_supervisor = dst - (already_supervisor+1);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4529 //save PC
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4530 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4531 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4532 dst = call(dst, opts->write_32_lowfirst);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4533 //save status register
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4534 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4535 dst = call(dst, (uint8_t *)get_sr);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4536 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4537 dst = call(dst, opts->write_16);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4538 //set supervisor bit
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4539 dst = or_irdisp8(dst, 0x20, CONTEXT, offsetof(m68k_context, status), SZ_B);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4540 //calculate vector address
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4541 dst = pop_r(dst, SCRATCH1);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4542 dst = shl_ir(dst, 2, SCRATCH1, SZ_D);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4543 dst = call(dst, opts->read_32);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4544 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4545 dst = cycles(dst, 18);
3923dbc2dcc4 m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S Mike Pavone <pavone@retrodev.com> parents: 347 diff changeset	4546 dst = jmp_r(dst, SCRATCH1);
447 e730fc040169 Fix performance regression from stop instruction work Mike Pavone <pavone@retrodev.com> parents: 446 diff changeset	4547
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 324 diff changeset	4548 opts->cur_code = dst;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4549 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4550
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4551 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4552 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4553 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4554 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4555 context->options = opts;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	4556 context->int_cycle = 0xFFFFFFFF;
167 f6c7fea1ecf7 Initialize status register to proper value on startup Mike Pavone <pavone@retrodev.com> parents: 165 diff changeset	4557 context->status = 0x27;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4558 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4559

Mercurial > repos > blastem

annotate m68k_to_x86.c @ 491:193ca779988e opengl