repos/blastem: m68k_to_x86.c annotate

annotate m68k_to_x86.c @ 213:4d4559b04c59

Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.

author	Mike Pavone <pavone@retrodev.com>
date	Tue, 16 Apr 2013 22:29:00 -0700
parents	464513050c85
children	0b5ec22dcda2

rev	line source
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "m68k_to_x86.h"
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	3 #include "68kinst.h"
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4 #include "mem.h"
211 464513050c85 Small bit of cleanup Mike Pavone <pavone@retrodev.com> parents: 210 diff changeset	5 #include "x86_backend.h"
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	6 #include <stdio.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	7 #include <stddef.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	8 #include <stdlib.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	9 #include <string.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	10
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define BUS 4
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	12 #define PREDEC_PENALTY 2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 #define CYCLES RAX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define LIMIT RBP
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	15 #define SCRATCH1 RCX
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	16 #define SCRATCH2 RDI
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define CONTEXT RSI
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define FLAG_N RBX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define FLAG_V BH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 #define FLAG_Z RDX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 #define FLAG_C DH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	24 char disasm_buf[1024];
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	25
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	26 void handle_cycle_limit_int();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	27 void m68k_read_word_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	28 void m68k_read_long_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	29 void m68k_read_byte_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	30 void m68k_write_word();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	31 void m68k_write_long_lowfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	32 void m68k_write_long_highfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	33 void m68k_write_byte();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	34 void m68k_save_context();
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	35 void m68k_load_context();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	36 void m68k_modified_ret_addr();
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	37 void m68k_native_addr();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	38 void m68k_native_addr_and_sync();
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	39 void m68k_trap();
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	40 void m68k_invalid();
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	41 void m68k_retrans_stub();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	42 void set_sr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	43 void set_ccr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	44 void get_sr();
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	45 void do_sync();
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	46 void bcd_add();
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	47 void bcd_sub();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	48 void m68k_start_context(uint8_t * addr, m68k_context * context);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	49
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 uint8_t * cycles(uint8_t * dst, uint32_t num)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	52 dst = add_ir(dst, num, CYCLES, SZ_D);
118 d9ff99ef5533 cycles should return dst Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	53 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	55
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	56 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	57 {
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	58 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	59 uint8_t * jmp_off = dst+1;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	60 dst = jcc(dst, CC_NC, dst + 7);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	61 dst = mov_ir(dst, address, SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	62 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	63 *jmp_off = dst - (jmp_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	64 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	65 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	66
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 if (op->addr_mode == MODE_REG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 return opts->dregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 if (op->addr_mode == MODE_AREG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 return opts->aregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	75 return -1;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	77
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	78 //must be called with an m68k_op_info that uses a register
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	79 size_t reg_offset(m68k_op_info *op)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	80 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	81 if (op->addr_mode == MODE_REG) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	82 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	83 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	84 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	85 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	86
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	87 void print_regs_exit(m68k_context * context)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	89 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	90 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	91 printf("d%d: %X\n", i, context->dregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	92 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	93 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	94 printf("a%d: %X\n", i, context->aregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	95 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	96 exit(0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	97 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	98
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	99 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	100 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	101 int8_t reg = native_reg(&(inst->src), opts);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	102 uint8_t sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	103 int32_t dec_amount,inc_amount;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 if (reg >= 0) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	105 ea->mode = MODE_REG_DIRECT;
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	106 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	107 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	108 ea->base = SCRATCH1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	109 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	110 ea->base = reg;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	111 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	112 return out;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	114 switch (inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	115 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	116 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	117 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	118 //We only get one memory parameter, so if the dst operand is a register in memory,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	119 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	120 reg = native_reg(&(inst->dst), opts);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	121 if (reg >= 0 \|\| inst->dst.addr_mode == MODE_UNUSED \|\| !(inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	122 \|\| inst->op == M68K_EXG) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	123
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	124 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	125 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	126 ea->disp = reg_offset(&(inst->src));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	127 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	128 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	129 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	130 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	131 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	132 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	133 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	134 ea->base = SCRATCH1;
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	135 //we're explicitly handling the areg dest here, so we exit immediately
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	136 return out;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	137 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	138 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	139 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	140 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	141 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	142 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
158 a2ab895d9708 Fix predec address mode when used as source Mike Pavone <pavone@retrodev.com> parents: 157 diff changeset	143 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	144 } else {
158 a2ab895d9708 Fix predec address mode when used as source Mike Pavone <pavone@retrodev.com> parents: 157 diff changeset	145 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	146 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	147 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	148 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	149 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	150 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	151 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	152 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	153 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	154 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	155 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	156 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	157 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	158 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	159 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	160 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	161 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	162 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	163 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	164 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	165 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	166
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	167 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 182 diff changeset	168 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	169 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	170 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	171 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	172 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	173 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	174 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	175 ea->mode = MODE_REG_DIRECT;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	176 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	177 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	178 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	179 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	180 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	181 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	182 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	183 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	184 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	185 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	186 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	187 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	188 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	189 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	190 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	191 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	192 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	193 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	194 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	195 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	196 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	197 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	198 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	199 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	200 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	201 case MODE_AREG_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	202 out = cycles(out, 6);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	203 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	204 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	205 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	206 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	207 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	208 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	209 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	210 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	211 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	212 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	213 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	214 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	215 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	216 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	217 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	218 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	219 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	220 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	221 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	222 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	223 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	224 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	225 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	226 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	227 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	228 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	229 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	230 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	231 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	232 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	233 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	234 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	235 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	236 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	237 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	238 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	239 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	240 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	241 }
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	242 switch (inst->extra.size)
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	243 {
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	244 case OPSIZE_BYTE:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	245 out = call(out, (char *)m68k_read_byte_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	246 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	247 case OPSIZE_WORD:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	248 out = call(out, (char *)m68k_read_word_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	249 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	250 case OPSIZE_LONG:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	251 out = call(out, (char *)m68k_read_long_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	252 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	253 }
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	254 ea->mode = MODE_REG_DIRECT;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	255 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	256 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	257 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	258 out = cycles(out, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	259 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	260 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	261 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	262 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	263 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	264 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	265 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	266 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	267 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	268 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	269 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	270 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	271 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	272 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	273 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	274 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	275 case MODE_PC_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	276 out = cycles(out, 6);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	277 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	278 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	279 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	280 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	281 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	282 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	283 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	284 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	285 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	286 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	287 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	288 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	289 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	290 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	291 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	292 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	293 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	294 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	295 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	296 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	297 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	298 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	299 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	300 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	301 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	302 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	303 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	304 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	305 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	306 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	307 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	308 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	309 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	310 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	311 }
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	312 switch (inst->extra.size)
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	313 {
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	314 case OPSIZE_BYTE:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	315 out = call(out, (char *)m68k_read_byte_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	316 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	317 case OPSIZE_WORD:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	318 out = call(out, (char *)m68k_read_word_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	319 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	320 case OPSIZE_LONG:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	321 out = call(out, (char *)m68k_read_long_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	322 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	323 }
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	324 ea->mode = MODE_REG_DIRECT;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	325 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	326 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	327 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	328 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	329 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	330 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	331 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	332 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	333 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	334 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	335 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	336 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	337 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	338 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	339 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	340 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	341 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	342 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	343 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	344 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	345 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	346 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	347 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	348 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	349 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	350 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	351 case MODE_IMMEDIATE_WORD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	352 if (inst->variant != VAR_QUICK) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	353 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	354 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	355 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	356 ea->disp = inst->src.params.immed;
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	357 return out;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	358 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	359 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	360 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	361 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	362 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	363 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	364 if (ea->mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	365 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	366 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	367 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	368 ea->mode = MODE_REG_DIRECT;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	369 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	370 ea->base = SCRATCH1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	371 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	372 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	373 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	374
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	375 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	376 {
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	377 int8_t reg = native_reg(&(inst->dst), opts), sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	378 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	379 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	380 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	381 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	382 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	383 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	384 switch (inst->dst.addr_mode)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	385 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	386 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 case MODE_AREG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	388 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	389 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	390 ea->disp = reg_offset(&(inst->dst));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	391 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	392 case MODE_AREG_PREDEC:
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	393 if (inst->src.addr_mode == MODE_AREG_PREDEC) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	394 out = push_r(out, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	395 }
182 924af8b2f7a0 Fix -(a7) dest when size is byte Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	396 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	397 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	398 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	399 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	400 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	401 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	402 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	403 case MODE_AREG_POSTINC:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	404 if (fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	405 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	406 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	407 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	408 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	409 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	410 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	411 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	412 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	413 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	414 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	415 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	416 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	417 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	418 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	419 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	420 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	421 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	422 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	423 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	424 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	425 if (inst->src.addr_mode == MODE_AREG_PREDEC) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	426 //restore src operand to SCRATCH2
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	427 out =pop_r(out, SCRATCH2);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	428 } else {
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	429 //save reg value in SCRATCH2 so we can use it to save the result in memory later
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	430 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	431 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	432 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	433 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	434 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	435 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	436
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	437 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	438 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	439 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	440 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	441 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	442 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	443 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	444 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	445 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	446 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	447 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	448 case MODE_AREG_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	449 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	450 reg = fake_read ? SCRATCH2 : SCRATCH1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	451 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	452 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	453 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	454 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	455 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	456 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	457 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	458 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	459 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	460 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	461 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	462 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	463 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	464 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	465 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	466 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	467 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	468 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	469 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	470 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	471 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	472 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	473 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	474 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	475 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	476 case MODE_AREG_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	477 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	478 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	479 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	480 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	481 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	482 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	483 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	484 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	485 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	486 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	487 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	488 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	489 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	490 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	491 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	492 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	493 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	494 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	495 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	496 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	497 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	498 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	499 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	500 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	501 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	502 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	503 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	504 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	505 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	506 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	507 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	508 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	509 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	510 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	511 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	512 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	513 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	514 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	515 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	516 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	517 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	518 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	519 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	520 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	521 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	522 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	523 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	524 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	525 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	526 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	527 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	528 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	529 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	530 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	531 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	532 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	533 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	534 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	535 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	536 ea->base = SCRATCH1;
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	537 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	538 case MODE_PC_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	539 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	540 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	541 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	542 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	543 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	544 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	545 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	546 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	547 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	548 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	549 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	550 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	551 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	552 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	553 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	554 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	555 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	556 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	557 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	558 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	559 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	560 case MODE_PC_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	561 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	562 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	563 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	564 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	565 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	566 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	567 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	568 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	569 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	570 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	571 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	572 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	573 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	574 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	575 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	576 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	577 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	578 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	579 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	580 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	581 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	582 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	583 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	584 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	585 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	586 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	587 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	588 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	589 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	590 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	591 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	592 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	593 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	594 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	595 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	596 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	597 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	598 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	599 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	600 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	601 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	602 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	603 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	604 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	605 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	606 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	607 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	608 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	609 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	610 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	611 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	612 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	613 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	614 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	615 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	616 ea->base = SCRATCH1;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	617 break;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	618 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	619 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	620 //Add cycles for reading address from instruction stream
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	621 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS2 : BUS) : 0));
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	622 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	623 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	624 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	625 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	626 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	627 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	628 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	629 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	630 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	631 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	632 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	633 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	634 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	635 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	636 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	637 out = pop_r(out, SCRATCH2);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	638 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	639 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	640 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	641 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	642 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	643 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	644 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	645 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	646 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	647 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	648 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	649
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	650 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	651 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	652 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	653 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	654 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	655 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	656 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	657 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	658 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	659 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	660 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	662 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	664 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	665 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	666 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	667 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	668 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	669 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	670 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	671 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	672 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	673 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	674 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	675
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	676 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	677 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	678 address &= 0xFFFFFF;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	679 address /= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	680 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	681 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	682 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	683 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	684 uint32_t offset = address % NATIVE_CHUNK_SIZE;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	685 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET \|\| native_code_map[chunk].offsets[offset] == EXTENSION_WORD) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	686 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	687 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	688 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	689 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	690
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	691 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	692 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	693 address &= 0xFFFFFF;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	694 address /= 2;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	695 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	696 if (!native_code_map[chunk].base) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	697 return 0;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	698 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	699 uint32_t offset = address % NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	700 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	701 return 0;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	702 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	703 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	704 --address;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	705 chunk = address / NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	706 offset = address % NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	707 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	708 return address*2;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	709 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	710
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	711 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	712 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	713 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	714 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	715 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	716 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	717 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	718 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	719
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	720 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	721 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	722 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	723 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	724 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	725 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	726 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	727 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	728 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	729 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	730 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	731 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	732 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	733 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	734 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	735 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	736 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	737 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	738 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	739 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	740 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	741 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	742 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	743 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	744 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	745 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	746
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	747 void map_native_address(m68k_context * context, uint32_t address, uint8_t * native_addr, uint8_t size, uint8_t native_size)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	748 {
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	749 native_map_slot * native_code_map = context->native_code_map;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	750 x86_68k_options * opts = context->options;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	751 address &= 0xFFFFFF;
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	752 if (address > 0xE00000) {
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	753 context->ram_code_flags[(address & 0xC000) >> 14] \|= 1 << ((address & 0x3800) >> 11);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	754 if (((address & 0x3FFF) + size) & 0xC000) {
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	755 context->ram_code_flags[((address+size) & 0xC000) >> 14] \|= 1 << (((address+size) & 0x3800) >> 11);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	756 }
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	757 uint32_t slot = (address & 0xFFFF)/1024;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	758 if (!opts->ram_inst_sizes[slot]) {
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	759 opts->ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	760 }
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	761 opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	762 }
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	763 address/= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	764 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	765 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	766 native_code_map[chunk].base = native_addr;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	767 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	768 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	769 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	770 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	771 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	772 for(address++,size-=2; size; address++,size-=2) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	773 chunk = address / NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	774 offset = address % NATIVE_CHUNK_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	775 if (!native_code_map[chunk].base) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	776 native_code_map[chunk].base = native_addr;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	777 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	778 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	779 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	780 native_code_map[chunk].offsets[offset] = EXTENSION_WORD;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	781 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	782 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	783
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	784 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	785 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	786 if (address < 0xE00000) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	787 return 0;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	788 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	789 uint32_t slot = (address & 0xFFFF)/1024;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	790 return opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512];
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	791 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	792
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	793 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	794 {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	795 int8_t reg, flags_reg, sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	796 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	797 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	798 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	799 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	800 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	801 reg = native_reg(&(inst->dst), opts);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	802 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	803 //update statically set flags
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	804 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	805 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	806 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	807
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	808 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	809 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	810 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	811 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	812 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	813 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	814 if(src.mode == MODE_REG_DISPLACE8) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	815 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	816 } else {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	817 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	818 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	819 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	820 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	821 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	822 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	823 uint8_t size = inst->extra.size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	824 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	825 {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	826 case MODE_AREG:
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	827 size = OPSIZE_LONG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	828 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	829 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	830 if (src.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	831 dst = mov_rr(dst, src.base, reg, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	832 } else if (src.mode == MODE_REG_DISPLACE8) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	833 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	834 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	835 dst = mov_ir(dst, src.disp, reg, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	836 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	837 } else if(src.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	838 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	839 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	840 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	841 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	842 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	843 dst = cmp_ir(dst, 0, flags_reg, size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	844 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	845 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	846 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	847 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	848 case MODE_AREG_PREDEC:
182 924af8b2f7a0 Fix -(a7) dest when size is byte Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	849 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	850 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	851 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	852 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	853 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	854 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	855 case MODE_AREG_INDIRECT:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	856 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	857 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	858 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	859 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	860 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	861 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	862 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	863 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	864 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	865 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	866 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	867 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	868 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	869 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	870 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	871 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	872 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	873 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	874 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	875 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	876 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	877 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	878 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	879 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	880 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	881 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	882 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	883 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	884 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	885 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	886 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	887 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	888 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	889 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	890 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	891 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	892 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	893 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	894 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	895 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	896 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	897 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	898 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	899 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	900 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	901 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	902 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	903 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	904 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	905 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	906 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	907 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	908 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	909 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	910 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	911 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	912 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	913 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	914 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	915 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	916 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	917 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	918 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	919 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	920 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	921 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	922 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	923 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	924 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	925 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	926 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	927 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	928 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	929 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	930 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	931 break;
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	932 case MODE_AREG_INDEX_DISP8:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	933 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	934 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	935 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	936 } else {
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	937 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	938 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	939 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	940 if (inst->dst.params.regs.sec & 1) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	941 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	942 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	943 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	944 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	945 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	946 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	947 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	948 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	949 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	950 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	951 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	952 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	953 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	954 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	955 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	956 dst = push_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	957 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	958 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	959 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	960 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	961 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	962 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	963 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	964 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	965 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	966 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	967 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	968 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	969 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	970 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	971 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	972 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	973 dst = pop_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	974 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	975 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	976 if (inst->dst.params.regs.displacement) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	977 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	978 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	979 if (src.mode == MODE_REG_DIRECT) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	980 if (src.base != SCRATCH1) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	981 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	982 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	983 } else if (src.mode == MODE_REG_DISPLACE8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	984 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	985 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	986 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	987 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	988 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	989 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	990 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	991 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	992 }
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	993 switch (inst->extra.size)
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	994 {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	995 case OPSIZE_BYTE:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	996 dst = call(dst, (char *)m68k_write_byte);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	997 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	998 case OPSIZE_WORD:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	999 dst = call(dst, (char *)m68k_write_word);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	1000 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	1001 case OPSIZE_LONG:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	1002 dst = call(dst, (char *)m68k_write_long_highfirst);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	1003 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	1004 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	1005 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1006 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1007 dst = cycles(dst, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1008 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1009 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1010 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1011 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1012 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1013 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1014 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1015 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1016 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1017 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1018 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1019 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1020 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1021 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1022 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1023 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1024 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1025 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1026 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1027 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1028 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1029 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1030 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1031 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1032 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1033 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1034 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1035 break;
196 f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1036 case MODE_PC_INDEX_DISP8:
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1037 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1038 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1039 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1040 if (inst->dst.params.regs.sec & 1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1041 if (inst->dst.params.regs.sec & 0x10) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1042 if (opts->aregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1043 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1044 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1045 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1046 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1047 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1048 if (opts->dregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1049 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1050 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1051 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1052 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1053 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1054 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1055 if (src.base == SCRATCH1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1056 dst = push_r(dst, SCRATCH1);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1057 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1058 if (inst->dst.params.regs.sec & 0x10) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1059 if (opts->aregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1060 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1061 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1062 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1063 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1064 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1065 if (opts->dregs[sec_reg] >= 0) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1066 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1067 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1068 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1069 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1070 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1071 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1072 if (src.base == SCRATCH1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1073 dst = pop_r(dst, SCRATCH1);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1074 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1075 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1076 if (inst->dst.params.regs.displacement) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1077 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1078 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1079 if (src.mode == MODE_REG_DIRECT) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1080 if (src.base != SCRATCH1) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1081 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1082 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1083 } else if (src.mode == MODE_REG_DISPLACE8) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1084 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1085 } else {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1086 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1087 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1088 if (inst->dst.addr_mode != MODE_AREG) {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1089 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1090 dst = setcc_r(dst, CC_Z, FLAG_Z);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1091 dst = setcc_r(dst, CC_S, FLAG_N);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1092 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1093 switch (inst->extra.size)
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1094 {
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1095 case OPSIZE_BYTE:
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1096 dst = call(dst, (char *)m68k_write_byte);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1097 break;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1098 case OPSIZE_WORD:
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1099 dst = call(dst, (char *)m68k_write_word);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1100 break;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1101 case OPSIZE_LONG:
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1102 dst = call(dst, (char *)m68k_write_long_highfirst);
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1103 break;
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1104 }
f8955d33486d Implement pc indexed mode as move dst Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1105 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1106 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1107 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1108 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1109 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1110 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1111 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1112 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1113 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1114 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1115 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1116 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1117 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1118 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1119 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1120 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1121 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1122 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1123 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1124 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1125 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1126 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1127 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1128 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1129 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1130 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1131 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1132 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1133 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1134 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1135 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1136 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1137 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1138 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1139 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	1140 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1141 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1142 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1143 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1144 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1145 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1146
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1147 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1148 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1149 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1150 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1151
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1152 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1153 {
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1154 int8_t bit,reg,sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1155 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1156 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1157 //reg to mem
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1158 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1159 int8_t dir;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1160 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1161 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1162 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1163 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1164 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1165 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1166 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1167 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1168 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1169 break;
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1170 case MODE_AREG_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1171 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1172 reg = SCRATCH2;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1173 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1174 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1175 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1176 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1177 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1178 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1179 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1180 case MODE_AREG_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1181 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1182 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1183 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1184 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1185 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1186 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1187 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1188 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1189 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1190 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1191 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1192 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1193 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1194 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1195 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1196 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1197 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1198 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1199 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1200 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1201 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1202 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1203 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1204 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1205 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1206 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1207 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1208 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1209 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1210 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1211 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1212 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1213 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1214 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1215 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1216 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1217 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1218 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1219 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1220 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1221 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1222 case MODE_PC_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1223 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1224 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1225 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1226 case MODE_PC_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1227 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1228 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1229 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1230 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1231 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1232 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1233 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1234 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1235 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1236 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1237 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1238 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1239 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1240 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1241 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1242 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1243 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1244 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1245 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1246 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1247 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1248 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1249 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1250 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1251 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1252 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1253 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1254 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1255 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1256 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1257 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1258 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1259 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1260 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1261 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1262 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1263 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1264 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1265 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1266 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1267 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1268 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1269 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1270 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1271 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1272 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1273 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1274 }
210 4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1275 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1276 reg = 15;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1277 dir = -1;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1278 } else {
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1279 reg = 0;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1280 dir = 1;
4beaad3a9a50 Fix movem reg to mem for certain addressing modes Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	1281 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1282 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1283 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1284 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1285 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1286 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1287 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1288 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1289 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1290 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1291 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1292 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1293 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1294 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1295 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1296 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1297 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1298 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1299 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1300 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1301 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1302 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1303 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1304 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1305 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1306 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1307 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1308 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1309 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1310 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1311 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1312 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1313 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1314 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1315 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1316 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1317 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1318 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1319 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1320 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1321 //mem to reg
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1322 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1323 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1324 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1325 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1326 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1327 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1328 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1329 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1330 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1331 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1332 break;
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1333 case MODE_AREG_DISPLACE:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1334 early_cycles += BUS;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1335 reg = SCRATCH2;
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1336 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1337 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1338 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1339 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1340 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1341 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1342 break;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1343 case MODE_AREG_INDEX_DISP8:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1344 early_cycles += 6;
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1345 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1346 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1347 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1348 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1349 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1350 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1351 if (inst->src.params.regs.sec & 1) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1352 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1353 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1354 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1355 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1356 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1357 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1358 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1359 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1360 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1361 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1362 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1363 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1364 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1365 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1366 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1367 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1368 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1369 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1370 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1371 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1372 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1373 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1374 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1375 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1376 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1377 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1378 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1379 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1380 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1381 if (inst->src.params.regs.displacement) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1382 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1383 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1384 break;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1385 case MODE_PC_DISPLACE:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1386 early_cycles += BUS;
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1387 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1388 break;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1389 case MODE_PC_INDEX_DISP8:
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1390 early_cycles += 6;
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1391 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1392 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1393 if (inst->src.params.regs.sec & 1) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1394 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1395 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1396 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1397 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1398 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1399 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1400 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1401 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1402 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1403 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1404 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1405 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1406 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1407 } else {
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1408 if (inst->src.params.regs.sec & 0x10) {
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1409 if (opts->aregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1410 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1411 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1412 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1413 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1414 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1415 if (opts->dregs[sec_reg] >= 0) {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1416 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1417 } else {
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1418 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1419 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1420 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1421 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1422 }
169 c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1423 if (inst->src.params.regs.displacement) {
c07713463c91 Fix a bunch of addressing modes in movem when a register list is the destination Mike Pavone <pavone@retrodev.com> parents: 168 diff changeset	1424 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
162 eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1425 }
eba78ad49a11 Implement more movem modes src Mike Pavone <pavone@retrodev.com> parents: 161 diff changeset	1426 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1427 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1428 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1429 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1430 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1431 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1432 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1433 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1434 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1435 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1436 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1437 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1438 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1439 for(reg = 0; reg < 16; reg ++) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1440 if (inst->dst.params.immed & (1 << reg)) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1441 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1442 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1443 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1444 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1445 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1446 }
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1447 if (inst->extra.size == OPSIZE_WORD) {
062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1448 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D);
062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1449 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1450 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1451 if (opts->aregs[reg-8] >= 0) {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1452 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1453 } else {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1454 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1455 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1456 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1457 if (opts->dregs[reg] >= 0) {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1458 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1459 } else {
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	1460 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1461 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1462 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1463 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1464 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1465 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1466 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1467 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1468 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1469 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1470 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1471 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1472 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1473 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1474 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1475 //prefetch
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1476 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1477 return dst;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1478 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1479
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1480 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1481 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1482 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1483 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1484 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1485 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1486 int8_t reg = native_reg(&(inst->dst), opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1487 if (reg >= 0) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1488 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1489 return xor_rr(dst, reg, reg, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1490 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1491 x86_ea dst_op;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1492 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1493 if (dst_op.mode == MODE_REG_DIRECT) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1494 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1495 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1496 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1497 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1498 dst = m68k_save_result(inst, dst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1499 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1500 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1501
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1502 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1503 {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1504 x86_ea dst_op;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1505 uint8_t dst_size = inst->extra.size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1506 inst->extra.size--;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1507 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1508 if (dst_op.mode == MODE_REG_DIRECT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1509 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1510 dst = cmp_ir(dst, 0, dst_op.base, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1511 } else {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1512 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1513 dst = cmp_ir(dst, 0, SCRATCH1, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1514 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1515 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1516 inst->extra.size = dst_size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1517 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1518 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1519 dst = setcc_r(dst, CC_Z, FLAG_Z);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1520 dst = setcc_r(dst, CC_S, FLAG_N);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1521 //M68K EXT only operates on registers so no need for a call to save result here
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1522 return dst;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1523 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1524
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1525 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1526 {
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1527 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1528 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1529 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1530 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1531 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1532 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1533 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1534 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1535 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1536 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1537 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1538 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1539 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1540 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1541 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1542 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1543 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1544 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1545 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1546 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1547 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1548 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1549 if (dst_reg >= 0) {
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1550 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1551 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1552 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1553 } else {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1554 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1555 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1556 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1557 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1558 } else {
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1559 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1560 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1561 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1562 } else {
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1563 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1564 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1565 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1566 }
165 62b152811bae Fix certain address modes with lea when the destination is not a native register Mike Pavone <pavone@retrodev.com> parents: 162 diff changeset	1567 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1568 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1569 break;
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1570 case MODE_AREG_INDEX_DISP8:
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1571 dst = cycles(dst, 12);
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1572 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1573 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1574 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1575 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1576 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1577 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1578 if (inst->src.params.regs.sec & 1) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1579 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1580 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1581 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1582 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1583 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1584 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1585 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1586 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1587 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1588 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1589 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1590 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1591 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1592 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1593 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1594 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1595 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1596 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1597 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1598 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1599 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1600 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1601 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1602 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1603 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1604 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1605 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1606 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1607 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1608 if (inst->src.params.regs.displacement) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1609 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1610 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1611 if (dst_reg >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1612 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1613 } else {
165 62b152811bae Fix certain address modes with lea when the destination is not a native register Mike Pavone <pavone@retrodev.com> parents: 162 diff changeset	1614 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1615 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1616 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1617 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1618 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1619 if (dst_reg >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1620 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1621 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1622 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1623 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1624 break;
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1625 case MODE_PC_INDEX_DISP8:
168 7b099f2b382b Minor optimization and a cycle count fix to lea Mike Pavone <pavone@retrodev.com> parents: 167 diff changeset	1626 dst = cycles(dst, BUS*3);
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1627 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1628 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1629 if (inst->src.params.regs.sec & 1) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1630 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1631 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1632 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1633 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1634 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1635 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1636 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1637 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1638 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1639 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1640 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1641 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1642 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1643 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1644 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1645 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1646 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1647 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1648 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1649 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1650 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1651 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1652 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1653 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1654 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1655 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1656 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1657 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1658 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1659 if (inst->src.params.regs.displacement) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1660 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1661 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1662 if (dst_reg >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1663 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1664 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1665 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1666 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1667 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1668 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1669 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1670 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1671 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1672 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1673 } else {
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1674 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1675 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1676 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1677 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1678 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1679 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1680 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1681 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1682 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1683 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1684
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1685 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1686 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1687 uint8_t sec_reg;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1688 switch(inst->src.addr_mode)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1689 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1690 case MODE_AREG_INDIRECT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1691 dst = cycles(dst, BUS);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1692 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1693 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1694 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1695 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1696 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1697 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1698 case MODE_AREG_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1699 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1700 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1701 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1702 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1703 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1704 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1705 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1706 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1707 case MODE_AREG_INDEX_DISP8:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1708 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1709 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1710 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1711 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1712 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1713 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1714 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1715 if (inst->src.params.regs.sec & 1) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1716 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1717 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1718 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1719 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1720 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1721 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1722 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1723 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1724 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1725 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1726 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1727 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1728 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1729 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1730 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1731 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1732 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1733 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1734 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1735 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1736 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1737 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1738 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1739 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1740 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1741 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1742 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1743 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1744 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1745 if (inst->src.params.regs.displacement) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1746 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1747 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1748 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1749 case MODE_PC_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1750 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1751 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1752 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1753 case MODE_ABSOLUTE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1754 case MODE_ABSOLUTE_SHORT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1755 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1756 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1757 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1758 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1759 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1760 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1761 exit(1);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1762 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1763 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1764 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1765 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1766 return dst;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1767 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1768
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1769 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1770 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1771 int32_t disp = inst->src.params.immed;
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1772 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1773 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1774 dst = cycles(dst, 10);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1775 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1776 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1777 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1778 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1779 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1780 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1781 dst = call(dst, (char *)m68k_write_long_highfirst);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1782 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1783 if (!dest_addr) {
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1784 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1785 //dummy address to be replaced later
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1786 dest_addr = dst + 256;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1787 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1788 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1789 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1790 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1791 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1792 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1793 dst = jmp(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1794 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1795 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1796 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1797
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1798 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1799 {
156 3900cfde9dbb Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive) Mike Pavone <pavone@retrodev.com> parents: 155 diff changeset	1800 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1801 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1802 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1803 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1804 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1805 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1806 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1807 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1808 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1809 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1810 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1811 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1812 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1813 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1814 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1815 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1816 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1817 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1818 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1819 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1820 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1821 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1822 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1823 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1824 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1825 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1826 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1827 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1828 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1829 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1830 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1831 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1832 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1833 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1834 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1835 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1836 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1837 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1838 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1839 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1840 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1841 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1842 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1843 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1844 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1845 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1846 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1847 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1848 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1849 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1850 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1851 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1852 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1853 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1854 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1855 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1856 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1857 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1858 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1859 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1860 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1861 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1862 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1863
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1864 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1865 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1866 uint8_t cond = inst->extra.cond;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1867 x86_ea dst_op;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1868 inst->extra.size = OPSIZE_BYTE;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1869 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1870 if (cond == COND_TRUE \|\| cond == COND_FALSE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1871 if ((inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1872 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1873 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1874 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1875 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1876 if (dst_op.mode == MODE_REG_DIRECT) {
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1877 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1878 } else {
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1879 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1880 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1881 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1882 uint8_t cc = CC_NZ;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1883 switch (cond)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1884 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1885 case COND_HIGH:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1886 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1887 case COND_LOW_SAME:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1888 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1889 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1890 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1891 case COND_CARRY_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1892 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1893 case COND_CARRY_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1894 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1895 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1896 case COND_NOT_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1897 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1898 case COND_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1899 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1900 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1901 case COND_OVERF_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1902 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1903 case COND_OVERF_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1904 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1905 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1906 case COND_PLUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1907 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1908 case COND_MINUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1909 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1910 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1911 case COND_GREATER_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1912 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1913 case COND_LESS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1914 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1915 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1916 case COND_GREATER:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1917 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1918 case COND_LESS_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1919 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1920 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1921 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1922 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1923 }
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1924 uint8_t *true_off = dst + 1;
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1925 dst = jcc(dst, cc, dst+2);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1926 dst = cycles(dst, BUS);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1927 if (dst_op.mode == MODE_REG_DIRECT) {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1928 dst = mov_ir(dst, 0, dst_op.base, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1929 } else {
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1930 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1931 }
179 68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1932 uint8_t *end_off = dst+1;
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1933 dst = jmp(dst, dst+2);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1934 *true_off = dst - (true_off+1);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1935 dst = cycles(dst, 6);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1936 if (dst_op.mode == MODE_REG_DIRECT) {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1937 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1938 } else {
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1939 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B);
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1940 }
68af8a56ab7a Fix scc to set reg to 0xFF rather than 1 when the condition is true Mike Pavone <pavone@retrodev.com> parents: 178 diff changeset	1941 *end_off = dst - (end_off+1);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1942 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1943 dst = m68k_save_result(inst, dst, opts);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1944 return dst;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1945 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1946
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1947 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1948 {
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1949 uint8_t * dest_addr, sec_reg;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1950 uint32_t m68k_addr;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1951 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1952 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1953 case MODE_AREG_INDIRECT:
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1954 dst = cycles(dst, BUS*2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1955 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1956 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1957 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1958 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1959 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1960 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1961 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1962 break;
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1963 case MODE_AREG_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1964 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1965 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1966 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1967 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1968 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1969 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1970 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1971 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1972 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1973 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1974 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1975 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1976 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1977 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1978 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1979 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1980 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1981 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1982 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1983 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1984 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1985 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1986 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1987 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1988 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1989 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1990 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1991 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1992 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1993 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1994 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1995 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1996 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1997 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1998 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1999 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2000 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2001 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2002 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2003 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2004 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2005 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2006 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2007 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2008 dst = cycles(dst, 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2009 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2010 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2011 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2012 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2013 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2014 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2015 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2016 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2017 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2018 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2019 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2020 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2021 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2022 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2023 break;
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2024 case MODE_PC_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2025 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2026 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2027 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2028 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2029 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2030 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2031 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2032 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2033 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2034 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2035 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2036 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2037 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2038 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2039 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2040 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2041 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2042 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2043 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2044 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2045 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2046 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2047 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2048 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2049 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2050 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2051 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2052 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2053 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2054 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2055 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2056 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2057 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2058 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2059 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2060 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2061 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2062 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	2063 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2064 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2065 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2066 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2067 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2068 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2069 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2070 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2071 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2072 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2073 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2074 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2075 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2076 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2077 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2078 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2079 dst = jmp_r(dst, SCRATCH1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2080 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2081 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2082 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2083 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2084 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode);
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 102 diff changeset	2085 exit(1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2086 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2087 return dst;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2088 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2089
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2090 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2091 {
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2092 uint8_t * dest_addr, sec_reg;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2093 uint32_t after;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2094 uint32_t m68k_addr;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2095 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2096 {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2097 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2098 dst = cycles(dst, BUS*2);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2099 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2100 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2101 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2102 }
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	2103 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	2104 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	2105 dst = call(dst, (char *)m68k_write_long_highfirst);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2106 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2107 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2108 } else {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2109 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2110 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2111 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2112 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2113 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2114 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2115 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2116 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2117 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2118 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2119 break;
174 a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2120 case MODE_AREG_DISPLACE:
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2121 dst = cycles(dst, BUS*2);
187 8e138da572ab Fix return address for areg displacement mode JSR Mike Pavone <pavone@retrodev.com> parents: 184 diff changeset	2122 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
174 a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2123 if (opts->flags & OPT_NATIVE_CALL_STACK) {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2124 dst = push_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2125 }
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2126 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2127 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2128 dst = call(dst, (char *)m68k_write_long_highfirst);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2129 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2130 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2131 } else {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2132 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2133 }
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2134 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2135 dst = call(dst, (uint8_t *)m68k_native_addr);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2136 if (opts->flags & OPT_NATIVE_CALL_STACK) {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2137 dst = call_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2138 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2139 dst = pop_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2140 } else {
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2141 dst = jmp_r(dst, SCRATCH1);
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2142 }
a1c3ecb4823f Implement areg displacement mode for jsr Mike Pavone <pavone@retrodev.com> parents: 173 diff changeset	2143 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2144 case MODE_AREG_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2145 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2146 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2147 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2148 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2149 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2150 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2151 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2152 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2153 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2154 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2155 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2156 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2157 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2158 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2159 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2160 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2161 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2162 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2163 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2164 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2165 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2166 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2167 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2168 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2169 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2170 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2171 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2172 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2173 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2174 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2175 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2176 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2177 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2178 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2179 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2180 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2181 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2182 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2183 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2184 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2185 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2186 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2187 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2188 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2189 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2190 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2191 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2192 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2193 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2194 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2195 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2196 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2197 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2198 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2199 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2200 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2201 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2202 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2203 dst = cycles(dst, 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2204 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2205 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2206 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2207 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2208 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2209 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2210 dst = call(dst, (char *)m68k_write_long_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2211 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2212 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2213 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2214 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2215 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2216 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2217 dest_addr = dst + 256;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2218 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2219 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2220 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2221 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2222 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2223 }
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2224 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2225 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2226 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2227 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2228 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2229 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2230 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2231 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2232 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2233 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2234 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2235 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2236 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2237 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2238 case MODE_PC_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2239 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2240 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2241 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2242 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2243 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2244 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2245 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2246 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2247 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2248 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2249 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2250 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2251 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2252 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2253 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2254 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2255 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2256 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2257 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2258 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2259 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2260 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2261 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2262 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2263 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2264 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2265 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2266 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2267 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2268 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2269 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2270 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2271 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2272 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2273 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2274 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2275 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2276 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2277 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2278 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2279 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2280 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2281 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2282 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2283 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2284 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2285 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2286 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2287 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2288 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2289 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	2290 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2291 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2292 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2293 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2294 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2295 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2296 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2297 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2298 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2299 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2300 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2301 dst = call(dst, (char *)m68k_write_long_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2302 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2303 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2304 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2305 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2306 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2307 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2308 dest_addr = dst + 256;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2309 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2310 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2311 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2312 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2313 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2314 }
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2315 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2316 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2317 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2318 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2319 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2320 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2321 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2322 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2323 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2324 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2325 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2326 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2327 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2328 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2329 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2330 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2331 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode);
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2332 exit(1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2333 }
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2334 return dst;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2335 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2336
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2337 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2338 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2339 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2340 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2341 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2342 dst = call(dst, (char *)m68k_read_long_scratch1);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2343 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2344 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2345 dst = jcc(dst, CC_NZ, dst+3);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2346 dst = retn(dst);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2347 dst = jmp(dst, (char *)m68k_modified_ret_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2348 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2349 dst = call(dst, (uint8_t *)m68k_native_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2350 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2351 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2352 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2353 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2354
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2355 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2356 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2357 //best case duration
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2358 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2359 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2360 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2361 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2362 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2363 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2364 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2365 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2366 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2367 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2368 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2369 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2370 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2371 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2372 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2373 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2374 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2375 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2376 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2377 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2378 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2379 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2380 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2381 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2382 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2383 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2384 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2385 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2386 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2387 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2388 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2389 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2390 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2391 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2392 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2393 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2394 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2395 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2396 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2397 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2398 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2399 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2400 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2401 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2402 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2403 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2404 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2405 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2406 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2407 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2408 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2409 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2410 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2411 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2412 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2413 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2414 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2415 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2416 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2417 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2418 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2419 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2420 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2421 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2422 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2423 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2424 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2425 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2426 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2427 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2428 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2429 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2430 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2431 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2432 }
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2433 return dst;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2434 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2435
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2436 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2437 {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2438 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2439 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2440 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2441 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2442 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2443 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2444 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2445 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2446 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2447 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2448 dst = call(dst, (char *)m68k_write_long_highfirst);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2449 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2450 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2451 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2452 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2453 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2454 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2455 //prefetch
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2456 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2457 return dst;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2458 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2459
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2460 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2461 {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2462 int8_t reg;
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2463 dst = cycles(dst, BUS*2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2464 if (inst->src.addr_mode == MODE_REG) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2465 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2466 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2467 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2468 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2469 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2470 if (inst->dst.params.regs.displacement) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2471 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2472 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2473 reg = native_reg(&(inst->src), opts);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2474 if (inst->extra.size == OPSIZE_LONG) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2475 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2476 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2477 dst = shr_ir(dst, 24, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2478 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2479 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2480 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2481 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2482 dst = shr_ir(dst, 16, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2483
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2484 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2485 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2486 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2487 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2488 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2489 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2490 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2491 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2492 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2493 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2494 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2495 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2496 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2497 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2498 dst = mov_rr(dst, reg, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2499 dst = shr_ir(dst, 8, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2500 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2501 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2502 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2503 dst = mov_rr(dst, reg, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2504 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2505 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2506 dst = push_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2507 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2508 dst = pop_r(dst, SCRATCH2);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2509 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2510 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2511 dst = add_ir(dst, 2, SCRATCH2, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2512 dst = call(dst, (uint8_t *)m68k_write_byte);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2513 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2514 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2515 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2516 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2517 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2518 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2519 if (inst->src.params.regs.displacement) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2520 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2521 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2522 reg = native_reg(&(inst->dst), opts);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2523 if (inst->extra.size == OPSIZE_LONG) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2524 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2525 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2526 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2527 dst = shl_ir(dst, 24, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2528 dst = mov_rr(dst, SCRATCH1, reg, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2529 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2530 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2531 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2532 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2533 dst = shl_ir(dst, 16, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2534 dst = or_rr(dst, SCRATCH1, reg, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2535 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2536 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2537 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2538 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2539 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2540 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2541 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2542 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2543 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2544 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2545 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2546 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2547 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2548 dst = push_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2549 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2550 if (reg >= 0) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2551
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2552 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2553 dst = mov_rr(dst, SCRATCH1, reg, SZ_W);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2554 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2555 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2556 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2557 dst = mov_rr(dst, SCRATCH1, reg, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2558 } else {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2559 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2560 dst = pop_r(dst, SCRATCH1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2561 dst = add_ir(dst, 2, SCRATCH1, SZ_D);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2562 dst = call(dst, (uint8_t *)m68k_read_byte_scratch1);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2563 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B);
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2564 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2565 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2566 return dst;
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2567 }
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2568
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2569 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2570 {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2571 uint8_t size = inst->extra.size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2572 x86_ea src_op, dst_op;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2573 dst = translate_m68k_src(inst, &src_op, dst, opts);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2574 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2575 dst = push_r(dst, SCRATCH1);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2576 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2577 dst = pop_r(dst, SCRATCH2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2578 src_op.base = SCRATCH2;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2579 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2580 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2581 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2582 size = OPSIZE_LONG;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2583 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2584 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2585 dst = cycles(dst, BUS);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2586 if (src_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2587 if (dst_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2588 dst = cmp_rr(dst, src_op.base, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2589 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2590 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2591 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2592 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2593 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2594 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2595 if (dst_op.mode == MODE_REG_DIRECT) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2596 dst = cmp_ir(dst, src_op.disp, dst_op.base, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2597 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2598 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2599 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2600 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2601 dst = setcc_r(dst, CC_C, FLAG_C);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2602 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2603 dst = setcc_r(dst, CC_S, FLAG_N);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2604 dst = setcc_r(dst, CC_O, FLAG_V);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2605 return dst;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2606 }
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2607
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2608 typedef uint8_t * (shift_ir_t)(uint8_t out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2609 typedef uint8_t * (shift_irdisp8_t)(uint8_t out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2610 typedef uint8_t * (shift_clr_t)(uint8_t out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2611 typedef uint8_t * (shift_clrdisp8_t)(uint8_t out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2612
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2613 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea src_op, x86_ea dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2614 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2615 uint8_t * end_off = NULL;
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2616 uint8_t * nz_off = NULL;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2617 uint8_t * z_off = NULL;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2618 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2619 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2620 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2621 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2622 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2623 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2624 if (src_op->mode == MODE_IMMED) {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2625 if (src_op->disp != 1 && inst->op == M68K_ASL) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2626 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2627 for (int i = 0; i < src_op->disp; i++) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2628 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2629 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2630 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2631 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2632 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2633 //dst = setcc_r(dst, CC_O, FLAG_V);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2634 dst = jcc(dst, CC_NO, dst+4);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2635 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2636 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2637 } else {
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2638 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2639 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2640 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2641 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2642 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	2643 dst = setcc_r(dst, CC_O, FLAG_V);
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2644 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2645 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2646 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2647 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2648 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2649 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2650 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2651 }
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2652
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2653 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2654 dst = and_ir(dst, 63, RCX, SZ_D);
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2655 nz_off = dst+1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2656 dst = jcc(dst, CC_NZ, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2657 //Flag behavior for shift count of 0 is different for x86 than 68K
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2658 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2659 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2660 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2661 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2662 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2663 dst = setcc_r(dst, CC_Z, FLAG_Z);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2664 dst = setcc_r(dst, CC_S, FLAG_N);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2665 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2666 //For other instructions, this flag will be set below
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2667 if (inst->op == M68K_ASL) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2668 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2669 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2670 z_off = dst+1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2671 dst = jmp(dst, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2672 *nz_off = dst - (nz_off + 1);
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2673 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2674 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2675 dst = add_rr(dst, RCX, CYCLES, SZ_D);
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2676 if (inst->op == M68K_ASL) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2677 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2678 //Easiest way to deal with this is to shift one bit at a time
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2679 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2680 uint8_t * loop_start = dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2681 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2682 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2683 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2684 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2685 }
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2686 //dst = setcc_r(dst, CC_O, FLAG_V);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2687 dst = jcc(dst, CC_NO, dst+4);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2688 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2689 dst = loop(dst, loop_start);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2690 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2691 //x86 shifts modulo 32 for operand sizes less than 64-bits
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2692 //but M68K shifts modulo 64, so we need to check for large shifts here
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2693 dst = cmp_ir(dst, 32, RCX, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2694 uint8_t * norm_shift_off = dst + 1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2695 dst = jcc(dst, CC_L, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2696 if (special) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2697 if (inst->extra.size == OPSIZE_LONG) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2698 uint8_t * neq_32_off = dst + 1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2699 dst = jcc(dst, CC_NZ, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2700
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2701 //set the carry bit to the lsb
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2702 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2703 dst = special(dst, 1, dst_op->base, SZ_D);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2704 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2705 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2706 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2707 dst = setcc_r(dst, CC_C, FLAG_C);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2708 dst = jmp(dst, dst+4);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2709 *neq_32_off = dst - (neq_32_off+1);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2710 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2711 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2712 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2713 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2714 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2715 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2716 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2717 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2718 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2719 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2720 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2721 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2722 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2723 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2724 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2725 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2726 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2727
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2728 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2729 end_off = dst+1;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2730 dst = jmp(dst, dst+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2731 *norm_shift_off = dst - (norm_shift_off+1);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2732 if (dst_op->mode == MODE_REG_DIRECT) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2733 dst = shift_clr(dst, dst_op->base, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2734 } else {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2735 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2736 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2737 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2738 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2739
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2740 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2741 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2742 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2743 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2744 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2745 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2746 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2747 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2748 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2749 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2750 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2751 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2752 if (z_off) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2753 *z_off = dst - (z_off + 1);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2754 }
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2755 if (inst->op != M68K_ASL && inst->src.addr_mode != MODE_UNUSED && !(src_op->mode == MODE_IMMED && src_op->disp == 1)) {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2756 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	2757 }
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2758 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2759 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2760 }
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	2761 return dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2762 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2763
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2764 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2765
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2766 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2767 {
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2768 uint8_t * end_off, zero_off, norm_off;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2769 uint8_t dst_reg;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2770 dst = check_cycles_int(dst, inst->address);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2771 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2772 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2773 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2774 return translate_m68k_lea(dst, inst, opts);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	2775 } else if(inst->op == M68K_PEA) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	2776 return translate_m68k_pea(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2777 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2778 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2779 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2780 return translate_m68k_bcc(dst, inst, opts);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2781 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2782 return translate_m68k_jmp(dst, inst, opts);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2783 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2784 return translate_m68k_jsr(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2785 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2786 return translate_m68k_rts(dst, inst, opts);
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2787 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2788 return translate_m68k_dbcc(dst, inst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2789 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2790 return translate_m68k_clr(dst, inst, opts);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2791 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2792 return translate_m68k_movem(dst, inst, opts);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2793 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2794 return translate_m68k_link(dst, inst, opts);
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2795 } else if(inst->op == M68K_EXT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2796 return translate_m68k_ext(dst, inst, opts);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2797 } else if(inst->op == M68K_SCC) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2798 return translate_m68k_scc(dst, inst, opts);
172 c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2799 } else if(inst->op == M68K_MOVEP) {
c61507f897e4 Implement movep Mike Pavone <pavone@retrodev.com> parents: 171 diff changeset	2800 return translate_m68k_movep(dst, inst, opts);
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	2801 } else if(inst->op == M68K_INVALID) {
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	2802 if (inst->src.params.immed == 0x7100) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	2803 return retn(dst);
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	2804 }
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	2805 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D);
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	2806 return call(dst, (uint8_t *)m68k_invalid);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2807 } else if(inst->op == M68K_CMP) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2808 return translate_m68k_cmp(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2809 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2810 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2811 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2812 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2813 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2814 if (inst->dst.addr_mode != MODE_UNUSED) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	2815 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2816 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2817 uint8_t size;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2818 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2819 {
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2820 case M68K_ABCD:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2821 if (src_op.base != SCRATCH2) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2822 if (src_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2823 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2824 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2825 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2826 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2827 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2828 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2829 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2830 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2831 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2832 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2833 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2834 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2835 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2836 dst = jcc(dst, CC_NC, dst+5);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2837 dst = add_ir(dst, 1, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2838 dst = call(dst, (uint8_t *)bcd_add);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2839 dst = mov_rr(dst, CH, FLAG_C, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2840 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2841 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2842 dst = jcc(dst, CC_Z, dst+4);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2843 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2844 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2845 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2846 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2847 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2848 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2849 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2850 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2851 dst = m68k_save_result(inst, dst, opts);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	2852 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2853 case M68K_ADD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2854 dst = cycles(dst, BUS);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2855 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2856 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2857 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2858 dst = add_rr(dst, src_op.base, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2859 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2860 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2861 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2862 } else if (src_op.mode == MODE_REG_DISPLACE8) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2863 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2864 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2865 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2866 dst = add_ir(dst, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2867 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	2868 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2869 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2870 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2871 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2872 dst = setcc_r(dst, CC_C, FLAG_C);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2873 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2874 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2875 dst = setcc_r(dst, CC_O, FLAG_V);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2876 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2877 }
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2878 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2879 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2880 case M68K_ADDX:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2881 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2882 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2883 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2884 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2885 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2886 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2887 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2888 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2889 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2890 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2891 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2892 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2893 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2894 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2895 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2896 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2897 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2898 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2899 dst = jcc(dst, CC_Z, dst+4);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	2900 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2901 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2902 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2903 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2904 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2905 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2906 case M68K_AND:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2907 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2908 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2909 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2910 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2911 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2912 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2913 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2914 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2915 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2916 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2917 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2918 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2919 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2920 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2921 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2922 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2923 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2924 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2925 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2926 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2927 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2928 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2929 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2930 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2931 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2932 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2933 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2934 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2935 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2936 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2937 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2938 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2939 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2940 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2941 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2942 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2943 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2944 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2945 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2946 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2947 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2948 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2949 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2950 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2951 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2952 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2953 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2954 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2955 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2956 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2957 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2958 }
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2959 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2960 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2961 case M68K_ASL:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2962 case M68K_LSL:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2963 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2964 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2965 case M68K_ASR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2966 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2967 break;
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2968 case M68K_LSR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2969 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2970 break;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2971 case M68K_BCHG:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2972 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2973 case M68K_BSET:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2974 case M68K_BTST:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2975 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67 534eb4976423 Fix BTST Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	2976 if (src_op.mode == MODE_IMMED) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2977 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2978 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2979 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2980 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2981 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2982 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2983 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2984 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2985 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2986 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2987 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2988 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2989 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2990 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2991 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2992 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2993 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2994 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2995 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2996 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2997 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2998 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2999 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3000 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3001 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3002 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3003 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3004 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3005 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3006 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3007 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3008 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3009 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3010 src_op.base = SCRATCH2;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3011 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3012 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3013 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3014 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3015 }
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3016 if (dst_op.mode == MODE_REG_DISPLACE8) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3017 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3018 if (src_op.mode == MODE_REG_DIRECT) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3019 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3020 } else {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3021 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3022 src_op.mode = MODE_REG_DIRECT;
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3023 }
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3024 src_op.base = SCRATCH1;
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3025 }
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3026 dst = and_ir(dst, 31, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	3027 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3028 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3029 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3030 dst = bt_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3031 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3032 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3033 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3034 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3035 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3036 dst = bts_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3037 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3038 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3039 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3040 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3041 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3042 dst = btr_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3043 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3044 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3045 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3046 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3047 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3048 dst = btc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3049 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3050 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	3051 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3052 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3053 if (src_op.base == SCRATCH2) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3054 dst = pop_r(dst, SCRATCH2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3055 }
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3056 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3057 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3058 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3059 dst = setcc_r(dst, CC_NC, FLAG_Z);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3060 if (inst->op != M68K_BTST) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	3061 dst = m68k_save_result(inst, dst, opts);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3062 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	3063 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3064 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3065 break;*/
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3066 case M68K_DIVS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3067 case M68K_DIVU:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3068 //TODO: Trap on division by zero
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3069 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3070 dst = push_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3071 dst = push_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3072 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3073 dst = mov_rr(dst, dst_op.base, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3074 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3075 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3076 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3077 if (src_op.mode == MODE_IMMED) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3078 dst = mov_ir(dst, src_op.disp, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3079 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3080 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3081 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3082 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3083 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3084 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3085 } else if (src_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3086 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3087 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3088 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3089 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3090 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3091 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3092 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3093 dst = cdq(dst);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3094 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3095 dst = xor_rr(dst, RDX, RDX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3096 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3097 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3098 dst = idiv_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3099 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3100 dst = div_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3101 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3102 dst = cmp_ir(dst, 0x10000, RAX, SZ_D);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3103 if (inst->op == M68K_DIVS) {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3104 uint8_t * skip_sec_check = dst + 1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3105 dst = jcc(dst, CC_C, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3106 dst = cmp_ir(dst, -0x10000, RAX, SZ_D);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3107 norm_off = dst+1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3108 dst = jcc(dst, CC_LE, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3109 *skip_sec_check = dst - (skip_sec_check+1);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3110 } else {
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3111 norm_off = dst+1;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3112 dst = jcc(dst, CC_NC, dst+2);
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3113 }
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3114 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3115 dst = mov_rr(dst, RDX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3116 dst = shl_ir(dst, 16, dst_op.base, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3117 dst = mov_rr(dst, RAX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3118 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3119 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3120 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3121 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3122 }
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3123 dst = cmp_ir(dst, 0, RAX, SZ_W);
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3124 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3125 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3126 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3127 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3128 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3129 end_off = dst+1;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3130 dst = jmp(dst, dst+2);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3131 *norm_off = dst - (norm_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3132 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3133 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3134 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3135 *end_off = dst - (end_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3136 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3137 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3138 case M68K_EOR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3139 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3140 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3141 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3142 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3143 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3144 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3145 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3146 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3147 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3148 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3149 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3150 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3151 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3152 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3153 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3154 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3155 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3156 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3157 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3158 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3159 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3160 break;
171 f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3161 case M68K_EORI_CCR:
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3162 case M68K_EORI_SR:
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3163 dst = cycles(dst, 20);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3164 //TODO: If ANDI to SR, trap if not in supervisor mode
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3165 if (inst->src.params.immed & 0x1) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3166 dst = xor_ir(dst, 1, FLAG_C, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3167 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3168 if (inst->src.params.immed & 0x2) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3169 dst = xor_ir(dst, 1, FLAG_V, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3170 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3171 if (inst->src.params.immed & 0x4) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3172 dst = xor_ir(dst, 1, FLAG_Z, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3173 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3174 if (inst->src.params.immed & 0x8) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3175 dst = xor_ir(dst, 1, FLAG_N, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3176 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3177 if (inst->src.params.immed & 0x10) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3178 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3179 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3180 if (inst->op == M68K_ORI_SR) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3181 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3182 if (inst->src.params.immed & 0x700) {
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3183 dst = call(dst, (uint8_t *)do_sync);
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3184 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3185 }
f03db3db48fb Implement EORI CCR/SR Mike Pavone <pavone@retrodev.com> parents: 170 diff changeset	3186 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3187 case M68K_EXG:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3188 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3189 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3190 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3191 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3192 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3193 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3194 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3195 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3196 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3197 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3198 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3199 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3200 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3201 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3202 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3203 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3204 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3205 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3206 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3207 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3208 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3209 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3210 case M68K_ILLEGAL:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3211 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3212 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3213 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3214 break;
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3215 case M68K_MOVE_FROM_SR:
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3216 //TODO: Trap if not in system mode
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3217 dst = call(dst, (uint8_t *)get_sr);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3218 if (dst_op.mode == MODE_REG_DIRECT) {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3219 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3220 } else {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3221 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3222 }
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3223 dst = m68k_save_result(inst, dst, opts);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	3224 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3225 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3226 case M68K_MOVE_SR:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3227 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3228 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3229 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3230 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3231 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3232 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3233 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3234 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3235 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3236 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3237 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3238 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3239 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3240 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3241 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3242 dst = call(dst, (uint8_t *)do_sync);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3243 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3244 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3245 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3246 if (src_op.base != SCRATCH1) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3247 if (src_op.mode == MODE_REG_DIRECT) {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3248 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3249 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3250 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3251 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3252 }
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3253 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr));
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3254 dst = cycles(dst, 12);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3255
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3256 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3257 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3258 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3259 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3260 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3261 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3262 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3263 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3264 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3265 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3266 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3267 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3268 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3269 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3270 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3271 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3272 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3273 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3274 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3275 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3276 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	3277 break;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3278 //case M68K_MOVEP:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3279 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3280 case M68K_MULU:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3281 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3282 if (src_op.mode == MODE_IMMED) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3283 //immediate value should already be sign extended to 32-bits
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3284 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : src_op.disp, SCRATCH1, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3285 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3286 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3287 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3288 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3289 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3290 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3291 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3292 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3293 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3294 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3295 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3296 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3297 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3298 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3299 dst_reg = dst_op.base;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3300 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3301 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3302 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3303 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3304 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3305 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3306 dst_reg = SCRATCH2;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3307 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3308 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3309 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3310 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3311 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3312 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3313 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3314 if (dst_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3315 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3316 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3317 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3318 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3319 dst = cmp_ir(dst, 0, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3320 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3321 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3322 break;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3323 //case M68K_NBCD:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3324 case M68K_NEG:
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3325 dst = cycles(dst, BUS);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3326 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3327 dst = neg_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3328 } else {
165 62b152811bae Fix certain address modes with lea when the destination is not a native register Mike Pavone <pavone@retrodev.com> parents: 162 diff changeset	3329 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3330 }
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3331 dst = setcc_r(dst, CC_C, FLAG_C);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3332 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3333 dst = setcc_r(dst, CC_S, FLAG_N);
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3334 dst = setcc_r(dst, CC_O, FLAG_V);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3335 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3336 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3337 break;
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3338 case M68K_NEGX:
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3339 dst = cycles(dst, BUS);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3340 if (dst_op.mode == MODE_REG_DIRECT) {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3341 if (dst_op.base == SCRATCH1) {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3342 dst = push_r(dst, SCRATCH2);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3343 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3344 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3345 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3346 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3347 dst = pop_r(dst, SCRATCH2);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3348 } else {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3349 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3350 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3351 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3352 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3353 }
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3354 } else {
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3355 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3356 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3357 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3358 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3359 }
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3360 dst = setcc_r(dst, CC_C, FLAG_C);
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3361 dst = jcc(dst, CC_Z, dst+4);
922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3362 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
173 47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3363 dst = setcc_r(dst, CC_S, FLAG_N);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3364 dst = setcc_r(dst, CC_O, FLAG_V);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3365 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3366 dst = m68k_save_result(inst, dst, opts);
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3367 break;
47b2796fb277 Implement negx Mike Pavone <pavone@retrodev.com> parents: 172 diff changeset	3368 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3369 case M68K_NOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3370 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3371 break;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3372 case M68K_NOT:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3373 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3374 dst = not_r(dst, dst_op.base, inst->extra.size);
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3375 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3376 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3377 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3378 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3379 }
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	3380
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3381 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3382 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3383 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3384 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3385 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3386 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3387 case M68K_OR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3388 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3389 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3390 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3391 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3392 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3393 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3394 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3395 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3396 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3397 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3398 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3399 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3400 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3401 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3402 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3403 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3404 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3405 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3406 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3407 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3408 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3409 break;
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3410 case M68K_ORI_CCR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3411 case M68K_ORI_SR:
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3412 dst = cycles(dst, 20);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3413 //TODO: If ANDI to SR, trap if not in supervisor mode
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3414 if (inst->src.params.immed & 0x1) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3415 dst = mov_ir(dst, 1, FLAG_C, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3416 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3417 if (inst->src.params.immed & 0x2) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3418 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3419 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3420 if (inst->src.params.immed & 0x4) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3421 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3422 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3423 if (inst->src.params.immed & 0x8) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3424 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3425 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3426 if (inst->src.params.immed & 0x10) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3427 dst = mov_irind(dst, 1, CONTEXT, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3428 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3429 if (inst->op == M68K_ORI_SR) {
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3430 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3431 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3432 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3433 }
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3434 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	3435 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3436 case M68K_RESET:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3437 dst = call(dst, (uint8_t *)m68k_save_context);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3438 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3439 dst = call(dst, (uint8_t *)print_regs_exit);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: 211 diff changeset	3440 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3441 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3442 case M68K_ROR:
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3443 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3444 if (inst->src.addr_mode == MODE_UNUSED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3445 dst = cycles(dst, BUS);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3446 //Memory rotate
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3447 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3448 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3449 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3450 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3451 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3452 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3453 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3454 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3455 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3456 dst = m68k_save_result(inst, dst, opts);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3457 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3458 if (src_op.mode == MODE_IMMED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3459 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3460 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3461 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3462 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3463 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3464 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3465 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3466 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3467 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3468 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3469 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3470 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3471 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3472 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3473 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3474 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3475 if (src_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3476 if (src_op.base != SCRATCH1) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3477 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3478 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3479 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3480 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3481 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3482 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3483 zero_off = dst+1;
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3484 dst = jcc(dst, CC_Z, dst+2);
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3485 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3486 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3487 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3488 norm_off = dst+1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3489 dst = jcc(dst, CC_L, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3490 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3491 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3492 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3493 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3494 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3495 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3496 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3497 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3498 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3499 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3500 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3501 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3502 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3503 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3504 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3505 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3506 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3507 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3508 *norm_off = dst - (norm_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3509 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3510 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3511 dst = rol_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3512 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3513 dst = ror_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3514 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3515 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3516 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3517 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3518 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3519 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3520 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3521 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3522 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3523 end_off = dst + 1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3524 dst = jmp(dst, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3525 *zero_off = dst - (zero_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3526 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3527 *end_off = dst - (end_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3528 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3529 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3530 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3531 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3532 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3533 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3534 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3535 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3536 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	3537 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3538 case M68K_ROXL:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3539 case M68K_ROXR:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3540 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3541 if (inst->src.addr_mode == MODE_UNUSED) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3542 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3543 //Memory rotate
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3544 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3545 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3546 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3547 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3548 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3549 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3550 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3551 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3552 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3553 dst = setcc_r(dst, CC_S, FLAG_N);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3554 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3555 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3556 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3557 if (src_op.mode == MODE_IMMED) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3558 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3559 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3560 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3561 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3562 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3563 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3564 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3565 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3566 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3567 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3568 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3569 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3570 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3571 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3572 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3573 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3574 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3575 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3576 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3577 if (src_op.base != SCRATCH1) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3578 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3579 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3580 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3581 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3582 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3583 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3584 zero_off = dst+1;
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3585 dst = jcc(dst, CC_Z, dst+2);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3586 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3587 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3588 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3589 norm_off = dst+1;
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3590 dst = jcc(dst, CC_L, dst+2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3591 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3592 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3593 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3594 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3595 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3596 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3597 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3598 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3599 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3600 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3601 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3602 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3603 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3604 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3605 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3606 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3607 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3608 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3609 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3610 *norm_off = dst - (norm_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3611 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3612 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3613 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3614 dst = rcl_clr(dst, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3615 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3616 dst = rcr_clr(dst, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3617 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3618 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3619 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3620 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3621 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3622 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3623 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3624 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3625 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3626 dst = mov_rr(dst, FLAG_C, CONTEXT, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3627 end_off = dst + 1;
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3628 dst = jmp(dst, dst+2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3629 *zero_off = dst - (zero_off+1);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3630 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3631 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3632 *end_off = dst - (end_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3633 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3634 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3635 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3636 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3637 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3638 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3639 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3640 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3641 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3642 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3643 case M68K_RTE:
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3644 //TODO: Trap if not in system mode
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3645 //Read saved SR
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3646 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3647 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3648 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3649 dst = call(dst, (uint8_t *)set_sr);
178 48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3650 //Read saved PC
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3651 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3652 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
48eb62ba63bc Fix order of reading saved pc and swapping user and system stack pointers Mike Pavone <pavone@retrodev.com> parents: 177 diff changeset	3653 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3654 //Check if we've switched to user mode and swap stack pointers if needed
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3655 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3656 end_off = dst+1;
121 f848aad2abef Fix logic for switching between USP and SSP Mike Pavone <pavone@retrodev.com> parents: 119 diff changeset	3657 dst = jcc(dst, CC_C, dst+2);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3658 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3659 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3660 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3661 *end_off = dst - (end_off+1);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3662 //Get native address, sync components, recalculate integer points and jump to returned address
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3663 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3664 dst = jmp_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3665 break;
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3666 case M68K_RTR:
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3667 //Read saved CCR
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3668 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3669 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3670 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3671 dst = call(dst, (uint8_t *)set_ccr);
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3672 //Read saved PC
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3673 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3674 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3675 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3676 //Get native address and jump to it
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 174 diff changeset	3677 dst = call(dst, (uint8_t *)m68k_native_addr);
170 7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3678 dst = jmp_r(dst, SCRATCH1);
7d1b04537377 Implement RTR Mike Pavone <pavone@retrodev.com> parents: 169 diff changeset	3679 break;
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3680 case M68K_SBCD:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3681 if (src_op.base != SCRATCH2) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3682 if (src_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3683 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3684 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3685 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3686 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3687 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3688 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3689 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3690 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3691 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3692 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3693 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3694 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3695 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3696 dst = jcc(dst, CC_NC, dst+5);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3697 dst = sub_ir(dst, 1, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3698 dst = call(dst, (uint8_t *)bcd_sub);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3699 dst = mov_rr(dst, CH, FLAG_C, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3700 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3701 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3702 dst = jcc(dst, CC_Z, dst+4);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3703 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3704 if (dst_op.base != SCRATCH1) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3705 if (dst_op.mode == MODE_REG_DIRECT) {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3706 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3707 } else {
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3708 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3709 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3710 }
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3711 dst = m68k_save_result(inst, dst, opts);
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3712 break;
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	3713 /*case M68K_STOP:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3714 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3715 case M68K_SUB:
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3716 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3717 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3718 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3719 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3720 dst = sub_rr(dst, src_op.base, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3721 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3722 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3723 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3724 } else if (src_op.mode == MODE_REG_DISPLACE8) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3725 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3726 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3727 if (dst_op.mode == MODE_REG_DIRECT) {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3728 dst = sub_ir(dst, src_op.disp, dst_op.base, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3729 } else {
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3730 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3731 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3732 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3733 if (inst->dst.addr_mode != MODE_AREG) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3734 dst = setcc_r(dst, CC_C, FLAG_C);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3735 dst = setcc_r(dst, CC_Z, FLAG_Z);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3736 dst = setcc_r(dst, CC_S, FLAG_N);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3737 dst = setcc_r(dst, CC_O, FLAG_V);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3738 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3739 }
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3740 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3741 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3742 case M68K_SUBX:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3743 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3744 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3745 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3746 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3747 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3748 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3749 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3750 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3751 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3752 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3753 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3754 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3755 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3756 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3757 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3758 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3759 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3760 dst = setcc_r(dst, CC_C, FLAG_C);
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3761 dst = jcc(dst, CC_Z, dst+4);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3762 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3763 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3764 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3765 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3766 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3767 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3768 case M68K_SWAP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3769 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3770 if (src_op.mode == MODE_REG_DIRECT) {
129 691e4b147cea Fix swap Mike Pavone <pavone@retrodev.com> parents: 128 diff changeset	3771 dst = rol_ir(dst, 16, src_op.base, SZ_D);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3772 } else{
129 691e4b147cea Fix swap Mike Pavone <pavone@retrodev.com> parents: 128 diff changeset	3773 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3774 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3775 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3776 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3777 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3778 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3779 break;
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3780 //case M68K_TAS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3781 case M68K_TRAP:
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3782 dst = mov_ir(dst, src_op.disp, SCRATCH2, SZ_D);
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 182 diff changeset	3783 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3784 dst = jmp(dst, (uint8_t *)m68k_trap);
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3785 break;
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3786 //case M68K_TRAPV:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3787 case M68K_TST:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3788 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3789 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3790 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3791 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3792 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3793 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3794 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3795 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3796 dst = setcc_r(dst, CC_S, FLAG_N);
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 179 diff changeset	3797 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3798 break;
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3799 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3800 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3801 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3802 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3803 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3804 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3805 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3806 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3807 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3808 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3809 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3810 } else {
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	3811 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3812 }
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	3813 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3814 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3815 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3816 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3817 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op);
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3818 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3819 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3820 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3821 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3822
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3823 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3824 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3825 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3826 x86_68k_options * opts = context->options;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3827 uint8_t * dst = opts->cur_code;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3828 uint8_t * dst_end = opts->code_end;
188 062e3aa549eb Fix movem.w when dest is register list Mike Pavone <pavone@retrodev.com> parents: 187 diff changeset	3829 address &= 0xFFFFFF;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3830 if(get_native_address(opts->native_code_map, address)) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3831 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3832 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3833 char disbuf[1024];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3834 uint16_t encoded, next;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3835 if ((address & 0xFFFFFF) < 0x400000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3836 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3837 } else if ((address & 0xFFFFFF) > 0xE00000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3838 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3839 } else {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3840 printf("attempt to translate non-memory address: %X\n", address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3841 exit(1);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3842 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3843 do {
197 7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 196 diff changeset	3844 if (opts->address_log) {
7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 196 diff changeset	3845 fprintf(opts->address_log, "%X\n", address);
7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 196 diff changeset	3846 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3847 do {
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3848 if (dst_end-dst < MAX_NATIVE_SIZE) {
102 bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3849 if (dst_end-dst < 5) {
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3850 puts("out of code memory, not enough space for jmp to next chunk");
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3851 exit(1);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3852 }
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3853 size_t size = 1024*1024;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3854 opts->cur_code = alloc_code(&size);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3855 opts->code_end = opts->cur_code + size;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3856 jmp(dst, opts->cur_code);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3857 dst = opts->cur_code;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3858 dst_end = opts->code_end;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3859 }
159 c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3860 if (address >= 0x400000 && address < 0xE00000) {
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3861 dst = xor_rr(dst, RDI, RDI, SZ_D);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3862 dst = call(dst, (uint8_t *)exit);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3863 break;
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3864 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3865 uint8_t * existing = get_native_address(opts->native_code_map, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3866 if (existing) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3867 dst = jmp(dst, existing);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3868 break;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3869 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3870 next = m68k_decode(encoded, &instbuf, address);
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	3871 if (instbuf.op == M68K_INVALID) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	3872 instbuf.src.params.immed = *encoded;
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	3873 }
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	3874 uint16_t m68k_size = (next-encoded)*2;
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	3875 address += m68k_size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3876 encoded = next;
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3877 //m68k_disasm(&instbuf, disbuf);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3878 //printf("%X: %s\n", instbuf.address, disbuf);
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	3879 uint8_t * after = translate_m68k(dst, &instbuf, opts);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	3880 map_native_address(context, instbuf.address, dst, m68k_size, after-dst);
1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	3881 dst = after;
177 09761d4391e1 Make sure we bail out of translation after translating an invalid instruction Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	3882 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_INVALID && instbuf.op != M68K_TRAP && instbuf.op != M68K_RTS && instbuf.op != M68K_RTR && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3883 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3884 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3885 address = opts->deferred->address;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3886 if ((address & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3887 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3888 } else if ((address & 0xFFFFFF) > 0xE00000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3889 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3890 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3891 printf("attempt to translate non-memory address: %X\n", address);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3892 exit(1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3893 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3894 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3895 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3896 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3897 } while(encoded != NULL);
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3898 opts->cur_code = dst;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3899 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3900 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3901
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3902 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address)
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3903 {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3904 address &= 0xFFFFFF;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3905 uint8_t * ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3906 if (!ret) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3907 translate_m68k_stream(address, context);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3908 ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3909 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3910 return ret;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3911 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3912
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3913 void * m68k_retranslate_inst(uint32_t address, m68k_context * context)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3914 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3915 x86_68k_options * opts = context->options;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3916 uint8_t orig_size = get_native_inst_size(opts, address);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3917 uint8_t * orig_start = get_native_address(context->native_code_map, address);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3918 uint32_t orig = address;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3919 address &= 0xFFFF;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3920 uint8_t * dst = opts->cur_code;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3921 uint8_t * dst_end = opts->code_end;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3922 uint16_t after, inst = context->mem_pointers[1] + address/2;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3923 m68kinst instbuf;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3924 after = m68k_decode(inst, &instbuf, orig);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3925 if (orig_size != MAX_NATIVE_SIZE) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3926 if (dst_end - dst < 128) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3927 size_t size = 1024*1024;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3928 dst = alloc_code(&size);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3929 opts->code_end = dst_end = dst + size;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3930 opts->cur_code = dst;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3931 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3932 uint8_t * native_end = translate_m68k(dst, &instbuf, opts);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3933 if ((native_end - dst) <= orig_size) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3934 native_end = translate_m68k(orig_start, &instbuf, opts);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3935 while (native_end < orig_start + orig_size) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3936 *(native_end++) = 0x90; //NOP
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3937 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3938 return orig_start;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3939 } else {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3940 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3941 opts->code_end = dst+MAX_NATIVE_SIZE;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3942 if (instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && instbuf.op != M68K_RTR && instbuf.op != M68K_JMP && (instbuf.op != M68K_BCC \|\| instbuf.extra.cond != COND_TRUE)) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3943 jmp(native_end, get_native_address(context->native_code_map, address + (after-inst)*2));
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3944 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3945 return dst;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3946 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3947 } else {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3948 dst = translate_m68k(orig_start, &instbuf, opts);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3949 if (instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && instbuf.op != M68K_RTR && instbuf.op != M68K_JMP && (instbuf.op != M68K_BCC \|\| instbuf.extra.cond != COND_TRUE)) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3950 dst = jmp(dst, get_native_address(context->native_code_map, address + (after-inst)*2));
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3951 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3952 return orig_start;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3953 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3954 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3955
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3956 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3957 {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3958 uint32_t inst_start = get_instruction_start(context->native_code_map, address \| 0xFF0000);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3959 if (inst_start) {
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3960 uint8_t * dst = get_native_address(context->native_code_map, inst_start);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3961 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3962 dst = jmp(dst, (uint8_t *)m68k_retrans_stub);
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3963 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3964 return context;
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3965 }
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	3966
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3967 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler)
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3968 {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3969 static uint8_t * bp_stub = NULL;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3970 uint8_t * native = get_native_address_trans(context, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3971 uint8_t * start_native = native;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3972 native = mov_ir(native, address, SCRATCH1, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3973 if (!bp_stub) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3974 x86_68k_options * opts = context->options;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3975 uint8_t * dst = opts->cur_code;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3976 uint8_t * dst_end = opts->code_end;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3977 if (dst_end - dst < 128) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3978 size_t size = 1024*1024;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3979 dst = alloc_code(&size);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3980 opts->code_end = dst_end = dst + size;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3981 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3982 bp_stub = dst;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3983 native = call(native, bp_stub);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3984
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3985 //Calculate length of prologue
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3986 dst = check_cycles_int(dst, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3987 int check_int_size = dst-bp_stub;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3988 dst = bp_stub;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3989
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3990 //Save context and call breakpoint handler
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3991 dst = call(dst, (uint8_t *)m68k_save_context);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3992 dst = push_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3993 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3994 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3995 dst = call(dst, bp_handler);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3996 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3997 //Restore context
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3998 dst = call(dst, (uint8_t *)m68k_load_context);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	3999 dst = pop_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4000 //do prologue stuff
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4001 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4002 uint8_t * jmp_off = dst+1;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4003 dst = jcc(dst, CC_NC, dst + 7);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4004 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4005 *jmp_off = dst - (jmp_off+1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4006 //jump back to body of translated instruction
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4007 dst = pop_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4008 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4009 dst = jmp_r(dst, SCRATCH1);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4010 opts->cur_code = dst;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4011 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4012 native = call(native, bp_stub);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4013 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4014 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4015
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4016 void remove_breakpoint(m68k_context * context, uint32_t address)
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4017 {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4018 uint8_t * native = get_native_address(context->native_code_map, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4019 check_cycles_int(native, address);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4020 }
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	4021
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4022 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4023 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4024 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4025 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4026 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4027
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4028 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4029 {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4030 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4031 context->aregs[7] = context->mem_pointers[0][0] << 16 \| context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4032 uint32_t address = context->mem_pointers[0][2] << 16 \| context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	4033 start_68k_context(context, address);
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4034 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	4035
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4036 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4037 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4038 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4039 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4040 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4041 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4042 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4043 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4044 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4045 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4046 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4047 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4048 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4049 opts->deferred = NULL;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4050 size_t size = 1024 * 1024;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4051 opts->cur_code = alloc_code(&size);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	4052 opts->code_end = opts->cur_code + size;
192 1db07e112bf7 Prep work for handling games that modify code in RAM Mike Pavone <pavone@retrodev.com> parents: 188 diff changeset	4053 opts->ram_inst_sizes = malloc(sizeof(uint8_t ) 64);
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 192 diff changeset	4054 memset(opts->ram_inst_sizes, 0, sizeof(uint8_t ) 64);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4055 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4056
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4057 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4058 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4059 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4060 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4061 context->options = opts;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	4062 context->int_cycle = 0xFFFFFFFF;
167 f6c7fea1ecf7 Initialize status register to proper value on startup Mike Pavone <pavone@retrodev.com> parents: 165 diff changeset	4063 context->status = 0x27;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4064 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4065

Mercurial > repos > blastem

annotate m68k_to_x86.c @ 213:4d4559b04c59