Mercurial > repos > blastem
annotate m68k_to_x86.c @ 621:5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 16 Jun 2014 19:13:28 -0700 |
parents | 7f54f1773e84 |
children | c2716b502a81 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_x86.h" |
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7 #include "m68k_to_x86.h" |
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8 #include "68kinst.h" |
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9 #include "mem.h" |
211 | 10 #include "x86_backend.h" |
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11 #include <stdio.h> |
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12 #include <stddef.h> |
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13 #include <stdlib.h> |
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14 #include <string.h> |
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15 |
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16 #define BUS 4 |
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17 #define PREDEC_PENALTY 2 |
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18 #define CYCLES RAX |
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19 #define LIMIT RBP |
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20 #define SCRATCH1 RCX |
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21 #define SCRATCH2 RDI |
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22 #define CONTEXT RSI |
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23 |
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24 #define FLAG_N RBX |
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25 #define FLAG_V BH |
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26 #define FLAG_Z RDX |
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27 #define FLAG_C DH |
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28 |
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29 char disasm_buf[1024]; |
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30 |
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31 m68k_context * sync_components(m68k_context * context, uint32_t address); |
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32 |
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33 void handle_cycle_limit(); |
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34 void m68k_save_context(); |
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35 void m68k_load_context(); |
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36 void m68k_modified_ret_addr(); |
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37 void m68k_native_addr(); |
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38 void m68k_native_addr_and_sync(); |
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39 void m68k_invalid(); |
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40 void m68k_retrans_stub(); |
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41 void set_sr(); |
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42 void set_ccr(); |
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43 void get_sr(); |
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44 void do_sync(); |
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45 void bcd_add(); |
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46 void bcd_sub(); |
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47 void m68k_start_context(uint8_t * addr, m68k_context * context); |
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48 void debug_print_sr(); |
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49 |
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50 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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51 { |
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52 dst = add_ir(dst, num, CYCLES, SZ_D); |
118 | 53 return dst; |
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54 } |
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55 |
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56 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address, x86_68k_options * opts) |
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57 { |
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58 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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59 uint8_t * jmp_off = dst+1; |
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60 dst = jcc(dst, CC_NC, dst + 7); |
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61 dst = mov_ir(dst, address, SCRATCH1, SZ_D); |
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62 dst = call(dst, opts->handle_cycle_limit_int); |
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63 *jmp_off = dst - (jmp_off+1); |
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64 return dst; |
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65 } |
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66 |
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67 uint8_t * check_cycles(uint8_t * dst) |
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68 { |
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69 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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70 uint8_t * jmp_off = dst+1; |
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71 dst = jcc(dst, CC_NC, dst + 7); |
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72 dst = call(dst, (uint8_t *)handle_cycle_limit); |
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73 *jmp_off = dst - (jmp_off+1); |
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74 return dst; |
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75 } |
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76 |
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77 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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78 { |
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79 if (op->addr_mode == MODE_REG) { |
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80 return opts->dregs[op->params.regs.pri]; |
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81 } |
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82 if (op->addr_mode == MODE_AREG) { |
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83 return opts->aregs[op->params.regs.pri]; |
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84 } |
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85 return -1; |
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86 } |
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87 |
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88 //must be called with an m68k_op_info that uses a register |
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89 size_t reg_offset(m68k_op_info *op) |
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90 { |
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91 if (op->addr_mode == MODE_REG) { |
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92 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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93 } |
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94 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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95 } |
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96 |
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97 void print_regs_exit(m68k_context * context) |
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98 { |
207 | 99 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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100 for (int i = 0; i < 8; i++) { |
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101 printf("d%d: %X\n", i, context->dregs[i]); |
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102 } |
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103 for (int i = 0; i < 8; i++) { |
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104 printf("a%d: %X\n", i, context->aregs[i]); |
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105 } |
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106 exit(0); |
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107 } |
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108 |
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109 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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110 { |
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111 int8_t reg = native_reg(&(inst->src), opts); |
81
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112 uint8_t sec_reg; |
18
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113 int32_t dec_amount,inc_amount; |
14
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114 if (reg >= 0) { |
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115 ea->mode = MODE_REG_DIRECT; |
181
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116 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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117 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D); |
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118 ea->base = SCRATCH1; |
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119 } else { |
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120 ea->base = reg; |
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121 } |
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122 return out; |
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123 } |
18
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124 switch (inst->src.addr_mode) |
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125 { |
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126 case MODE_REG: |
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127 case MODE_AREG: |
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128 //We only get one memory parameter, so if the dst operand is a register in memory, |
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129 //we need to copy this to a temp register first |
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130 reg = native_reg(&(inst->dst), opts); |
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131 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) |
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132 || inst->op == M68K_EXG) { |
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133 |
18
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134 ea->mode = MODE_REG_DISPLACE8; |
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135 ea->base = CONTEXT; |
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136 ea->disp = reg_offset(&(inst->src)); |
18
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137 } else { |
181
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138 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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139 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D); |
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140 } else { |
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141 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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142 } |
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143 ea->mode = MODE_REG_DIRECT; |
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144 ea->base = SCRATCH1; |
181
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145 //we're explicitly handling the areg dest here, so we exit immediately |
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146 return out; |
18
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147 } |
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148 break; |
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149 case MODE_AREG_PREDEC: |
216
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150 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 :1)); |
18
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151 out = cycles(out, PREDEC_PENALTY); |
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152 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
158
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153 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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154 } else { |
158
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155 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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156 } |
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157 case MODE_AREG_INDIRECT: |
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158 case MODE_AREG_POSTINC: |
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159 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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160 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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161 } else { |
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162 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
18
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163 } |
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164 switch (inst->extra.size) |
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165 { |
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166 case OPSIZE_BYTE: |
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167 out = call(out, opts->read_8); |
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168 break; |
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169 case OPSIZE_WORD: |
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170 out = call(out, opts->read_16); |
18
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171 break; |
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172 case OPSIZE_LONG: |
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173 out = call(out, opts->read_32); |
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174 break; |
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175 } |
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176 |
18
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177 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
183
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182
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178 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1)); |
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179 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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180 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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181 } else { |
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182 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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183 } |
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184 } |
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185 ea->mode = MODE_REG_DIRECT; |
184
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183
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186 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1; |
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187 break; |
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188 case MODE_AREG_DISPLACE: |
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189 out = cycles(out, BUS); |
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190 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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191 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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192 } else { |
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193 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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194 } |
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195 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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196 switch (inst->extra.size) |
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197 { |
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198 case OPSIZE_BYTE: |
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199 out = call(out, opts->read_8); |
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200 break; |
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201 case OPSIZE_WORD: |
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202 out = call(out, opts->read_16); |
71
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203 break; |
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204 case OPSIZE_LONG: |
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205 out = call(out, opts->read_32); |
71
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206 break; |
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207 } |
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208 ea->mode = MODE_REG_DIRECT; |
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209 ea->base = SCRATCH1; |
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210 break; |
81
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|
211 case MODE_AREG_INDEX_DISP8: |
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|
212 out = cycles(out, 6); |
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213 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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|
214 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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|
215 } else { |
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216 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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|
217 } |
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218 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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219 if (inst->src.params.regs.sec & 1) { |
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|
220 if (inst->src.params.regs.sec & 0x10) { |
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|
221 if (opts->aregs[sec_reg] >= 0) { |
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222 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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223 } else { |
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224 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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|
225 } |
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226 } else { |
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227 if (opts->dregs[sec_reg] >= 0) { |
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228 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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229 } else { |
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230 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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231 } |
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232 } |
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233 } else { |
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234 if (inst->src.params.regs.sec & 0x10) { |
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235 if (opts->aregs[sec_reg] >= 0) { |
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236 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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237 } else { |
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238 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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239 } |
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240 } else { |
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241 if (opts->dregs[sec_reg] >= 0) { |
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242 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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243 } else { |
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244 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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245 } |
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246 } |
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247 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
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248 } |
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249 if (inst->src.params.regs.displacement) { |
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250 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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251 } |
97
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|
252 switch (inst->extra.size) |
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253 { |
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|
254 case OPSIZE_BYTE: |
343
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255 out = call(out, opts->read_8); |
97
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256 break; |
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257 case OPSIZE_WORD: |
343
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258 out = call(out, opts->read_16); |
97
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259 break; |
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260 case OPSIZE_LONG: |
343
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261 out = call(out, opts->read_32); |
97
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|
262 break; |
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|
263 } |
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|
264 ea->mode = MODE_REG_DIRECT; |
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96
diff
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|
265 ea->base = SCRATCH1; |
81
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|
266 break; |
71
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70
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|
267 case MODE_PC_DISPLACE: |
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|
268 out = cycles(out, BUS); |
74
6396dc91f61e
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73
diff
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|
269 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
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70
diff
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|
270 switch (inst->extra.size) |
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|
271 { |
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70
diff
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|
272 case OPSIZE_BYTE: |
343
467bfa17004a
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324
diff
changeset
|
273 out = call(out, opts->read_8); |
71
f80fa1776507
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70
diff
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|
274 break; |
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diff
changeset
|
275 case OPSIZE_WORD: |
343
467bfa17004a
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324
diff
changeset
|
276 out = call(out, opts->read_16); |
71
f80fa1776507
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70
diff
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|
277 break; |
f80fa1776507
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70
diff
changeset
|
278 case OPSIZE_LONG: |
343
467bfa17004a
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324
diff
changeset
|
279 out = call(out, opts->read_32); |
71
f80fa1776507
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70
diff
changeset
|
280 break; |
f80fa1776507
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70
diff
changeset
|
281 } |
f80fa1776507
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diff
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|
282 ea->mode = MODE_REG_DIRECT; |
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70
diff
changeset
|
283 ea->base = SCRATCH1; |
f80fa1776507
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70
diff
changeset
|
284 break; |
81
6d231dbe75ab
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78
diff
changeset
|
285 case MODE_PC_INDEX_DISP8: |
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78
diff
changeset
|
286 out = cycles(out, 6); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
287 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
288 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
6d231dbe75ab
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diff
changeset
|
289 if (inst->src.params.regs.sec & 1) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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diff
changeset
|
290 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
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78
diff
changeset
|
291 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
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78
diff
changeset
|
292 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
293 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
294 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
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78
diff
changeset
|
295 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
296 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
297 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
298 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
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78
diff
changeset
|
299 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
300 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
301 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
302 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
303 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
304 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
305 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
306 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
307 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
308 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
309 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
310 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
311 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
312 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
313 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
314 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
315 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
316 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
317 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
318 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
319 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
320 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
321 } |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
322 switch (inst->extra.size) |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
323 { |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
324 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
325 out = call(out, opts->read_8); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
326 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
327 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
328 out = call(out, opts->read_16); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
329 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
330 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
331 out = call(out, opts->read_32); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
332 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
333 } |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
334 ea->mode = MODE_REG_DIRECT; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
335 ea->base = SCRATCH1; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
336 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
337 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
338 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
339 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
340 out = cycles(out, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
341 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
342 out = cycles(out, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
343 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
344 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
345 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
346 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
347 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
348 out = call(out, opts->read_8); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
349 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
350 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
351 out = call(out, opts->read_16); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
352 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
353 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
354 out = call(out, opts->read_32); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
355 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
356 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
357 ea->mode = MODE_REG_DIRECT; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
358 ea->base = SCRATCH1; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
359 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
360 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
361 case MODE_IMMEDIATE_WORD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
362 if (inst->variant != VAR_QUICK) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
363 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
364 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
365 ea->mode = MODE_IMMED; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
366 ea->disp = inst->src.params.immed; |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
367 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
368 ea->disp |= 0xFFFF0000; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
369 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
370 return out; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
371 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
372 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
373 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
374 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
375 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
376 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
377 if (ea->mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
378 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
379 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
380 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
381 ea->mode = MODE_REG_DIRECT; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
382 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
383 ea->base = SCRATCH1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
384 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
385 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
386 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
387 |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
388 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
389 { |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
390 int8_t reg = native_reg(&(inst->dst), opts), sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
391 int32_t dec_amount, inc_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
392 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
393 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
394 ea->base = reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
395 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
396 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
397 switch (inst->dst.addr_mode) |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
398 { |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 case MODE_REG: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 case MODE_AREG: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
401 ea->mode = MODE_REG_DISPLACE8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
402 ea->base = CONTEXT; |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
403 ea->disp = reg_offset(&(inst->dst)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
404 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
405 case MODE_AREG_PREDEC: |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
406 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
407 out = push_r(out, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
408 } |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
409 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
410 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
411 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
412 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
413 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
414 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
415 case MODE_AREG_INDIRECT: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
416 case MODE_AREG_POSTINC: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
417 if (fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
418 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
419 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
420 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
421 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
422 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
423 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
424 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
425 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
426 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
427 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
428 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
429 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
430 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
431 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
432 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
433 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
434 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
435 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
436 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
437 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
438 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
439 //restore src operand to SCRATCH2 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
440 out =pop_r(out, SCRATCH2); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
441 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
442 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
443 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
444 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
445 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
446 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
447 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
448 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
449 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
450 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
451 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
452 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
453 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
454 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
455 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
456 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
457 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
458 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
459 ea->base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
460 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
461 case MODE_AREG_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
462 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
463 reg = fake_read ? SCRATCH2 : SCRATCH1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
464 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
465 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
466 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
467 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
468 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
469 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
470 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
471 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
472 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
473 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
474 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
475 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
476 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
477 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
478 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
479 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
480 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
481 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
482 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
483 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
484 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
485 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
486 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
487 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
488 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
489 case MODE_AREG_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
490 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
491 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
492 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
493 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
494 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
495 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
496 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
497 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
498 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
499 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
500 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
501 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
502 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
503 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
504 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
505 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
506 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
507 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
508 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
509 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
510 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
511 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
512 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
513 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
514 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
515 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
516 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
517 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
518 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
519 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
520 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
521 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
522 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
523 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
524 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
525 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
526 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
527 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
528 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
529 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
530 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
531 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
532 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
533 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
534 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
535 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
536 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
537 out = call(out, opts->read_8); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
538 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
539 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
540 out = call(out, opts->read_16); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
541 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
542 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
543 out = call(out, opts->read_32); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
544 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
545 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
546 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
547 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
548 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
549 ea->base = SCRATCH1; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
550 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
551 case MODE_PC_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
552 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
553 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
554 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
555 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
556 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
557 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
558 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
559 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
560 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
561 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
562 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
563 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
564 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
565 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
566 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
567 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
568 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
569 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
570 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
571 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
572 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
573 case MODE_PC_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
574 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
575 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
576 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
577 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
578 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
579 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
580 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
581 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
582 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
583 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
584 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
585 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
586 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
587 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
588 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
589 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
590 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
591 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
592 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
593 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
594 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
595 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
596 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
597 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
598 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
599 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
600 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
601 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
602 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
603 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
604 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
605 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
606 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
607 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
608 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
609 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
610 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
611 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
612 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
613 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
614 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
615 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
616 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
617 out = call(out, opts->read_8); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
618 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
619 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
620 out = call(out, opts->read_16); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
621 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
622 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
623 out = call(out, opts->read_32); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
624 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
625 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
626 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
627 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
628 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
629 ea->base = SCRATCH1; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
630 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
631 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
632 case MODE_ABSOLUTE_SHORT: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
633 //Add cycles for reading address from instruction stream |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
634 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0)); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
635 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
636 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
637 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
638 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
639 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
640 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
641 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
642 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
643 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
644 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
645 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
646 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
647 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
648 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
649 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
650 out = pop_r(out, SCRATCH2); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
651 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
652 ea->mode = MODE_REG_DIRECT; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
653 ea->base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
654 break; |
18
3e7bfde7606e
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parents:
14
diff
changeset
|
655 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
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parents:
150
diff
changeset
|
656 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
657 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
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14
diff
changeset
|
658 exit(1); |
3e7bfde7606e
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14
diff
changeset
|
659 } |
3e7bfde7606e
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diff
changeset
|
660 return out; |
3e7bfde7606e
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parents:
14
diff
changeset
|
661 } |
3e7bfde7606e
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diff
changeset
|
662 |
3e7bfde7606e
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diff
changeset
|
663 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
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parents:
14
diff
changeset
|
664 { |
3e7bfde7606e
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diff
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|
665 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
changeset
|
666 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
changeset
|
667 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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183
diff
changeset
|
668 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
changeset
|
669 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
changeset
|
670 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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183
diff
changeset
|
671 } |
ebcbdd1c4cc8
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183
diff
changeset
|
672 } |
18
3e7bfde7606e
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14
diff
changeset
|
673 switch (inst->extra.size) |
3e7bfde7606e
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parents:
14
diff
changeset
|
674 { |
3e7bfde7606e
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diff
changeset
|
675 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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324
diff
changeset
|
676 out = call(out, opts->write_8); |
18
3e7bfde7606e
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14
diff
changeset
|
677 break; |
3e7bfde7606e
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14
diff
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|
678 case OPSIZE_WORD: |
343
467bfa17004a
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324
diff
changeset
|
679 out = call(out, opts->write_16); |
18
3e7bfde7606e
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parents:
14
diff
changeset
|
680 break; |
3e7bfde7606e
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14
diff
changeset
|
681 case OPSIZE_LONG: |
343
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324
diff
changeset
|
682 out = call(out, opts->write_32_lowfirst); |
18
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
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14
diff
changeset
|
683 break; |
3e7bfde7606e
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14
diff
changeset
|
684 } |
3e7bfde7606e
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parents:
14
diff
changeset
|
685 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
686 return out; |
3e7bfde7606e
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parents:
14
diff
changeset
|
687 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
688 |
3e7bfde7606e
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parents:
14
diff
changeset
|
689 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
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parents:
14
diff
changeset
|
690 { |
3e7bfde7606e
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14
diff
changeset
|
691 address &= 0xFFFFFF; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
692 address /= 2; |
18
3e7bfde7606e
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parents:
14
diff
changeset
|
693 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
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parents:
14
diff
changeset
|
694 if (!native_code_map[chunk].base) { |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
695 return NULL; |
3e7bfde7606e
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14
diff
changeset
|
696 } |
3e7bfde7606e
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diff
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|
697 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
193
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diff
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|
698 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
18
3e7bfde7606e
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parents:
14
diff
changeset
|
699 return NULL; |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
700 } |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
701 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
702 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
703 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
704 uint8_t * get_native_from_context(m68k_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
705 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
706 return get_native_address(context->native_code_map, address); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
707 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
708 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
709 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
710 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
711 address &= 0xFFFFFF; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
712 address /= 2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
713 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
714 if (!native_code_map[chunk].base) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
715 return 0; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
716 } |
c66e4636f991
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parents:
192
diff
changeset
|
717 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
718 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
719 return 0; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
720 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
721 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
722 --address; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
723 chunk = address / NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
724 offset = address % NATIVE_CHUNK_SIZE; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
725 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
726 return address*2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
727 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
728 |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
729 void map_native_address(m68k_context * context, uint32_t address, uint8_t * native_addr, uint8_t size, uint8_t native_size) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
730 { |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
731 native_map_slot * native_code_map = context->native_code_map; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
732 x86_68k_options * opts = context->options; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
733 address &= 0xFFFFFF; |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
734 if (address > 0xE00000) { |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
735 context->ram_code_flags[(address & 0xC000) >> 14] |= 1 << ((address & 0x3800) >> 11); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
736 if (((address & 0x3FFF) + size) & 0xC000) { |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
737 context->ram_code_flags[((address+size) & 0xC000) >> 14] |= 1 << (((address+size) & 0x3800) >> 11); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
738 } |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
739 uint32_t slot = (address & 0xFFFF)/1024; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
740 if (!opts->ram_inst_sizes[slot]) { |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
741 opts->ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
742 } |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
743 opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
744 } |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
745 address/= 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
746 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
747 if (!native_code_map[chunk].base) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
748 native_code_map[chunk].base = native_addr; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
749 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
750 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
751 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
752 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
753 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
193
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Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
754 for(address++,size-=2; size; address++,size-=2) { |
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parents:
192
diff
changeset
|
755 chunk = address / NATIVE_CHUNK_SIZE; |
c66e4636f991
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parents:
192
diff
changeset
|
756 offset = address % NATIVE_CHUNK_SIZE; |
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parents:
192
diff
changeset
|
757 if (!native_code_map[chunk].base) { |
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parents:
192
diff
changeset
|
758 native_code_map[chunk].base = native_addr; |
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parents:
192
diff
changeset
|
759 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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Implement support for self-modifying code
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parents:
192
diff
changeset
|
760 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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Implement support for self-modifying code
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parents:
192
diff
changeset
|
761 } |
c66e4636f991
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Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
762 native_code_map[chunk].offsets[offset] = EXTENSION_WORD; |
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Implement support for self-modifying code
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parents:
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diff
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|
763 } |
c66e4636f991
Implement support for self-modifying code
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parents:
192
diff
changeset
|
764 } |
c66e4636f991
Implement support for self-modifying code
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192
diff
changeset
|
765 |
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Implement support for self-modifying code
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diff
changeset
|
766 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address) |
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parents:
192
diff
changeset
|
767 { |
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192
diff
changeset
|
768 if (address < 0xE00000) { |
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Implement support for self-modifying code
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192
diff
changeset
|
769 return 0; |
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Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
770 } |
c66e4636f991
Implement support for self-modifying code
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parents:
192
diff
changeset
|
771 uint32_t slot = (address & 0xFFFF)/1024; |
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Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
772 return opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512]; |
18
3e7bfde7606e
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parents:
14
diff
changeset
|
773 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
774 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
775 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
776 { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
777 int8_t reg, flags_reg, sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
778 uint8_t dir = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
779 int32_t offset; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
780 int32_t inc_amount, dec_amount; |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
781 x86_ea src; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
782 dst = translate_m68k_src(inst, &src, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
783 reg = native_reg(&(inst->dst), opts); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
784 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
785 //update statically set flags |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
786 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
787 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
788 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
789 |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
790 if (inst->dst.addr_mode != MODE_AREG) { |
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Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
791 if (src.mode == MODE_REG_DIRECT) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
792 flags_reg = src.base; |
18
3e7bfde7606e
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parents:
14
diff
changeset
|
793 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
794 if (reg >= 0) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
795 flags_reg = reg; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
796 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
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parents:
213
diff
changeset
|
797 if(src.mode == MODE_REG_DISPLACE8) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
798 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
799 } else { |
0b5ec22dcda2
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Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
800 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
801 } |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
802 src.mode = MODE_REG_DIRECT; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
803 flags_reg = src.base = SCRATCH1; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
804 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
805 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
806 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
807 uint8_t size = inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
808 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
809 { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
810 case MODE_AREG: |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
811 size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
812 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
813 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
814 if (src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
815 dst = mov_rr(dst, src.base, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
816 } else if (src.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
817 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
818 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
819 dst = mov_ir(dst, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
820 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
821 } else if(src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
822 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
823 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
824 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
825 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
826 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
827 dst = cmp_ir(dst, 0, flags_reg, size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
828 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
829 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
830 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
832 case MODE_AREG_PREDEC: |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
833 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
834 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
835 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
836 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
837 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
838 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
840 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
841 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
842 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
843 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
844 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
845 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
846 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
847 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
848 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
849 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
850 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
851 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
852 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
853 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
854 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
855 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
856 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
857 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
858 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
859 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
860 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
861 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
862 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
863 dst = call(dst, opts->write_8); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
864 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
865 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
866 dst = call(dst, opts->write_16); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
867 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
868 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
869 dst = call(dst, opts->write_32_highfirst); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
870 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
871 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
872 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
873 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
874 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
875 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
876 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
877 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
878 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
879 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
881 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
882 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
883 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
884 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
885 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
886 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
887 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
888 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
889 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
890 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
891 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
892 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
893 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
894 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
895 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
896 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
897 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
898 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
899 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
900 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
901 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
902 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
903 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
904 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
905 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
906 dst = call(dst, opts->write_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
907 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
908 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
909 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
910 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
911 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
912 dst = call(dst, opts->write_32_highfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
913 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
914 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
915 break; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
916 case MODE_AREG_INDEX_DISP8: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
917 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
918 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
919 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
920 } else { |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
921 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
922 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
923 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
924 if (inst->dst.params.regs.sec & 1) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
925 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
926 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
927 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
928 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
929 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
930 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
931 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
932 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
933 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
934 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
935 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
936 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
937 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
938 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
939 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
940 dst = push_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
941 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
942 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
943 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
944 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
945 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
946 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
947 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
948 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
949 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
950 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
951 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
952 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
953 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
954 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
955 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
956 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
957 dst = pop_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
958 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
959 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
960 if (inst->dst.params.regs.displacement) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
961 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
962 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
963 if (src.mode == MODE_REG_DIRECT) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
964 if (src.base != SCRATCH1) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
965 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
966 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
967 } else if (src.mode == MODE_REG_DISPLACE8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
968 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
969 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
970 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
971 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
972 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
973 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
974 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
975 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
976 } |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
977 switch (inst->extra.size) |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
978 { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
979 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
980 dst = call(dst, opts->write_8); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
981 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
982 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
983 dst = call(dst, opts->write_16); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
984 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
985 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
986 dst = call(dst, opts->write_32_highfirst); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
987 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
988 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
989 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
990 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
991 dst = cycles(dst, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
992 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
993 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
994 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
995 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
996 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
997 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
998 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
999 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1000 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1001 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1002 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1003 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1004 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1005 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1006 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1007 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1008 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1009 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1010 dst = call(dst, opts->write_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1011 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1012 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1013 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1014 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1015 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1016 dst = call(dst, opts->write_32_highfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1017 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1018 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1019 break; |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1020 case MODE_PC_INDEX_DISP8: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1021 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1022 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1023 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1024 if (inst->dst.params.regs.sec & 1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1025 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1026 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1027 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1028 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1029 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1030 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1031 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1032 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1033 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1034 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1035 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1036 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1037 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1038 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1039 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1040 dst = push_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1041 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1042 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1043 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1044 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1045 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1046 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1047 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1048 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1049 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1050 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1051 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1052 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1053 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1054 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1055 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1056 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1057 dst = pop_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1058 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1059 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1060 if (inst->dst.params.regs.displacement) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1061 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1062 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1063 if (src.mode == MODE_REG_DIRECT) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1064 if (src.base != SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1065 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1066 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1067 } else if (src.mode == MODE_REG_DISPLACE8) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1068 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1069 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1070 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1071 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1072 if (inst->dst.addr_mode != MODE_AREG) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1073 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1074 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1075 dst = setcc_r(dst, CC_S, FLAG_N); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1076 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1077 switch (inst->extra.size) |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1078 { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1079 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1080 dst = call(dst, opts->write_8); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1081 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1082 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1083 dst = call(dst, opts->write_16); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1084 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1085 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1086 dst = call(dst, opts->write_32_highfirst); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1087 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1088 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1089 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1090 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1091 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1092 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1093 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1094 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
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parents:
53
diff
changeset
|
1095 } |
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parents:
53
diff
changeset
|
1096 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1097 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1098 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1099 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
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Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1100 } |
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parents:
53
diff
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|
1101 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
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Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1102 dst = cycles(dst, BUS*2); |
3b79cbcf6846
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parents:
53
diff
changeset
|
1103 } else { |
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parents:
53
diff
changeset
|
1104 dst = cycles(dst, BUS); |
3b79cbcf6846
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53
diff
changeset
|
1105 } |
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53
diff
changeset
|
1106 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1107 if (inst->dst.addr_mode != MODE_AREG) { |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1108 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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183
diff
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|
1109 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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parents:
183
diff
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|
1110 dst = setcc_r(dst, CC_S, FLAG_N); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
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|
1111 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1112 switch (inst->extra.size) |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1113 { |
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Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1114 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1115 dst = call(dst, opts->write_8); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1116 break; |
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parents:
53
diff
changeset
|
1117 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1118 dst = call(dst, opts->write_16); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1119 break; |
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Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1120 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1121 dst = call(dst, opts->write_32_highfirst); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1122 break; |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1123 } |
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Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1124 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1125 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1126 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1127 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1128 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1130 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1131 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1132 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1133 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1134 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1135 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1136 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1137 { |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1138 int8_t bit,reg,sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1139 uint8_t early_cycles; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1140 if(inst->src.addr_mode == MODE_REG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1141 //reg to mem |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1142 early_cycles = 8; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1143 int8_t dir; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1144 switch (inst->dst.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1145 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1146 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1147 case MODE_AREG_PREDEC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1148 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1149 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1150 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1151 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1152 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1153 break; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1154 case MODE_AREG_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1155 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1156 reg = SCRATCH2; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1157 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1158 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1159 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1160 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1161 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1162 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1163 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1164 case MODE_AREG_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1165 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1166 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1167 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1168 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1169 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1170 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1171 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1172 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1173 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1174 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1175 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1176 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1177 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1178 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1179 } else { |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1180 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1181 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1182 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1183 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1184 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1185 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1186 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1187 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1188 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1189 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1190 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1191 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1192 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1193 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1194 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1195 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1196 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1197 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1198 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1199 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1200 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1201 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1202 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1203 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1204 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1205 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1206 case MODE_PC_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1207 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1208 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1209 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1210 case MODE_PC_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1211 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1212 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1213 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1214 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1215 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1216 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1217 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1218 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1219 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1220 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1221 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1222 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1223 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1224 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1225 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1226 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1227 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1228 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1229 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1230 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1231 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1232 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1233 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1234 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1235 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1236 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1237 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1238 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1239 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1240 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1241 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1242 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1243 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1244 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1245 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1246 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1247 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1248 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1249 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1250 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1251 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1252 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1253 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1254 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1255 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1256 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1257 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1258 } |
210
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1259 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1260 reg = 15; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1261 dir = -1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1262 } else { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1263 reg = 0; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1264 dir = 1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1265 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1266 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1267 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1268 if (inst->src.params.immed & (1 << bit)) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1269 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1270 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1271 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1272 dst = push_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1273 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1274 if (opts->aregs[reg-8] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1275 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1276 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1277 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1278 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1279 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1280 if (opts->dregs[reg] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1281 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1282 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1283 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1284 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1285 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1286 if (inst->extra.size == OPSIZE_LONG) { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1287 dst = call(dst, opts->write_32_lowfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1288 } else { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1289 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1290 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1291 dst = pop_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1292 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1293 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1294 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1295 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1296 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1297 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1298 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1299 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1300 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1301 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1302 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1303 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1304 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1305 //mem to reg |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1306 early_cycles = 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1307 switch (inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1308 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1309 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1310 case MODE_AREG_POSTINC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1311 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1312 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1313 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1314 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1315 } |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1316 break; |
162
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1317 case MODE_AREG_DISPLACE: |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1318 early_cycles += BUS; |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1319 reg = SCRATCH2; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1320 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1321 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1322 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1323 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1324 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1325 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1326 break; |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1327 case MODE_AREG_INDEX_DISP8: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1328 early_cycles += 6; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1329 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1330 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1331 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1332 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1333 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1334 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1335 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1336 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1337 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1338 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1339 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1340 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1341 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1342 } else { |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1343 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1344 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1345 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1346 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1347 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1348 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1349 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1350 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1351 if (opts->aregs[sec_reg] >= 0) { |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1352 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1353 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1354 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1355 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1356 } else { |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1357 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1358 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1359 } else { |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1360 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1361 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1362 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1363 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1364 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1365 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1366 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1367 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1368 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1369 case MODE_PC_DISPLACE: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1370 early_cycles += BUS; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1371 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1372 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1373 case MODE_PC_INDEX_DISP8: |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1374 early_cycles += 6; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1375 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1376 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1377 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1378 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1379 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1380 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1381 } else { |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1382 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
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parents:
161
diff
changeset
|
1383 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1384 } else { |
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parents:
161
diff
changeset
|
1385 if (opts->dregs[sec_reg] >= 0) { |
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1386 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1387 } else { |
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Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
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161
diff
changeset
|
1388 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1389 } |
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1390 } |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1391 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1392 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1393 if (opts->aregs[sec_reg] >= 0) { |
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161
diff
changeset
|
1394 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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parents:
161
diff
changeset
|
1395 } else { |
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161
diff
changeset
|
1396 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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parents:
161
diff
changeset
|
1397 } |
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parents:
161
diff
changeset
|
1398 } else { |
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161
diff
changeset
|
1399 if (opts->dregs[sec_reg] >= 0) { |
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parents:
161
diff
changeset
|
1400 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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parents:
161
diff
changeset
|
1401 } else { |
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161
diff
changeset
|
1402 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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parents:
161
diff
changeset
|
1403 } |
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parents:
161
diff
changeset
|
1404 } |
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161
diff
changeset
|
1405 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
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161
diff
changeset
|
1406 } |
169
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Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1407 if (inst->src.params.regs.displacement) { |
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Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1408 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
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Implement more movem modes src
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161
diff
changeset
|
1409 } |
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parents:
161
diff
changeset
|
1410 break; |
71
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1411 case MODE_ABSOLUTE: |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1412 early_cycles += 4; |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1413 case MODE_ABSOLUTE_SHORT: |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1414 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
1415 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1416 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1417 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1418 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1419 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1420 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1421 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1422 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1423 for(reg = 0; reg < 16; reg ++) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1424 if (inst->dst.params.immed & (1 << reg)) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1425 dst = push_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1426 if (inst->extra.size == OPSIZE_LONG) { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1427 dst = call(dst, opts->read_32); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1428 } else { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1429 dst = call(dst, opts->read_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1430 } |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1431 if (inst->extra.size == OPSIZE_WORD) { |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1432 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1433 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1434 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1435 if (opts->aregs[reg-8] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1436 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1437 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1438 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1439 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1440 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1441 if (opts->dregs[reg] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1442 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1443 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1444 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1445 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1446 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1447 dst = pop_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1448 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1449 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1450 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1451 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1452 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1453 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1454 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1455 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1456 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1457 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1458 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1459 //prefetch |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1460 dst = cycles(dst, 4); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1461 return dst; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1462 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1463 |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1464 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1465 { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1466 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1467 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1468 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1469 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1470 int8_t reg = native_reg(&(inst->dst), opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1471 if (reg >= 0) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1472 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1473 return xor_rr(dst, reg, reg, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1474 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1475 x86_ea dst_op; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1476 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1477 if (dst_op.mode == MODE_REG_DIRECT) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1478 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1479 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1480 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1481 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1482 dst = m68k_save_result(inst, dst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1483 return dst; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1484 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1485 |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1486 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1487 { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1488 x86_ea dst_op; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1489 uint8_t dst_size = inst->extra.size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1490 inst->extra.size--; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1491 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1492 if (dst_op.mode == MODE_REG_DIRECT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1493 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1494 dst = cmp_ir(dst, 0, dst_op.base, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1495 } else { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1496 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1497 dst = cmp_ir(dst, 0, SCRATCH1, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1498 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1499 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1500 inst->extra.size = dst_size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1501 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1502 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1503 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1504 dst = setcc_r(dst, CC_S, FLAG_N); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1505 //M68K EXT only operates on registers so no need for a call to save result here |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1506 return dst; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1507 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1508 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1509 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1510 { |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1511 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1512 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1513 { |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1514 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1515 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1516 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1517 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1518 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1519 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1520 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1521 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1522 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1523 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1524 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1525 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1526 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1527 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1528 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1529 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1530 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1531 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1532 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1533 if (dst_reg >= 0) { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1534 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1535 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1536 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1537 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1538 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1539 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1540 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1541 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1542 } else { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1543 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1544 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1545 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1546 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1547 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1548 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1549 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1550 } |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1551 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1552 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1553 break; |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1554 case MODE_AREG_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1555 dst = cycles(dst, 12); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1556 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1557 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1558 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1559 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1560 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1561 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1562 if (inst->src.params.regs.sec & 1) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1563 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1564 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1565 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1566 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1567 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1568 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1569 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1570 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1571 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1572 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1573 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1574 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1575 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1576 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1577 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1578 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1579 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1580 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1581 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1582 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1583 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1584 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1585 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1586 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1587 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1588 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1589 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1590 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1591 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1592 if (inst->src.params.regs.displacement) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1593 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1594 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1595 if (dst_reg >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1596 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1597 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1598 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1599 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1600 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1601 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1602 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1603 if (dst_reg >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1604 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1605 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1606 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1607 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1608 break; |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1609 case MODE_PC_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1610 dst = cycles(dst, BUS*3); |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1611 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1612 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1613 if (inst->src.params.regs.sec & 1) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1614 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1615 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1616 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1617 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1618 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1619 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1620 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1621 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1622 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1623 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1624 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1625 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1626 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1627 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1628 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1629 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1630 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1631 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1632 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1633 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1634 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1635 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1636 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1637 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1638 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1639 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1640 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1641 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1642 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1643 if (inst->src.params.regs.displacement) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1644 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1645 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1646 if (dst_reg >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1647 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1648 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1649 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1650 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1651 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1652 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1653 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1654 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1655 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1656 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1657 } else { |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1658 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1659 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1660 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1661 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1662 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1663 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1664 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1665 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1666 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1667 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1668 |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1669 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1670 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1671 uint8_t sec_reg; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1672 switch(inst->src.addr_mode) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1673 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1674 case MODE_AREG_INDIRECT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1675 dst = cycles(dst, BUS); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1676 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1677 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1678 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1679 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1680 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1681 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1682 case MODE_AREG_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1683 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1684 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1685 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1686 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1687 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1688 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1689 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1690 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1691 case MODE_AREG_INDEX_DISP8: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1692 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1693 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1694 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1695 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1696 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1697 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1698 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1699 if (inst->src.params.regs.sec & 1) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1700 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1701 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1702 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1703 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1704 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1705 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1706 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1707 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1708 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1709 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1710 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1711 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1712 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1713 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1714 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1715 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1716 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1717 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1718 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1719 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1720 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1721 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1722 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1723 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1724 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1725 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1726 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1727 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1728 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1729 if (inst->src.params.regs.displacement) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1730 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1731 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1732 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1733 case MODE_PC_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1734 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1735 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1736 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1737 case MODE_ABSOLUTE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1738 case MODE_ABSOLUTE_SHORT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1739 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1740 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1741 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1742 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1743 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1744 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1745 exit(1); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1746 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1747 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1748 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1749 dst = call(dst, opts->write_32_lowfirst); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1750 return dst; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1751 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1752 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1753 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1754 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1755 int32_t disp = inst->src.params.immed; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1756 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1757 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1758 dst = cycles(dst, 10); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1759 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1760 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1761 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1762 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1763 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1764 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1765 dst = call(dst, opts->write_32_highfirst); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1766 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1767 if (!dest_addr) { |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1768 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1769 //dummy address to be replaced later |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1770 dest_addr = dst + 256; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1771 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1772 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1773 dst = call(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1774 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1775 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1776 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1777 dst = jmp(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1778 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1779 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1780 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1781 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1782 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1783 { |
156
3900cfde9dbb
Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Mike Pavone <pavone@retrodev.com>
parents:
155
diff
changeset
|
1784 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1785 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1786 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1787 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1788 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1789 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1790 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1791 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1792 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1793 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1794 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1795 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1796 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1797 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1798 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1799 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1800 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1801 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1802 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1803 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1804 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1805 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1806 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1807 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1808 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1809 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1810 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1811 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1812 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1813 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1814 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1815 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1816 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1817 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1818 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1819 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1820 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1821 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1822 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1823 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1824 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1825 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1826 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1827 case COND_LESS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1828 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1829 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1830 case COND_GREATER: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1831 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1832 case COND_LESS_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1833 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1834 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1835 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1836 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1837 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1838 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1839 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1840 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1841 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1842 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1843 dst = jcc(dst, cond, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1844 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1845 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1846 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1847 |
112 | 1848 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
1849 { | |
1850 uint8_t cond = inst->extra.cond; | |
1851 x86_ea dst_op; | |
1852 inst->extra.size = OPSIZE_BYTE; | |
1853 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); | |
1854 if (cond == COND_TRUE || cond == COND_FALSE) { | |
1855 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) { | |
1856 dst = cycles(dst, 6); | |
1857 } else { | |
1858 dst = cycles(dst, BUS); | |
1859 } | |
1860 if (dst_op.mode == MODE_REG_DIRECT) { | |
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1861 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B); |
112 | 1862 } else { |
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1863 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1864 } |
1865 } else { | |
1866 uint8_t cc = CC_NZ; | |
1867 switch (cond) | |
1868 { | |
1869 case COND_HIGH: | |
1870 cc = CC_Z; | |
1871 case COND_LOW_SAME: | |
1872 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1873 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); | |
1874 break; | |
1875 case COND_CARRY_CLR: | |
1876 cc = CC_Z; | |
1877 case COND_CARRY_SET: | |
1878 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); | |
1879 break; | |
1880 case COND_NOT_EQ: | |
1881 cc = CC_Z; | |
1882 case COND_EQ: | |
1883 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); | |
1884 break; | |
1885 case COND_OVERF_CLR: | |
1886 cc = CC_Z; | |
1887 case COND_OVERF_SET: | |
1888 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); | |
1889 break; | |
1890 case COND_PLUS: | |
1891 cc = CC_Z; | |
1892 case COND_MINUS: | |
1893 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); | |
1894 break; | |
1895 case COND_GREATER_EQ: | |
1896 cc = CC_Z; | |
1897 case COND_LESS: | |
1898 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); | |
1899 break; | |
1900 case COND_GREATER: | |
1901 cc = CC_Z; | |
1902 case COND_LESS_EQ: | |
1903 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); | |
1904 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); | |
1905 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1906 break; | |
1907 } | |
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1908 uint8_t *true_off = dst + 1; |
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1909 dst = jcc(dst, cc, dst+2); |
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1910 dst = cycles(dst, BUS); |
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1911 if (dst_op.mode == MODE_REG_DIRECT) { |
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1912 dst = mov_ir(dst, 0, dst_op.base, SZ_B); |
112 | 1913 } else { |
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1914 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1915 } |
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1916 uint8_t *end_off = dst+1; |
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1917 dst = jmp(dst, dst+2); |
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1918 *true_off = dst - (true_off+1); |
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1919 dst = cycles(dst, 6); |
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1920 if (dst_op.mode == MODE_REG_DIRECT) { |
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1921 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B); |
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1922 } else { |
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1923 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B); |
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1924 } |
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1925 *end_off = dst - (end_off+1); |
112 | 1926 } |
1927 dst = m68k_save_result(inst, dst, opts); | |
1928 return dst; | |
1929 } | |
1930 | |
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1931 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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1932 { |
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1933 uint8_t * dest_addr, sec_reg; |
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1934 uint32_t m68k_addr; |
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1935 switch(inst->src.addr_mode) |
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1936 { |
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1937 case MODE_AREG_INDIRECT: |
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1938 dst = cycles(dst, BUS*2); |
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1939 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1940 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1941 } else { |
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1942 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
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1943 } |
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1944 dst = call(dst, (uint8_t *)m68k_native_addr); |
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1945 dst = jmp_r(dst, SCRATCH1); |
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1946 break; |
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1947 case MODE_AREG_INDEX_DISP8: |
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1948 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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1949 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1950 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1951 } else { |
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1952 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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1953 } |
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1954 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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1955 if (inst->src.params.regs.sec & 1) { |
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1956 //32-bit index register |
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1957 if (inst->src.params.regs.sec & 0x10) { |
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1958 if (opts->aregs[sec_reg] >= 0) { |
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1959 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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1960 } else { |
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1961 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1962 } |
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1963 } else { |
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1964 if (opts->dregs[sec_reg] >= 0) { |
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1965 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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1966 } else { |
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1967 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1968 } |
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1969 } |
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1970 } else { |
516
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1971 //16-bit index register |
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1972 if (inst->src.params.regs.sec & 0x10) { |
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1973 if (opts->aregs[sec_reg] >= 0) { |
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1974 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1975 } else { |
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1976 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1977 } |
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1978 } else { |
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1979 if (opts->dregs[sec_reg] >= 0) { |
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1980 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1981 } else { |
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1982 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1983 } |
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1984 } |
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1985 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
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1986 } |
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1987 if (inst->src.params.regs.displacement) { |
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1988 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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1989 } |
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1990 dst = call(dst, (uint8_t *)m68k_native_addr); |
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1991 dst = jmp_r(dst, SCRATCH1); |
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1992 break; |
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1993 case MODE_PC_DISPLACE: |
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1994 dst = cycles(dst, 10); |
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1995 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
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1996 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
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1997 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
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1998 if (!dest_addr) { |
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1999 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
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2000 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
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2001 dest_addr = dst + 256; |
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2002 } |
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2003 dst = jmp(dst, dest_addr); |
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2004 } else { |
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2005 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
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2006 dst = call(dst, (uint8_t *)m68k_native_addr); |
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2007 dst = jmp_r(dst, SCRATCH1); |
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2008 } |
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2009 break; |
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2010 case MODE_PC_INDEX_DISP8: |
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2011 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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diff
changeset
|
2012 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
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129
diff
changeset
|
2013 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
0969d8363a20
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parents:
129
diff
changeset
|
2014 if (inst->src.params.regs.sec & 1) { |
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129
diff
changeset
|
2015 if (inst->src.params.regs.sec & 0x10) { |
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129
diff
changeset
|
2016 if (opts->aregs[sec_reg] >= 0) { |
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129
diff
changeset
|
2017 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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129
diff
changeset
|
2018 } else { |
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129
diff
changeset
|
2019 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
0969d8363a20
Support more address modes for jmp
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129
diff
changeset
|
2020 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2021 } else { |
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129
diff
changeset
|
2022 if (opts->dregs[sec_reg] >= 0) { |
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Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2023 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
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|
2024 } else { |
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129
diff
changeset
|
2025 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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Support more address modes for jmp
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129
diff
changeset
|
2026 } |
0969d8363a20
Support more address modes for jmp
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parents:
129
diff
changeset
|
2027 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2028 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2029 if (inst->src.params.regs.sec & 0x10) { |
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parents:
129
diff
changeset
|
2030 if (opts->aregs[sec_reg] >= 0) { |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2031 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2032 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2033 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2034 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2035 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2036 if (opts->dregs[sec_reg] >= 0) { |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2037 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2038 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2039 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2040 } |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2041 } |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2042 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2043 } |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
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129
diff
changeset
|
2044 if (inst->src.params.regs.displacement) { |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2045 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2046 } |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2047 dst = call(dst, (uint8_t *)m68k_native_addr); |
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2048 dst = jmp_r(dst, SCRATCH1); |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2049 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2050 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2051 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2052 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2053 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2054 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2055 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2056 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2057 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2058 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2059 dest_addr = dst + 256; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2060 } |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2061 dst = jmp(dst, dest_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2062 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2063 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2064 dst = call(dst, (uint8_t *)m68k_native_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2065 dst = jmp_r(dst, SCRATCH1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2066 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2067 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2068 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2069 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2070 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode); |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
102
diff
changeset
|
2071 exit(1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2072 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2073 return dst; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2074 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2075 |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2076 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2077 { |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2078 uint8_t * dest_addr, sec_reg; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2079 uint32_t after; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2080 uint32_t m68k_addr; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2081 switch(inst->src.addr_mode) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2082 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2083 case MODE_AREG_INDIRECT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2084 dst = cycles(dst, BUS*2); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2085 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2086 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2087 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2088 } |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2089 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2090 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2091 dst = call(dst, opts->write_32_highfirst); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2092 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2093 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2094 } else { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2095 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2096 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2097 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2098 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2099 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2100 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2101 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2102 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2103 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2104 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2105 break; |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2106 case MODE_AREG_DISPLACE: |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2107 dst = cycles(dst, BUS*2); |
187
8e138da572ab
Fix return address for areg displacement mode JSR
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
2108 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2109 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2110 dst = push_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2111 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2112 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2113 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2114 dst = call(dst, opts->write_32_highfirst); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2115 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2116 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2117 } else { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2118 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2119 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2120 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2121 dst = call(dst, (uint8_t *)m68k_native_addr); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2122 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2123 dst = call_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2124 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2125 dst = pop_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2126 } else { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2127 dst = jmp_r(dst, SCRATCH1); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2128 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2129 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2130 case MODE_AREG_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2131 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2132 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2133 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2134 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2135 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2136 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2137 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2138 dst = call(dst, opts->write_32_highfirst); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2139 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2140 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2141 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2142 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2143 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2144 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2145 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2146 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2147 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2148 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2149 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2150 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2151 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2152 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2153 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2154 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2155 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2156 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2157 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2158 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2159 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2160 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2161 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2162 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2163 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2164 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2165 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2166 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2167 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2168 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2169 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2170 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2171 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2172 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2173 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2174 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2175 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2176 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2177 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2178 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2179 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2180 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2181 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2182 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2183 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2184 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2185 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2186 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2187 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2188 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2189 dst = cycles(dst, 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2190 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2191 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2192 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2193 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2194 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2195 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2196 dst = call(dst, opts->write_32_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2197 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2198 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2199 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2200 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2201 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2202 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2203 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2204 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2205 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2206 dst = call(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2207 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2208 dst = jmp(dst, dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2209 } |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2210 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2211 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2212 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2213 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2214 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2215 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2216 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2217 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2218 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2219 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2220 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2221 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2222 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2223 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2224 case MODE_PC_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2225 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2226 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2227 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2228 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2229 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2230 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2231 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2232 dst = call(dst, opts->write_32_highfirst); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2233 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2234 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2235 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2236 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2237 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2238 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2239 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2240 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2241 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2242 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2243 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2244 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2245 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2246 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2247 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2248 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2249 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2250 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2251 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2252 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2253 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2254 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2255 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2256 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2257 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2258 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2259 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2260 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2261 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2262 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2263 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2264 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2265 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2266 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2267 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2268 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2269 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2270 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2271 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2272 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2273 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2274 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2275 } |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2276 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2277 case MODE_ABSOLUTE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2278 case MODE_ABSOLUTE_SHORT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2279 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2280 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2281 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2282 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2283 dst = push_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2284 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2285 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2286 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2287 dst = call(dst, opts->write_32_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2288 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2289 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2290 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2291 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2292 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2293 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2294 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2295 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2296 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2297 dst = call(dst, (char *)dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2298 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2299 dst = jmp(dst, dest_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2300 } |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2301 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2302 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2303 dst = call(dst, (uint8_t *)m68k_native_addr); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2304 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2305 dst = call_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2306 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2307 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2308 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2309 } |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2310 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2311 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2312 dst = pop_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2313 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2314 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2315 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2316 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2317 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode); |
105 | 2318 exit(1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2319 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2320 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2321 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2322 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2323 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2324 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2325 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2326 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2327 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2328 dst = call(dst, opts->read_32); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2329 if (opts->flags & OPT_NATIVE_CALL_STACK) { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2330 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2331 dst = jcc(dst, CC_NZ, dst+3); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2332 dst = retn(dst); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2333 dst = jmp(dst, (char *)m68k_modified_ret_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2334 } else { |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2335 dst = call(dst, (uint8_t *)m68k_native_addr); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2336 dst = jmp_r(dst, SCRATCH1); |
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2337 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2338 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2339 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2340 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2341 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2342 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2343 //best case duration |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2344 dst = cycles(dst, 10); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2345 uint8_t * skip_loc = NULL; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2346 //TODO: Check if COND_TRUE technically valid here even though |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2347 //it's basically a slow NOP |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2348 if (inst->extra.cond != COND_FALSE) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2349 uint8_t cond = CC_NZ; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2350 switch (inst->extra.cond) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2351 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2352 case COND_HIGH: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2353 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2354 case COND_LOW_SAME: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2355 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2356 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2357 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2358 case COND_CARRY_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2359 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2360 case COND_CARRY_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2361 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2362 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2363 case COND_NOT_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2364 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2365 case COND_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2366 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2367 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2368 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2369 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2370 case COND_OVERF_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2371 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2372 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2373 case COND_PLUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2374 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2375 case COND_MINUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2376 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2377 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2378 case COND_GREATER_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2379 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2380 case COND_LESS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2381 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2382 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2383 case COND_GREATER: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2384 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2385 case COND_LESS_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2386 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2387 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2388 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2389 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2390 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2391 skip_loc = dst + 1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2392 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2393 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2394 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2395 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2396 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2397 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2398 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2399 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2400 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2401 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2402 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2403 uint32_t after = inst->address + 2; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2404 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2405 if (!dest_addr) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2406 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2407 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2408 dest_addr = dst + 256; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2409 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2410 dst = jmp(dst, dest_addr); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2411 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2412 if (skip_loc) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2413 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2414 *skip_loc = dst - (skip_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2415 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2416 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2417 dst = cycles(dst, 4); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2418 } |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2419 return dst; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2420 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2421 |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2422 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2423 { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2424 int8_t reg = native_reg(&(inst->src), opts); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2425 //compensate for displacement word |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2426 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2427 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2428 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2429 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2430 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2431 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2432 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2433 } |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2434 dst = call(dst, opts->write_32_highfirst); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2435 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2436 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2437 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2438 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2439 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2440 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2441 //prefetch |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2442 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2443 return dst; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2444 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2445 |
172 | 2446 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2447 { | |
2448 int8_t reg; | |
2449 dst = cycles(dst, BUS*2); | |
2450 if (inst->src.addr_mode == MODE_REG) { | |
2451 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { | |
2452 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); | |
2453 } else { | |
2454 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); | |
2455 } | |
2456 if (inst->dst.params.regs.displacement) { | |
2457 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); | |
2458 } | |
2459 reg = native_reg(&(inst->src), opts); | |
2460 if (inst->extra.size == OPSIZE_LONG) { | |
2461 if (reg >= 0) { | |
2462 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2463 dst = shr_ir(dst, 24, SCRATCH1, SZ_D); | |
2464 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2465 dst = call(dst, opts->write_8); |
172 | 2466 dst = pop_r(dst, SCRATCH2); |
2467 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2468 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2469 |
172 | 2470 } else { |
2471 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B); | |
2472 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2473 dst = call(dst, opts->write_8); |
172 | 2474 dst = pop_r(dst, SCRATCH2); |
2475 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B); | |
2476 } | |
2477 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2478 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2479 dst = call(dst, opts->write_8); |
172 | 2480 dst = pop_r(dst, SCRATCH2); |
2481 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2482 } | |
2483 if (reg >= 0) { | |
2484 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2485 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); | |
2486 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2487 dst = call(dst, opts->write_8); |
172 | 2488 dst = pop_r(dst, SCRATCH2); |
2489 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2490 } else { | |
2491 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B); | |
2492 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2493 dst = call(dst, opts->write_8); |
172 | 2494 dst = pop_r(dst, SCRATCH2); |
2495 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B); | |
2496 } | |
2497 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2498 dst = call(dst, opts->write_8); |
172 | 2499 } else { |
2500 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | |
2501 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); | |
2502 } else { | |
2503 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); | |
2504 } | |
2505 if (inst->src.params.regs.displacement) { | |
2506 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); | |
2507 } | |
2508 reg = native_reg(&(inst->dst), opts); | |
2509 if (inst->extra.size == OPSIZE_LONG) { | |
2510 if (reg >= 0) { | |
2511 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
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324
diff
changeset
|
2512 dst = call(dst, opts->read_8); |
172 | 2513 dst = shl_ir(dst, 24, SCRATCH1, SZ_D); |
2514 dst = mov_rr(dst, SCRATCH1, reg, SZ_D); | |
2515 dst = pop_r(dst, SCRATCH1); | |
2516 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2517 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2518 dst = call(dst, opts->read_8); |
172 | 2519 dst = shl_ir(dst, 16, SCRATCH1, SZ_D); |
2520 dst = or_rr(dst, SCRATCH1, reg, SZ_D); | |
2521 } else { | |
2522 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2523 dst = call(dst, opts->read_8); |
172 | 2524 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B); |
2525 dst = pop_r(dst, SCRATCH1); | |
2526 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2527 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2528 dst = call(dst, opts->read_8); |
172 | 2529 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B); |
2530 } | |
2531 dst = pop_r(dst, SCRATCH1); | |
2532 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2533 } | |
2534 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2535 dst = call(dst, opts->read_8); |
172 | 2536 if (reg >= 0) { |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2537 |
172 | 2538 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
2539 dst = mov_rr(dst, SCRATCH1, reg, SZ_W); | |
2540 dst = pop_r(dst, SCRATCH1); | |
2541 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2542 dst = call(dst, opts->read_8); |
172 | 2543 dst = mov_rr(dst, SCRATCH1, reg, SZ_B); |
2544 } else { | |
2545 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B); | |
2546 dst = pop_r(dst, SCRATCH1); | |
2547 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2548 dst = call(dst, opts->read_8); |
172 | 2549 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B); |
2550 } | |
2551 } | |
2552 return dst; | |
2553 } | |
2554 | |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2555 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2556 { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2557 uint8_t size = inst->extra.size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2558 x86_ea src_op, dst_op; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2559 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2560 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2561 dst = push_r(dst, SCRATCH1); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2562 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2563 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2564 src_op.base = SCRATCH2; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2565 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2566 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2567 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2568 size = OPSIZE_LONG; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2569 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2570 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2571 dst = cycles(dst, BUS); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2572 if (src_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2573 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2574 dst = cmp_rr(dst, src_op.base, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2575 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2576 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2577 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2578 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2579 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2580 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2581 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2582 dst = cmp_ir(dst, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2583 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2584 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2585 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2586 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2587 dst = setcc_r(dst, CC_C, FLAG_C); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2588 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2589 dst = setcc_r(dst, CC_S, FLAG_N); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2590 dst = setcc_r(dst, CC_O, FLAG_V); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2591 return dst; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2592 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2593 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2594 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2595 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2596 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2597 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2598 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2599 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2600 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2601 uint8_t * end_off = NULL; |
207 | 2602 uint8_t * nz_off = NULL; |
2603 uint8_t * z_off = NULL; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2604 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2605 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2606 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2607 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2608 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2609 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2610 if (src_op->mode == MODE_IMMED) { |
207 | 2611 if (src_op->disp != 1 && inst->op == M68K_ASL) { |
2612 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2613 for (int i = 0; i < src_op->disp; i++) { | |
2614 if (dst_op->mode == MODE_REG_DIRECT) { | |
2615 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2616 } else { | |
2617 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2618 } | |
2619 //dst = setcc_r(dst, CC_O, FLAG_V); | |
2620 dst = jcc(dst, CC_NO, dst+4); | |
2621 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2622 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2623 } else { |
207 | 2624 if (dst_op->mode == MODE_REG_DIRECT) { |
2625 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); | |
2626 } else { | |
2627 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); | |
2628 } | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
2629 dst = setcc_r(dst, CC_O, FLAG_V); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2630 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2631 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2632 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2633 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2634 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2635 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2636 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2637 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2638 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2639 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2640 dst = and_ir(dst, 63, RCX, SZ_D); |
207 | 2641 nz_off = dst+1; |
2642 dst = jcc(dst, CC_NZ, dst+2); | |
2643 //Flag behavior for shift count of 0 is different for x86 than 68K | |
2644 if (dst_op->mode == MODE_REG_DIRECT) { | |
2645 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size); | |
2646 } else { | |
2647 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2648 } | |
2649 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
2650 dst = setcc_r(dst, CC_S, FLAG_N); | |
2651 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2652 //For other instructions, this flag will be set below | |
2653 if (inst->op == M68K_ASL) { | |
2654 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2655 } | |
2656 z_off = dst+1; | |
2657 dst = jmp(dst, dst+2); | |
2658 *nz_off = dst - (nz_off + 1); | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2659 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2660 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2661 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
207 | 2662 if (inst->op == M68K_ASL) { |
2663 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB | |
2664 //Easiest way to deal with this is to shift one bit at a time | |
2665 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2666 uint8_t * loop_start = dst; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2667 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2668 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2669 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2670 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2671 } |
207 | 2672 //dst = setcc_r(dst, CC_O, FLAG_V); |
2673 dst = jcc(dst, CC_NO, dst+4); | |
2674 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2675 dst = loop(dst, loop_start); | |
2676 } else { | |
2677 //x86 shifts modulo 32 for operand sizes less than 64-bits | |
2678 //but M68K shifts modulo 64, so we need to check for large shifts here | |
2679 dst = cmp_ir(dst, 32, RCX, SZ_B); | |
2680 uint8_t * norm_shift_off = dst + 1; | |
2681 dst = jcc(dst, CC_L, dst+2); | |
2682 if (special) { | |
2683 if (inst->extra.size == OPSIZE_LONG) { | |
2684 uint8_t * neq_32_off = dst + 1; | |
2685 dst = jcc(dst, CC_NZ, dst+2); | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2686 |
207 | 2687 //set the carry bit to the lsb |
2688 if (dst_op->mode == MODE_REG_DIRECT) { | |
2689 dst = special(dst, 1, dst_op->base, SZ_D); | |
2690 } else { | |
2691 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); | |
2692 } | |
2693 dst = setcc_r(dst, CC_C, FLAG_C); | |
2694 dst = jmp(dst, dst+4); | |
2695 *neq_32_off = dst - (neq_32_off+1); | |
2696 } | |
2697 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2698 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
2699 dst = mov_ir(dst, 0, FLAG_N, SZ_B); | |
2700 if (dst_op->mode == MODE_REG_DIRECT) { | |
2701 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); | |
2702 } else { | |
2703 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2704 } | |
2705 } else { | |
2706 if (dst_op->mode == MODE_REG_DIRECT) { | |
2707 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); | |
2708 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2709 } else { | |
2710 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); | |
2711 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2712 } | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2713 |
207 | 2714 } |
2715 end_off = dst+1; | |
2716 dst = jmp(dst, dst+2); | |
2717 *norm_shift_off = dst - (norm_shift_off+1); | |
2718 if (dst_op->mode == MODE_REG_DIRECT) { | |
2719 dst = shift_clr(dst, dst_op->base, inst->extra.size); | |
2720 } else { | |
2721 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); | |
2722 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2723 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2724 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2725 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2726 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2727 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2728 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2729 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2730 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2731 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2732 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2733 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2734 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2735 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2736 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2737 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
207 | 2738 if (z_off) { |
2739 *z_off = dst - (z_off + 1); | |
2740 } | |
219
8d3c16071559
Fix overflow flag behavior for lsl/lsr/asr
Mike Pavone <pavone@retrodev.com>
parents:
218
diff
changeset
|
2741 if (inst->op != M68K_ASL) { |
207 | 2742 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
2743 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2744 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2745 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2746 } |
66 | 2747 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2748 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2749 |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2750 #define BIT_SUPERVISOR 5 |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2751 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2752 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2753 { |
122 | 2754 uint8_t * end_off, *zero_off, *norm_off; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2755 uint8_t dst_reg; |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
2756 dst = check_cycles_int(dst, inst->address, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2757 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2758 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2759 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2760 return translate_m68k_lea(dst, inst, opts); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2761 } else if(inst->op == M68K_PEA) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2762 return translate_m68k_pea(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2763 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2764 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2765 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2766 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2767 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2768 return translate_m68k_jmp(dst, inst, opts); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2769 } else if(inst->op == M68K_JSR) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2770 return translate_m68k_jsr(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2771 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2772 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2773 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2774 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2775 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2776 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2777 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2778 return translate_m68k_movem(dst, inst, opts); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2779 } else if(inst->op == M68K_LINK) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2780 return translate_m68k_link(dst, inst, opts); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2781 } else if(inst->op == M68K_EXT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2782 return translate_m68k_ext(dst, inst, opts); |
112 | 2783 } else if(inst->op == M68K_SCC) { |
2784 return translate_m68k_scc(dst, inst, opts); | |
172 | 2785 } else if(inst->op == M68K_MOVEP) { |
2786 return translate_m68k_movep(dst, inst, opts); | |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2787 } else if(inst->op == M68K_INVALID) { |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2788 if (inst->src.params.immed == 0x7100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2789 return retn(dst); |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2790 } |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2791 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D); |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2792 return call(dst, (uint8_t *)m68k_invalid); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2793 } else if(inst->op == M68K_CMP) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2794 return translate_m68k_cmp(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2795 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2796 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2797 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2798 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2799 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2800 if (inst->dst.addr_mode != MODE_UNUSED) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
2801 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2802 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2803 uint8_t size; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2804 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2805 { |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2806 case M68K_ABCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2807 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2808 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2809 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2810 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2811 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2812 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2813 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2814 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2815 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2816 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2817 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2818 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2819 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2820 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2821 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2822 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2823 dst = add_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2824 dst = call(dst, (uint8_t *)bcd_add); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2825 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2826 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2827 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2828 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2829 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2830 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2831 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2832 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2833 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2834 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2835 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2836 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2837 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2838 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2839 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2840 dst = cycles(dst, BUS); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2841 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2842 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2843 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2844 dst = add_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2845 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2846 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2847 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2848 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2849 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2850 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2851 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2852 dst = add_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2853 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2854 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2855 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2856 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2857 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2858 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2859 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2860 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2861 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2862 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2863 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2864 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2865 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2866 case M68K_ADDX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2867 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2868 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2869 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2870 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2871 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2872 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2873 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2874 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2875 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2876 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2877 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2878 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2879 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2880 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2881 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2882 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2883 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2884 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2885 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2886 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2887 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2888 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2889 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2890 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2891 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2892 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2893 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2894 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2895 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2896 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2897 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2898 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2899 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2900 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2901 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2902 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2903 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2904 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2905 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2906 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2907 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2908 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2909 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2910 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2911 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2912 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2913 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2914 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2915 case M68K_ANDI_CCR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2916 case M68K_ANDI_SR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2917 dst = cycles(dst, 20); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2918 //TODO: If ANDI to SR, trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2919 if (!(inst->src.params.immed & 0x1)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2920 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2921 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2922 if (!(inst->src.params.immed & 0x2)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2923 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2924 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2925 if (!(inst->src.params.immed & 0x4)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2926 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2927 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2928 if (!(inst->src.params.immed & 0x8)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2929 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2930 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2931 if (!(inst->src.params.immed & 0x10)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2932 dst = mov_irind(dst, 0, CONTEXT, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2933 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2934 if (inst->op == M68K_ANDI_SR) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2935 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2936 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2937 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2938 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2939 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2940 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2941 } |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
319
diff
changeset
|
2942 //dst = call(dst, (uint8_t *)debug_print_sr); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2943 if (inst->src.params.immed & 0x700) { |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2944 dst = call(dst, (uint8_t *)do_sync); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2945 } |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2946 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2947 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2948 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2949 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2950 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2951 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2952 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2953 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2954 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2955 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2956 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2957 break; |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2958 case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2959 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2960 case M68K_BSET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2961 case M68K_BTST: |
457
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2962 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : ( |
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2963 inst->op == M68K_BTST ? 6 : (inst->op == M68K_BCLR ? 10 : 8)) |
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2964 ); |
67 | 2965 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2966 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2967 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2968 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2969 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2970 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2971 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2972 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2973 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2974 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2975 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2976 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2977 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2978 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2979 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2980 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2981 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2982 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2983 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2984 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2985 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2986 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2987 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2988 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2989 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2990 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2991 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2992 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2993 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2994 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2995 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != SCRATCH1 && src_op.base != SCRATCH2)) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2996 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2997 dst = push_r(dst, SCRATCH2); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2998 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2999 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3000 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3001 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3002 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3003 src_op.base = SCRATCH2; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3004 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3005 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3006 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3007 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3008 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3009 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3010 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3011 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3012 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3013 uint8_t size = inst->extra.size; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3014 if (dst_op.mode == MODE_REG_DISPLACE8) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3015 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3016 if (src_op.mode == MODE_REG_DIRECT) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3017 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3018 } else { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3019 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3020 src_op.mode = MODE_REG_DIRECT; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3021 } |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3022 src_op.base = SCRATCH1; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3023 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3024 //b### with register destination is modulo 32 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3025 //x86 with a memory destination isn't modulo anything |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3026 //so use an and here to force the value to be modulo 32 |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3027 dst = and_ir(dst, 31, SCRATCH1, SZ_D); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3028 } else if(inst->dst.addr_mode != MODE_REG) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3029 //b### with memory destination is modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3030 //x86-64 doesn't support 8-bit bit operations |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3031 //so we fake it by forcing the bit number to be modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3032 dst = and_ir(dst, 7, src_op.base, SZ_D); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3033 size = SZ_D; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3034 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3035 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3036 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3037 dst = bt_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3038 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3039 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3040 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3041 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3042 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3043 dst = bts_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3044 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3045 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3046 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3047 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3048 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3049 dst = btr_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3050 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3051 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3052 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3053 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3054 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3055 dst = btc_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3056 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3057 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3058 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3059 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3060 if (src_op.base == SCRATCH2) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3061 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3062 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3063 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3064 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3065 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3066 dst = setcc_r(dst, CC_NC, FLAG_Z); |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3067 if (inst->op != M68K_BTST) { |
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3068 dst = m68k_save_result(inst, dst, opts); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3069 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3070 break; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3071 case M68K_CHK: |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3072 { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3073 dst = cycles(dst, 6); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3074 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3075 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3076 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3077 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3078 } |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3079 uint32_t isize; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3080 switch(inst->src.addr_mode) |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3081 { |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3082 case MODE_AREG_DISPLACE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3083 case MODE_AREG_INDEX_DISP8: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3084 case MODE_ABSOLUTE_SHORT: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3085 case MODE_PC_INDEX_DISP8: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3086 case MODE_PC_DISPLACE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3087 case MODE_IMMEDIATE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3088 isize = 4; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3089 break; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3090 case MODE_ABSOLUTE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3091 isize = 6; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3092 break; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3093 default: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3094 isize = 2; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3095 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3096 uint8_t * passed = dst+1; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3097 dst = jcc(dst, CC_GE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3098 dst = mov_ir(dst, 1, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3099 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3100 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3101 dst = jmp(dst, opts->trap); |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3102 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3103 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3104 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3105 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3106 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3107 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3108 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3109 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3110 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3111 } else if(dst_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3112 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3113 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3114 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3115 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3116 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3117 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3118 passed = dst+1; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3119 dst = jcc(dst, CC_LE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3120 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3121 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3122 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3123 dst = jmp(dst, opts->trap); |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3124 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3125 dst = cycles(dst, 4); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3126 break; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3127 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3128 case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3129 case M68K_DIVU: |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3130 { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3131 //TODO: cycle exact division |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3132 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3133 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3134 dst = push_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3135 dst = push_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3136 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3137 dst = mov_rr(dst, dst_op.base, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3138 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3139 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3140 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3141 if (src_op.mode == MODE_IMMED) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3142 dst = mov_ir(dst, (src_op.disp & 0x8000) && inst->op == M68K_DIVS ? src_op.disp | 0xFFFF0000 : src_op.disp, SCRATCH2, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3143 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3144 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3145 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3146 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3147 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3148 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3149 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3150 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3151 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3152 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3153 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3154 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3155 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3156 dst = cmp_ir(dst, 0, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3157 uint8_t * not_zero = dst+1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3158 dst = jcc(dst, CC_NZ, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3159 dst = pop_r(dst, RAX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3160 dst = pop_r(dst, RDX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3161 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3162 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3163 dst = jmp(dst, opts->trap); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3164 *not_zero = dst - (not_zero+1); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3165 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3166 dst = cdq(dst); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3167 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3168 dst = xor_rr(dst, RDX, RDX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3169 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3170 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3171 dst = idiv_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3172 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3173 dst = div_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3174 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3175 uint8_t * skip_sec_check; |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3176 if (inst->op == M68K_DIVS) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3177 dst = cmp_ir(dst, 0x8000, RAX, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3178 skip_sec_check = dst + 1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3179 dst = jcc(dst, CC_GE, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3180 dst = cmp_ir(dst, -0x8000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3181 norm_off = dst+1; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3182 dst = jcc(dst, CC_L, dst+2); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3183 } else { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3184 dst = cmp_ir(dst, 0x10000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3185 norm_off = dst+1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3186 dst = jcc(dst, CC_NC, dst+2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3187 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3188 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3189 dst = mov_rr(dst, RDX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3190 dst = shl_ir(dst, 16, dst_op.base, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3191 dst = mov_rr(dst, RAX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3192 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3193 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3194 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3195 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3196 } |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3197 dst = cmp_ir(dst, 0, RAX, SZ_W); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3198 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3199 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3200 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3201 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3202 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3203 end_off = dst+1; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3204 dst = jmp(dst, dst+2); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3205 *norm_off = dst - (norm_off + 1); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3206 if (inst->op == M68K_DIVS) { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3207 *skip_sec_check = dst - (skip_sec_check+1); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3208 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3209 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3210 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3211 dst = mov_ir(dst, 1, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3212 *end_off = dst - (end_off + 1); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3213 break; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3214 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3215 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3216 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3217 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3218 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3219 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3220 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3221 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3222 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3223 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3224 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3225 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3226 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3227 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3228 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3229 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3230 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3231 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3232 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3233 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3234 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3235 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3236 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3237 break; |
171 | 3238 case M68K_EORI_CCR: |
3239 case M68K_EORI_SR: | |
3240 dst = cycles(dst, 20); | |
3241 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3242 if (inst->src.params.immed & 0x1) { | |
3243 dst = xor_ir(dst, 1, FLAG_C, SZ_B); | |
3244 } | |
3245 if (inst->src.params.immed & 0x2) { | |
3246 dst = xor_ir(dst, 1, FLAG_V, SZ_B); | |
3247 } | |
3248 if (inst->src.params.immed & 0x4) { | |
3249 dst = xor_ir(dst, 1, FLAG_Z, SZ_B); | |
3250 } | |
3251 if (inst->src.params.immed & 0x8) { | |
3252 dst = xor_ir(dst, 1, FLAG_N, SZ_B); | |
3253 } | |
3254 if (inst->src.params.immed & 0x10) { | |
3255 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B); | |
3256 } | |
3257 if (inst->op == M68K_ORI_SR) { | |
3258 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); | |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
319
diff
changeset
|
3259 //dst = call(dst, (uint8_t *)debug_print_sr); |
171 | 3260 if (inst->src.params.immed & 0x700) { |
3261 dst = call(dst, (uint8_t *)do_sync); | |
3262 } | |
3263 } | |
3264 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3265 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3266 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3267 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3268 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3269 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3270 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3271 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3272 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3273 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3274 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3275 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3276 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3277 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3278 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3279 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3280 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3281 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3282 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3283 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3284 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3285 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3286 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3287 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3288 case M68K_ILLEGAL: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3289 dst = call(dst, (uint8_t *)m68k_save_context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3290 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3291 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3292 break; |
105 | 3293 case M68K_MOVE_FROM_SR: |
3294 //TODO: Trap if not in system mode | |
3295 dst = call(dst, (uint8_t *)get_sr); | |
3296 if (dst_op.mode == MODE_REG_DIRECT) { | |
3297 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W); | |
3298 } else { | |
3299 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W); | |
3300 } | |
3301 dst = m68k_save_result(inst, dst, opts); | |
3302 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3303 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3304 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3305 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3306 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3307 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3308 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3309 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3310 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3311 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3312 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3313 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3314 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3315 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3316 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3317 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3318 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3319 } |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
319
diff
changeset
|
3320 //dst = call(dst, (uint8_t *)debug_print_sr); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3321 dst = call(dst, (uint8_t *)do_sync); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3322 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3323 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3324 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3325 if (src_op.base != SCRATCH1) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3326 if (src_op.mode == MODE_REG_DIRECT) { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3327 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3328 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3329 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3330 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3331 } |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3332 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr)); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3333 dst = cycles(dst, 12); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3334 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3335 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3336 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3337 case M68K_MOVE_USP: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3338 dst = cycles(dst, BUS); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3339 //TODO: Trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3340 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3341 if (inst->src.addr_mode == MODE_UNUSED) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3342 if (dst_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3343 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3344 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3345 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3346 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3347 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3348 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3349 if (src_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3350 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3351 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3352 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3353 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3354 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3355 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3356 break; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3357 //case M68K_MOVEP: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3358 case M68K_MULS: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3359 case M68K_MULU: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3360 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3361 if (src_op.mode == MODE_IMMED) { |
223
17534fb7c4f5
Fix muls with a negative immediate source.
Mike Pavone <pavone@retrodev.com>
parents:
221
diff
changeset
|
3362 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : ((src_op.disp & 0x8000) ? src_op.disp | 0xFFFF0000 : src_op.disp), SCRATCH1, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3363 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3364 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3365 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3366 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3367 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3368 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3369 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3370 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3371 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3372 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3373 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3374 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3375 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3376 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3377 dst_reg = dst_op.base; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3378 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3379 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3380 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3381 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3382 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3383 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3384 dst_reg = SCRATCH2; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3385 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3386 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3387 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3388 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3389 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3390 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3391 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3392 if (dst_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3393 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3394 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3395 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3396 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3397 dst = cmp_ir(dst, 0, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3398 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3399 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3400 break; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3401 //case M68K_NBCD: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3402 case M68K_NEG: |
173 | 3403 dst = cycles(dst, BUS); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3404 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3405 dst = neg_r(dst, dst_op.base, inst->extra.size); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3406 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
3407 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3408 } |
173 | 3409 dst = setcc_r(dst, CC_C, FLAG_C); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3410 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3411 dst = setcc_r(dst, CC_S, FLAG_N); |
173 | 3412 dst = setcc_r(dst, CC_O, FLAG_V); |
3413 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3414 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3415 break; |
173 | 3416 case M68K_NEGX: |
3417 dst = cycles(dst, BUS); | |
3418 if (dst_op.mode == MODE_REG_DIRECT) { | |
3419 if (dst_op.base == SCRATCH1) { | |
3420 dst = push_r(dst, SCRATCH2); | |
3421 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size); | |
3422 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3423 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size); | |
3424 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size); | |
3425 dst = pop_r(dst, SCRATCH2); | |
3426 } else { | |
3427 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3428 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3429 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size); | |
3430 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size); | |
3431 } | |
3432 } else { | |
3433 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3434 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3435 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size); | |
3436 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size); | |
3437 } | |
3438 dst = setcc_r(dst, CC_C, FLAG_C); | |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3439 dst = jcc(dst, CC_Z, dst+4); |
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3440 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
173 | 3441 dst = setcc_r(dst, CC_S, FLAG_N); |
3442 dst = setcc_r(dst, CC_O, FLAG_V); | |
3443 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
3444 dst = m68k_save_result(inst, dst, opts); | |
3445 break; | |
3446 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3447 case M68K_NOP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3448 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3449 break; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3450 case M68K_NOT: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3451 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3452 dst = not_r(dst, dst_op.base, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3453 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3454 } else { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3455 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3456 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3457 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3458 |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3459 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3460 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3461 dst = setcc_r(dst, CC_S, FLAG_N); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3462 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3463 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3464 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3465 case M68K_OR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3466 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3467 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3468 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3469 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3470 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3471 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3472 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3473 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3474 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3475 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3476 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3477 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3478 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3479 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3480 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3481 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3482 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3483 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3484 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3485 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3486 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3487 break; |
106 | 3488 case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3489 case M68K_ORI_SR: |
106 | 3490 dst = cycles(dst, 20); |
3491 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3492 if (inst->src.params.immed & 0x1) { | |
3493 dst = mov_ir(dst, 1, FLAG_C, SZ_B); | |
3494 } | |
3495 if (inst->src.params.immed & 0x2) { | |
3496 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
3497 } | |
3498 if (inst->src.params.immed & 0x4) { | |
3499 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
3500 } | |
3501 if (inst->src.params.immed & 0x8) { | |
3502 dst = mov_ir(dst, 1, FLAG_N, SZ_B); | |
3503 } | |
3504 if (inst->src.params.immed & 0x10) { | |
3505 dst = mov_irind(dst, 1, CONTEXT, SZ_B); | |
3506 } | |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3507 if (inst->op == M68K_ORI_SR) { |
106 | 3508 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
319
diff
changeset
|
3509 //dst = call(dst, (uint8_t *)debug_print_sr); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3510 if (inst->src.params.immed & 0x700) { |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3511 dst = call(dst, (uint8_t *)do_sync); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3512 } |
106 | 3513 } |
3514 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3515 case M68K_RESET: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3516 dst = call(dst, (uint8_t *)m68k_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3517 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3518 dst = call(dst, (uint8_t *)print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3519 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3520 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3521 case M68K_ROR: |
122 | 3522 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
3523 if (inst->src.addr_mode == MODE_UNUSED) { | |
3524 dst = cycles(dst, BUS); | |
3525 //Memory rotate | |
3526 if (inst->op == M68K_ROL) { | |
3527 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3528 } else { | |
3529 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3530 } | |
3531 dst = setcc_r(dst, CC_C, FLAG_C); | |
3532 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3533 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3534 dst = setcc_r(dst, CC_S, FLAG_N); | |
3535 dst = m68k_save_result(inst, dst, opts); | |
3536 } else { | |
3537 if (src_op.mode == MODE_IMMED) { | |
3538 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); | |
3539 if (dst_op.mode == MODE_REG_DIRECT) { | |
3540 if (inst->op == M68K_ROL) { | |
3541 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3542 } else { | |
3543 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3544 } | |
3545 } else { | |
3546 if (inst->op == M68K_ROL) { | |
3547 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3548 } else { | |
3549 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3550 } | |
3551 } | |
3552 dst = setcc_r(dst, CC_C, FLAG_C); | |
3553 } else { | |
3554 if (src_op.mode == MODE_REG_DIRECT) { | |
3555 if (src_op.base != SCRATCH1) { | |
3556 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); | |
3557 } | |
3558 } else { | |
3559 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | |
3560 } | |
3561 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | |
3562 zero_off = dst+1; | |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3563 dst = jcc(dst, CC_Z, dst+2); |
122 | 3564 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
3565 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | |
3566 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | |
3567 norm_off = dst+1; | |
3568 dst = jcc(dst, CC_L, dst+2); | |
442
1a48b31f5316
Fix carry flag on rotate when the register provided rotate bit count is exactly 32
Mike Pavone <pavone@retrodev.com>
parents:
440
diff
changeset
|
3569 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
122 | 3570 if (dst_op.mode == MODE_REG_DIRECT) { |
3571 if (inst->op == M68K_ROL) { | |
3572 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size); | |
3573 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3574 } else { | |
3575 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size); | |
3576 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3577 } | |
3578 } else { | |
3579 if (inst->op == M68K_ROL) { | |
3580 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3581 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3582 } else { | |
3583 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3584 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3585 } | |
3586 } | |
3587 *norm_off = dst - (norm_off+1); | |
3588 if (dst_op.mode == MODE_REG_DIRECT) { | |
3589 if (inst->op == M68K_ROL) { | |
3590 dst = rol_clr(dst, dst_op.base, inst->extra.size); | |
3591 } else { | |
3592 dst = ror_clr(dst, dst_op.base, inst->extra.size); | |
3593 } | |
3594 } else { | |
3595 if (inst->op == M68K_ROL) { | |
3596 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3597 } else { | |
3598 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3599 } | |
3600 } | |
3601 dst = setcc_r(dst, CC_C, FLAG_C); | |
3602 end_off = dst + 1; | |
3603 dst = jmp(dst, dst+2); | |
3604 *zero_off = dst - (zero_off+1); | |
3605 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
3606 *end_off = dst - (end_off+1); | |
3607 } | |
3608 if (dst_op.mode == MODE_REG_DIRECT) { | |
3609 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3610 } else { | |
3611 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); | |
3612 } | |
3613 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3614 dst = setcc_r(dst, CC_S, FLAG_N); | |
3615 } | |
3616 break; | |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3617 case M68K_ROXL: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3618 case M68K_ROXR: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3619 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3620 if (inst->src.addr_mode == MODE_UNUSED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3621 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3622 //Memory rotate |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3623 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3624 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3625 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3626 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3627 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3628 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3629 dst = setcc_r(dst, CC_C, FLAG_C); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3630 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3631 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3632 dst = setcc_r(dst, CC_S, FLAG_N); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3633 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3634 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3635 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3636 if (src_op.mode == MODE_IMMED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3637 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3638 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3639 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3640 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3641 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3642 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3643 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3644 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3645 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3646 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3647 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3648 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3649 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3650 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3651 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3652 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3653 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3654 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3655 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3656 if (src_op.base != SCRATCH1) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3657 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3658 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3659 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3660 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3661 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3662 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3663 zero_off = dst+1; |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3664 dst = jcc(dst, CC_Z, dst+2); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3665 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3666 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3667 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3668 norm_off = dst+1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3669 dst = jcc(dst, CC_L, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3670 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3671 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3672 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3673 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3674 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3675 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3676 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3677 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3678 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3679 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3680 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3681 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3682 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3683 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3684 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3685 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3686 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3687 } |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3688 dst = setcc_rind(dst, CC_C, CONTEXT); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3689 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3690 *norm_off = dst - (norm_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3691 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3692 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3693 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3694 dst = rcl_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3695 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3696 dst = rcr_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3697 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3698 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3699 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3700 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3701 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3702 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3703 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3704 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3705 dst = setcc_r(dst, CC_C, FLAG_C); |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3706 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3707 end_off = dst + 1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3708 dst = jmp(dst, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3709 *zero_off = dst - (zero_off+1); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3710 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3711 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3712 *end_off = dst - (end_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3713 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3714 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3715 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3716 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3717 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3718 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3719 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3720 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3721 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3722 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3723 case M68K_RTE: |
170 | 3724 //TODO: Trap if not in system mode |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3725 //Read saved SR |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3726 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3727 dst = call(dst, opts->read_16); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3728 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3729 dst = call(dst, (uint8_t *)set_sr); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3730 //Read saved PC |
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3731 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3732 dst = call(dst, opts->read_32); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3733 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3734 //Check if we've switched to user mode and swap stack pointers if needed |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3735 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3736 end_off = dst+1; |
121
f848aad2abef
Fix logic for switching between USP and SSP
Mike Pavone <pavone@retrodev.com>
parents:
119
diff
changeset
|
3737 dst = jcc(dst, CC_C, dst+2); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3738 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3739 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3740 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3741 *end_off = dst - (end_off+1); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3742 //Get native address, sync components, recalculate integer points and jump to returned address |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3743 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3744 dst = jmp_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3745 break; |
170 | 3746 case M68K_RTR: |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3747 //Read saved CCR |
170 | 3748 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3749 dst = call(dst, opts->read_16); |
170 | 3750 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
3751 dst = call(dst, (uint8_t *)set_ccr); | |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3752 //Read saved PC |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3753 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3754 dst = call(dst, opts->read_32); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3755 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3756 //Get native address and jump to it |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3757 dst = call(dst, (uint8_t *)m68k_native_addr); |
170 | 3758 dst = jmp_r(dst, SCRATCH1); |
3759 break; | |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3760 case M68K_SBCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3761 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3762 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3763 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3764 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3765 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3766 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3767 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3768 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3769 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3770 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3771 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3772 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3773 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3774 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3775 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3776 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3777 dst = sub_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3778 dst = call(dst, (uint8_t *)bcd_sub); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3779 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3780 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3781 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3782 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3783 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3784 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3785 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3786 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3787 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3788 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3789 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3790 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3791 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3792 break; |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3793 case M68K_STOP: { |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3794 //TODO: Trap if not in system mode |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3795 //manual says 4 cycles, but it has to be at least 8 since it's a 2-word instruction |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3796 //possibly even 12 since that's how long MOVE to SR takes |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3797 dst = cycles(dst, BUS*2); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3798 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3799 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3800 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3801 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3802 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3803 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3804 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3805 //leave supervisor mode |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3806 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3807 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3808 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3809 } |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3810 uint8_t * loop_top = dst; |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3811 dst = call(dst, (uint8_t *)do_sync); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3812 dst = cmp_rr(dst, LIMIT, CYCLES, SZ_D); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3813 uint8_t * normal_cycle_up = dst + 1; |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3814 dst = jcc(dst, CC_A, dst+2); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3815 dst = cycles(dst, BUS); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3816 uint8_t * after_cycle_up = dst + 1; |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3817 dst = jmp(dst, dst+2); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3818 *normal_cycle_up = dst - (normal_cycle_up + 1); |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3819 dst = mov_rr(dst, LIMIT, CYCLES, SZ_D); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3820 *after_cycle_up = dst - (after_cycle_up+1); |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3821 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3822 dst = jcc(dst, CC_C, loop_top); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3823 break; |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3824 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3825 case M68K_SUB: |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3826 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3827 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3828 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3829 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3830 dst = sub_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3831 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3832 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3833 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3834 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3835 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3836 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3837 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3838 dst = sub_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3839 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3840 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3841 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3842 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3843 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3844 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3845 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3846 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3847 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3848 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3849 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3850 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3851 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3852 case M68K_SUBX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3853 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3854 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3855 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3856 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3857 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3858 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3859 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3860 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3861 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3862 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3863 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3864 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3865 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3866 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3867 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3868 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3869 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3870 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3871 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3872 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3873 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3874 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3875 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3876 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3877 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3878 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3879 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3880 if (src_op.mode == MODE_REG_DIRECT) { |
129 | 3881 dst = rol_ir(dst, 16, src_op.base, SZ_D); |
443 | 3882 dst = cmp_ir(dst, 0, src_op.base, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3883 } else{ |
129 | 3884 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D); |
443 | 3885 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3886 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3887 |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3888 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3889 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3890 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3891 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3892 break; |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3893 //case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3894 case M68K_TRAP: |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3895 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
182
diff
changeset
|
3896 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3897 dst = jmp(dst, opts->trap); |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3898 break; |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3899 //case M68K_TRAPV: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3900 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3901 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3902 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3903 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3904 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3905 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3906 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3907 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3908 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3909 dst = setcc_r(dst, CC_S, FLAG_N); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3910 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3911 break; |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3912 case M68K_UNLK: |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3913 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3914 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3915 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3916 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3917 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3918 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3919 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3920 dst = call(dst, opts->read_32); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3921 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3922 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3923 } else { |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3924 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3925 } |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3926 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3927 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3928 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3929 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3930 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op); |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3931 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3932 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3933 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3934 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3935 |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3936 uint8_t m68k_is_terminal(m68kinst * inst) |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3937 { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3938 return inst->op == M68K_RTS || inst->op == M68K_RTE || inst->op == M68K_RTR || inst->op == M68K_JMP |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3939 || inst->op == M68K_TRAP || inst->op == M68K_ILLEGAL || inst->op == M68K_INVALID || inst->op == M68K_RESET |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3940 || (inst->op == M68K_BCC && inst->extra.cond == COND_TRUE); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3941 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3942 |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3943 void m68k_handle_deferred(m68k_context * context) |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3944 { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3945 x86_68k_options * opts = context->options; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3946 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3947 if (opts->deferred) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3948 translate_m68k_stream(opts->deferred->address, context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3949 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3950 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3951 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3952 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3953 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3954 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3955 x86_68k_options * opts = context->options; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3956 uint8_t * dst = opts->cur_code; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3957 uint8_t * dst_end = opts->code_end; |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
3958 address &= 0xFFFFFF; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3959 if(get_native_address(opts->native_code_map, address)) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3960 return dst; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3961 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3962 char disbuf[1024]; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3963 uint16_t *encoded, *next; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3964 if ((address & 0xFFFFFF) < 0x400000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3965 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3966 } else if ((address & 0xFFFFFF) > 0xE00000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3967 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3968 } else { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3969 printf("attempt to translate non-memory address: %X\n", address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3970 exit(1); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3971 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3972 do { |
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3973 if (opts->address_log) { |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3974 fprintf(opts->address_log, "%X\n", address); |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3975 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3976 do { |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3977 if (dst_end-dst < MAX_NATIVE_SIZE) { |
102
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3978 if (dst_end-dst < 5) { |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3979 puts("out of code memory, not enough space for jmp to next chunk"); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3980 exit(1); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3981 } |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3982 size_t size = 1024*1024; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3983 opts->cur_code = alloc_code(&size); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3984 opts->code_end = opts->cur_code + size; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3985 jmp(dst, opts->cur_code); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3986 dst = opts->cur_code; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3987 dst_end = opts->code_end; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3988 } |
159
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3989 if (address >= 0x400000 && address < 0xE00000) { |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3990 dst = xor_rr(dst, RDI, RDI, SZ_D); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3991 dst = call(dst, (uint8_t *)exit); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3992 break; |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3993 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3994 uint8_t * existing = get_native_address(opts->native_code_map, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3995 if (existing) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3996 dst = jmp(dst, existing); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3997 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3998 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3999 next = m68k_decode(encoded, &instbuf, address); |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
4000 if (instbuf.op == M68K_INVALID) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
4001 instbuf.src.params.immed = *encoded; |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
4002 } |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4003 uint16_t m68k_size = (next-encoded)*2; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4004 address += m68k_size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4005 encoded = next; |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
4006 //m68k_disasm(&instbuf, disbuf); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
4007 //printf("%X: %s\n", instbuf.address, disbuf); |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4008 uint8_t * after = translate_m68k(dst, &instbuf, opts); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4009 map_native_address(context, instbuf.address, dst, m68k_size, after-dst); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4010 dst = after; |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4011 } while(!m68k_is_terminal(&instbuf)); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
4012 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4013 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4014 address = opts->deferred->address; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4015 if ((address & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4016 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4017 } else if ((address & 0xFFFFFF) > 0xE00000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4018 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4019 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4020 printf("attempt to translate non-memory address: %X\n", address); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4021 exit(1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4022 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4023 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4024 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4025 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4026 } while(encoded != NULL); |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4027 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4028 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4029 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4030 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4031 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address) |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4032 { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4033 address &= 0xFFFFFF; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4034 uint8_t * ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4035 if (!ret) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4036 translate_m68k_stream(address, context); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4037 ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4038 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4039 return ret; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4040 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4041 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4042 void * m68k_retranslate_inst(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4043 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4044 x86_68k_options * opts = context->options; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4045 uint8_t orig_size = get_native_inst_size(opts, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4046 uint8_t * orig_start = get_native_address(context->native_code_map, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4047 uint32_t orig = address; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4048 address &= 0xFFFF; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4049 uint8_t * dst = opts->cur_code; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4050 uint8_t * dst_end = opts->code_end; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4051 uint16_t *after, *inst = context->mem_pointers[1] + address/2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4052 m68kinst instbuf; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4053 after = m68k_decode(inst, &instbuf, orig); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4054 if (orig_size != MAX_NATIVE_SIZE) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4055 if (dst_end - dst < 128) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4056 size_t size = 1024*1024; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4057 dst = alloc_code(&size); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4058 opts->code_end = dst_end = dst + size; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4059 opts->cur_code = dst; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4060 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4061 deferred_addr * orig_deferred = opts->deferred; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4062 uint8_t * native_end = translate_m68k(dst, &instbuf, opts); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4063 uint8_t is_terminal = m68k_is_terminal(&instbuf); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4064 if ((native_end - dst) <= orig_size) { |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4065 uint8_t * native_next; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4066 if (!is_terminal) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4067 native_next = get_native_address(context->native_code_map, orig + (after-inst)*2); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4068 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4069 if (is_terminal || (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5))) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4070 remove_deferred_until(&opts->deferred, orig_deferred); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4071 native_end = translate_m68k(orig_start, &instbuf, opts); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4072 if (!is_terminal) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4073 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4074 while (native_end < orig_start + orig_size) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4075 *(native_end++) = 0x90; //NOP |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4076 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4077 } else { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4078 jmp(native_end, native_next); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4079 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4080 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4081 m68k_handle_deferred(context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4082 return orig_start; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4083 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4084 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4085 |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4086 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4087 opts->cur_code = dst+MAX_NATIVE_SIZE; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4088 jmp(orig_start, dst); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4089 if (!m68k_is_terminal(&instbuf)) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4090 jmp(native_end, get_native_address_trans(context, orig + (after-inst)*2)); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4091 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4092 m68k_handle_deferred(context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4093 return dst; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4094 } else { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4095 dst = translate_m68k(orig_start, &instbuf, opts); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4096 if (!m68k_is_terminal(&instbuf)) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4097 dst = jmp(dst, get_native_address_trans(context, orig + (after-inst)*2)); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4098 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4099 m68k_handle_deferred(context); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4100 return orig_start; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4101 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4102 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4103 |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4104 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4105 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4106 uint32_t inst_start = get_instruction_start(context->native_code_map, address | 0xFF0000); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4107 if (inst_start) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4108 uint8_t * dst = get_native_address(context->native_code_map, inst_start); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4109 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4110 dst = jmp(dst, (uint8_t *)m68k_retrans_stub); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4111 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4112 return context; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4113 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4114 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4115 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4116 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4117 static uint8_t * bp_stub = NULL; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4118 uint8_t * native = get_native_address_trans(context, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4119 uint8_t * start_native = native; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4120 native = mov_ir(native, address, SCRATCH1, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4121 if (!bp_stub) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4122 x86_68k_options * opts = context->options; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4123 uint8_t * dst = opts->cur_code; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4124 uint8_t * dst_end = opts->code_end; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4125 if (dst_end - dst < 128) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4126 size_t size = 1024*1024; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4127 dst = alloc_code(&size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4128 opts->code_end = dst_end = dst + size; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4129 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4130 bp_stub = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4131 native = call(native, bp_stub); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4132 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4133 //Calculate length of prologue |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4134 dst = check_cycles_int(dst, address, opts); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4135 int check_int_size = dst-bp_stub; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4136 dst = bp_stub; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4137 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4138 //Save context and call breakpoint handler |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4139 dst = call(dst, (uint8_t *)m68k_save_context); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4140 dst = push_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4141 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4142 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4143 dst = call(dst, bp_handler); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4144 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4145 //Restore context |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4146 dst = call(dst, (uint8_t *)m68k_load_context); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4147 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4148 //do prologue stuff |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4149 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4150 uint8_t * jmp_off = dst+1; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4151 dst = jcc(dst, CC_NC, dst + 7); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4152 dst = call(dst, opts->handle_cycle_limit_int); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4153 *jmp_off = dst - (jmp_off+1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4154 //jump back to body of translated instruction |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4155 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4156 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4157 dst = jmp_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4158 opts->cur_code = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4159 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4160 native = call(native, bp_stub); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4161 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4162 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4163 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4164 void remove_breakpoint(m68k_context * context, uint32_t address) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4165 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4166 uint8_t * native = get_native_address(context->native_code_map, address); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4167 check_cycles_int(native, address, context->options); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4168 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4169 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4170 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4171 { |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
423
diff
changeset
|
4172 uint8_t * addr = get_native_address_trans(context, address); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4173 m68k_start_context(addr, context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4174 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4175 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4176 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4177 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4178 //TODO: Make this actually use the normal read functions |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4179 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4180 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4181 start_68k_context(context, address); |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4182 } |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4183 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4184 typedef enum { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4185 READ_16, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4186 READ_8, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4187 WRITE_16, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4188 WRITE_8 |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4189 } ftype; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4190 |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4191 uint8_t * gen_mem_fun(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4192 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4193 uint8_t * dst = opts->cur_code; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4194 uint8_t * start = dst; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4195 dst = check_cycles(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4196 dst = cycles(dst, BUS); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4197 dst = and_ir(dst, 0xFFFFFF, SCRATCH1, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4198 uint8_t *lb_jcc = NULL, *ub_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4199 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4200 uint8_t adr_reg = is_write ? SCRATCH2 : SCRATCH1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4201 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4202 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4203 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4204 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4205 if (memmap[chunk].start > 0) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4206 dst = cmp_ir(dst, memmap[chunk].start, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4207 lb_jcc = dst + 1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4208 dst = jcc(dst, CC_C, dst+2); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4209 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4210 if (memmap[chunk].end < 0x1000000) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4211 dst = cmp_ir(dst, memmap[chunk].end, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4212 ub_jcc = dst + 1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4213 dst = jcc(dst, CC_NC, dst+2); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4214 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4215 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4216 if (memmap[chunk].mask != 0xFFFFFF) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4217 dst = and_ir(dst, memmap[chunk].mask, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4218 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4219 void * cfun; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4220 switch (fun_type) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4221 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4222 case READ_16: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4223 cfun = memmap[chunk].read_16; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4224 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4225 case READ_8: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4226 cfun = memmap[chunk].read_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4227 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4228 case WRITE_16: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4229 cfun = memmap[chunk].write_16; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4230 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4231 case WRITE_8: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4232 cfun = memmap[chunk].write_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4233 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4234 default: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4235 cfun = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4236 } |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4237 if(memmap[chunk].buffer && memmap[chunk].flags & access_flag) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4238 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4239 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4240 dst = cmp_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4241 uint8_t * not_null = dst+1; |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4242 dst = jcc(dst, CC_NZ, dst+2); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4243 dst = call(dst, (uint8_t *)m68k_save_context); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4244 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4245 //SCRATCH2 is RDI, so no need to move it there |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4246 dst = mov_rr(dst, SCRATCH1, RDX, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4247 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4248 dst = push_r(dst, CONTEXT); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4249 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4250 } |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4251 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4252 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4253 dst = jcc(dst, CC_NZ, dst+2); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4254 dst = call(dst, cfun); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4255 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4256 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4257 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4258 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4259 dst = call(dst, cfun); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4260 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4261 *no_adjust = dst - (no_adjust + 1); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4262 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4263 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4264 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4265 dst = pop_r(dst, CONTEXT); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4266 dst = mov_rr(dst, RAX, SCRATCH1, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4267 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4268 dst = jmp(dst, (uint8_t *)m68k_load_context); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4269 |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4270 *not_null = dst - (not_null + 1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4271 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4272 if (size == SZ_B) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4273 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4274 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4275 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4276 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4277 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, size); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4278 |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4279 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4280 dst = mov_rindr(dst, SCRATCH1, SCRATCH1, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4281 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4282 } else { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4283 uint8_t tmp_size = size; |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4284 if (size == SZ_B) { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4285 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4286 dst = bt_ir(dst, 0, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4287 uint8_t * good_addr = dst + 1; |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4288 dst = jcc(dst, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, dst+2); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4289 if (!is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4290 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4291 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4292 dst = retn(dst); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4293 *good_addr = dst - (good_addr + 1); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4294 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4295 } else { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4296 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4297 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4298 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4299 tmp_size = SZ_B; |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4300 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4301 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4302 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4303 } |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4304 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4305 if ((int64_t)memmap[chunk].buffer <= 0x7FFFFFFF && (int64_t)memmap[chunk].buffer >= -2147483648) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4306 if (is_write) { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4307 dst = mov_rrdisp32(dst, SCRATCH1, SCRATCH2, (int64_t)memmap[chunk].buffer, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4308 } else { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4309 dst = mov_rdisp32r(dst, SCRATCH1, (int64_t)memmap[chunk].buffer, SCRATCH1, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4310 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4311 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4312 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4313 dst = push_r(dst, SCRATCH1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4314 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH1, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4315 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4316 dst = pop_r(dst, SCRATCH1); |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4317 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4318 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4319 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH2, SZ_Q); |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4320 dst = mov_rindexr(dst, SCRATCH2, SCRATCH1, 1, SCRATCH1, tmp_size); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4321 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4322 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4323 if (size != tmp_size && !is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4324 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4325 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4326 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4327 } else { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4328 dst = or_ir(dst, 0xFF00, SCRATCH1, SZ_W); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4329 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4330 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4331 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4332 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4333 dst = mov_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4334 dst = shr_ir(dst, 11, SCRATCH1, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4335 dst = bt_rrdisp32(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, ram_code_flags), SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4336 uint8_t * not_code = dst+1; |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4337 dst = jcc(dst, CC_NC, dst+2); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4338 dst = call(dst, (uint8_t *)m68k_save_context); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4339 dst = call(dst, (uint8_t *)m68k_handle_code_write); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4340 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4341 dst = call(dst, (uint8_t *)m68k_load_context); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4342 *not_code = dst - (not_code+1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4343 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4344 dst = retn(dst); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4345 } else if (cfun) { |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4346 dst = call(dst, (uint8_t *)m68k_save_context); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4347 if (is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4348 //SCRATCH2 is RDI, so no need to move it there |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4349 dst = mov_rr(dst, SCRATCH1, RDX, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4350 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4351 dst = push_r(dst, CONTEXT); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4352 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4353 } |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4354 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4355 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4356 dst = jcc(dst, CC_NZ, dst+2); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4357 dst = call(dst, cfun); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4358 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4359 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4360 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4361 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4362 dst = call(dst, cfun); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4363 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4364 *no_adjust = dst - (no_adjust+1); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4365 if (is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4366 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4367 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4368 dst = pop_r(dst, CONTEXT); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4369 dst = mov_rr(dst, RAX, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4370 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4371 dst = jmp(dst, (uint8_t *)m68k_load_context); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4372 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4373 //Not sure the best course of action here |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4374 if (!is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4375 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4376 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4377 dst = retn(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4378 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4379 if (lb_jcc) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4380 *lb_jcc = dst - (lb_jcc+1); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4381 lb_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4382 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4383 if (ub_jcc) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4384 *ub_jcc = dst - (ub_jcc+1); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4385 ub_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4386 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4387 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4388 if (!is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4389 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4390 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4391 dst = retn(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4392 opts->cur_code = dst; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4393 return start; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4394 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4395 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4396 void init_x86_68k_opts(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4397 { |
440 | 4398 memset(opts, 0, sizeof(*opts)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4399 for (int i = 0; i < 8; i++) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4400 opts->dregs[i] = opts->aregs[i] = -1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4401 opts->dregs[0] = R10; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4402 opts->dregs[1] = R11; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4403 opts->dregs[2] = R12; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4404 opts->dregs[3] = R8; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4405 opts->aregs[0] = R13; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4406 opts->aregs[1] = R14; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4407 opts->aregs[2] = R9; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4408 opts->aregs[7] = R15; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4409 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4410 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4411 opts->deferred = NULL; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4412 size_t size = 1024 * 1024; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4413 opts->cur_code = alloc_code(&size); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4414 opts->code_end = opts->cur_code + size; |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4415 opts->ram_inst_sizes = malloc(sizeof(uint8_t *) * 64); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4416 memset(opts->ram_inst_sizes, 0, sizeof(uint8_t *) * 64); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4417 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4418 opts->read_16 = gen_mem_fun(opts, memmap, num_chunks, READ_16); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4419 opts->read_8 = gen_mem_fun(opts, memmap, num_chunks, READ_8); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4420 opts->write_16 = gen_mem_fun(opts, memmap, num_chunks, WRITE_16); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4421 opts->write_8 = gen_mem_fun(opts, memmap, num_chunks, WRITE_8); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4422 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4423 uint8_t * dst = opts->cur_code; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4424 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4425 opts->read_32 = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4426 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4427 dst = call(dst, opts->read_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4428 dst = mov_rr(dst, SCRATCH1, SCRATCH2, SZ_W); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4429 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4430 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4431 dst = add_ir(dst, 2, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4432 dst = call(dst, opts->read_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4433 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4434 dst = movzx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4435 dst = shl_ir(dst, 16, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4436 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4437 dst = retn(dst); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4438 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4439 opts->write_32_lowfirst = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4440 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4441 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4442 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4443 dst = call(dst, opts->write_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4444 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4445 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4446 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4447 dst = jmp(dst, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4448 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4449 opts->write_32_highfirst = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4450 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4451 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4452 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4453 dst = call(dst, opts->write_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4454 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4455 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4456 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4457 dst = jmp(dst, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4458 |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4459 opts->handle_cycle_limit_int = dst; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4460 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4461 uint8_t * do_int = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4462 dst = jcc(dst, CC_NC, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4463 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4464 uint8_t * skip_sync = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4465 dst = jcc(dst, CC_C, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4466 dst = call(dst, (uint8_t *)m68k_save_context); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4467 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4468 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4469 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4470 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4471 dst = jcc(dst, CC_NZ, dst+2); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4472 dst = call(dst, (uint8_t *)sync_components); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4473 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4474 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4475 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4476 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4477 dst = call(dst, (uint8_t *)sync_components); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4478 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4479 *no_adjust = dst - (no_adjust+1); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4480 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4481 dst = jmp(dst, (uint8_t *)m68k_load_context); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4482 *skip_sync = dst - (skip_sync+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4483 dst = retn(dst); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4484 *do_int = dst - (do_int+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4485 //set target cycle to sync cycle |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4486 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), LIMIT, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4487 //swap USP and SSP if not already in supervisor mode |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4488 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4489 uint8_t *already_supervisor = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4490 dst = jcc(dst, CC_C, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4491 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4492 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4493 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4494 *already_supervisor = dst - (already_supervisor+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4495 //save PC |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4496 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4497 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4498 dst = call(dst, opts->write_32_lowfirst); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4499 //save status register |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4500 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4501 dst = call(dst, (uint8_t *)get_sr); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4502 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4503 dst = call(dst, opts->write_16); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4504 //update status register |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4505 dst = and_irdisp8(dst, 0xF8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4506 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4507 dst = or_ir(dst, 0x20, SCRATCH1, SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4508 dst = or_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4509 //calculate interrupt vector address |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4510 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4511 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, int_ack), SZ_W); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4512 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4513 dst = add_ir(dst, 0x60, SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4514 dst = call(dst, opts->read_32); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4515 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4516 dst = cycles(dst, 24); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4517 //discard function return address |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4518 dst = pop_r(dst, SCRATCH2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4519 dst = jmp_r(dst, SCRATCH1); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4520 |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4521 opts->trap = dst; |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4522 dst = push_r(dst, SCRATCH2); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4523 //swap USP and SSP if not already in supervisor mode |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4524 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4525 already_supervisor = dst+1; |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4526 dst = jcc(dst, CC_C, dst+2); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4527 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4528 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4529 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4530 *already_supervisor = dst - (already_supervisor+1); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4531 //save PC |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4532 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4533 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4534 dst = call(dst, opts->write_32_lowfirst); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4535 //save status register |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4536 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4537 dst = call(dst, (uint8_t *)get_sr); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4538 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4539 dst = call(dst, opts->write_16); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4540 //set supervisor bit |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4541 dst = or_irdisp8(dst, 0x20, CONTEXT, offsetof(m68k_context, status), SZ_B); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4542 //calculate vector address |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4543 dst = pop_r(dst, SCRATCH1); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4544 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4545 dst = call(dst, opts->read_32); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4546 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4547 dst = cycles(dst, 18); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4548 dst = jmp_r(dst, SCRATCH1); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4549 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4550 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4551 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4552 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4553 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
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4554 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
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4555 memset(context, 0, sizeof(m68k_context)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
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4556 context->native_code_map = native_code_map; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
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4557 context->options = opts; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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4558 context->int_cycle = 0xFFFFFFFF; |
167
f6c7fea1ecf7
Initialize status register to proper value on startup
Mike Pavone <pavone@retrodev.com>
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4559 context->status = 0x27; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
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4560 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
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4561 |