Mercurial > repos > blastem
annotate vdp.c @ 422:642b2f8aee32
Change default resolution to 640x480
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Tue, 25 Jun 2013 23:03:25 -0700 |
| parents | acdd6c5240fe |
| children | 7e8e179116af |
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1 #include "vdp.h" |
| 75 | 2 #include "blastem.h" |
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3 #include <stdlib.h> |
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4 #include <string.h> |
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5 |
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6 #define NTSC_ACTIVE 225 |
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7 #define PAL_ACTIVE 241 |
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8 #define BUF_BIT_PRIORITY 0x40 |
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9 #define MAP_BIT_PRIORITY 0x8000 |
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10 #define MAP_BIT_H_FLIP 0x800 |
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11 #define MAP_BIT_V_FLIP 0x1000 |
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12 |
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13 #define SCROLL_BUFFER_SIZE 32 |
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14 #define SCROLL_BUFFER_DRAW 16 |
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15 |
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16 #define FIFO_SIZE 4 |
| 40 | 17 |
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18 #define MCLKS_SLOT_H40 16 |
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19 #define MCLKS_SLOT_H32 20 |
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20 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
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21 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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22 #define HSYNC_SLOT_H40 21 |
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23 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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24 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
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25 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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26 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
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27 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
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28 |
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29 void init_vdp_context(vdp_context * context) |
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30 { |
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31 memset(context, 0, sizeof(*context)); |
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32 context->vdpmem = malloc(VRAM_SIZE); |
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33 memset(context->vdpmem, 0, VRAM_SIZE); |
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34 context->oddbuf = context->framebuf = malloc(FRAMEBUF_SIZE); |
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35 memset(context->framebuf, 0, FRAMEBUF_SIZE); |
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36 context->evenbuf = malloc(FRAMEBUF_SIZE); |
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37 memset(context->evenbuf, 0, FRAMEBUF_SIZE); |
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38 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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39 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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40 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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41 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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42 context->sprite_draws = MAX_DRAWS; |
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43 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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44 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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45 } |
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46 |
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47 void render_sprite_cells(vdp_context * context) |
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48 { |
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49 if (context->cur_slot >= context->sprite_draws) { |
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50 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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51 |
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52 uint16_t dir; |
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53 int16_t x; |
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54 if (d->h_flip) { |
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55 x = d->x_pos + 7; |
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56 dir = -1; |
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57 } else { |
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58 x = d->x_pos; |
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59 dir = 1; |
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60 } |
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61 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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62 context->cur_slot--; |
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63 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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64 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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65 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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66 } |
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67 x += dir; |
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68 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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69 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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70 } |
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71 x += dir; |
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72 } |
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73 } |
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74 } |
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75 |
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76 void vdp_print_sprite_table(vdp_context * context) |
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77 { |
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78 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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79 uint16_t current_index = 0; |
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80 uint8_t count = 0; |
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81 do { |
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82 uint16_t address = current_index * 8 + sat_address; |
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83 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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84 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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85 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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86 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
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87 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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88 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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89 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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90 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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91 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
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92 current_index = link; |
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93 count++; |
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94 } while (current_index != 0 && count < 80); |
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95 } |
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96 |
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97 void vdp_print_reg_explain(vdp_context * context) |
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98 { |
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99 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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100 printf("**Mode Group**\n" |
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101 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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102 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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103 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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104 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
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105 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
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106 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
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107 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
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108 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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109 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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110 hscroll[context->regs[REG_MODE_3] & 0x3], |
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111 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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112 printf("\n**Table Group**\n" |
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113 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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114 "03: %.2X | Window Name Table: $%.4X\n" |
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115 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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116 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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117 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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118 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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119 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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120 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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121 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
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122 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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123 char * sizes[] = {"32", "64", "invalid", "128"}; |
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124 printf("\n**Misc Group**\n" |
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125 "07: %.2X | Backdrop Color: $%X\n" |
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126 "0A: %.2X | H-Int Counter: %u\n" |
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127 "0F: %.2X | Auto-increment: $%X\n" |
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128 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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129 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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130 context->regs[REG_HINT], context->regs[REG_HINT], |
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131 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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132 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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133 |
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134 //TODO: Window Group, DMA Group |
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135 } |
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136 |
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137 void scan_sprite_table(uint32_t line, vdp_context * context) |
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138 { |
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139 if (context->sprite_index && context->slot_counter) { |
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140 line += 1; |
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141 line &= 0xFF; |
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142 uint16_t ymask, ymin; |
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143 uint8_t height_mult; |
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144 if (context->double_res) { |
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145 line *= 2; |
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146 if (context->framebuf != context->oddbuf) { |
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147 line++; |
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148 } |
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149 ymask = 0x3FF; |
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150 ymin = 256; |
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151 height_mult = 16; |
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152 } else { |
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153 ymask = 0x1FF; |
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154 ymin = 128; |
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155 height_mult = 8; |
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156 } |
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157 context->sprite_index &= 0x7F; |
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158 if (context->latched_mode & BIT_H40) { |
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159 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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160 context->sprite_index = 0; |
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161 return; |
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162 } |
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163 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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164 context->sprite_index = 0; |
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165 return; |
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166 } |
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167 //TODO: Read from SAT cache rather than from VRAM |
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168 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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169 uint16_t address = context->sprite_index * 8 + sat_address; |
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170 line += ymin; |
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171 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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172 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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173 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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174 if (y <= line && line < (y + height)) { |
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175 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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176 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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177 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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178 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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179 } |
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180 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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181 if (context->sprite_index && context->slot_counter) |
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182 { |
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183 address = context->sprite_index * 8 + sat_address; |
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184 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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185 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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186 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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187 if (y <= line && line < (y + height)) { |
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188 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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189 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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190 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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191 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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192 } |
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193 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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194 } |
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195 } |
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196 } |
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197 |
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198 void read_sprite_x(uint32_t line, vdp_context * context) |
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199 { |
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200 if (context->cur_slot >= context->slot_counter) { |
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201 if (context->sprite_draws) { |
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202 line += 1; |
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203 line &= 0xFF; |
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204 //in tiles |
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205 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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206 //in pixels |
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207 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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208 if (context->double_res) { |
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209 line *= 2; |
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210 if (context->framebuf != context->oddbuf) { |
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211 line++; |
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212 } |
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213 height *= 2; |
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214 } |
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215 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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216 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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217 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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218 uint8_t row; |
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219 if (tileinfo & MAP_BIT_V_FLIP) { |
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220 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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221 } else { |
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222 row = line-context->sprite_info_list[context->cur_slot].y; |
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223 } |
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224 uint16_t address; |
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225 if (context->double_res) { |
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226 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
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227 } else { |
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228 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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229 } |
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323
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230 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
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231 if (x) { |
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232 context->flags |= FLAG_CAN_MASK; |
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233 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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234 context->flags |= FLAG_MASKED; |
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235 } |
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236 |
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237 context->flags &= ~FLAG_DOT_OFLOW; |
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238 int16_t i; |
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239 if (context->flags & FLAG_MASKED) { |
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240 for (i=0; i < width && context->sprite_draws; i++) { |
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241 --context->sprite_draws; |
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242 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
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243 } |
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244 } else { |
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245 x -= 128; |
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246 int16_t base_x = x; |
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247 int16_t dir; |
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248 if (tileinfo & MAP_BIT_H_FLIP) { |
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249 x += (width-1) * 8; |
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250 dir = -8; |
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251 } else { |
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252 dir = 8; |
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253 } |
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254 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
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255 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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256 --context->sprite_draws; |
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257 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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258 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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259 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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260 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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261 } |
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262 } |
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263 if (i < width) { |
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264 context->flags |= FLAG_DOT_OFLOW; |
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265 } |
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266 context->cur_slot--; |
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267 } else { |
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268 context->flags |= FLAG_DOT_OFLOW; |
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269 } |
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270 } |
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271 } |
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272 |
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273 #define VRAM_READ 0 |
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274 #define VRAM_WRITE 1 |
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275 #define CRAM_READ 8 |
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276 #define CRAM_WRITE 3 |
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277 #define VSRAM_READ 4 |
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278 #define VSRAM_WRITE 5 |
| 75 | 279 #define DMA_START 0x20 |
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280 |
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281 void external_slot(vdp_context * context) |
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282 { |
| 75 | 283 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
| 284 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
| 285 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
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286 if(context->flags & FLAG_DMA_RUN) { |
| 75 | 287 uint16_t dma_len; |
| 288 switch(context->regs[REG_DMASRC_H] & 0xC0) | |
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289 { |
| 75 | 290 //68K -> VDP |
| 291 case 0: | |
| 292 case 0x40: | |
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293 switch(context->dma_cd & 0xF) |
| 75 | 294 { |
| 295 case VRAM_WRITE: | |
| 296 if (context->flags & FLAG_DMA_PROG) { | |
| 297 context->vdpmem[context->address ^ 1] = context->dma_val; | |
| 298 context->flags &= ~FLAG_DMA_PROG; | |
| 299 } else { | |
| 300 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 301 context->vdpmem[context->address] = context->dma_val >> 8; | |
| 302 context->flags |= FLAG_DMA_PROG; | |
| 303 } | |
| 304 break; | |
| 305 case CRAM_WRITE: | |
| 306 context->cram[(context->address/2) & (CRAM_SIZE-1)] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
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307 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles); |
| 75 | 308 break; |
| 309 case VSRAM_WRITE: | |
| 310 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 311 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 312 } | |
| 313 break; | |
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314 } |
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315 break; |
| 75 | 316 //Fill |
| 317 case 0x80: | |
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318 switch(context->dma_cd & 0xF) |
| 75 | 319 { |
| 320 case VRAM_WRITE: | |
| 321 //Charles MacDonald's VDP doc says that the low byte gets written first | |
| 142 | 322 context->vdpmem[context->address] = context->dma_val; |
| 323 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF); | |
| 75 | 324 break; |
| 325 case CRAM_WRITE: | |
| 326 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
|
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327 //printf("CRAM DMA Fill | %X set to %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->cycles); |
| 75 | 328 break; |
| 329 case VSRAM_WRITE: | |
| 330 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 331 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 332 } | |
| 333 break; | |
| 334 } | |
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335 break; |
| 75 | 336 //Copy |
| 337 case 0xC0: | |
| 338 if (context->flags & FLAG_DMA_PROG) { | |
|
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339 switch(context->dma_cd & 0xF) |
| 75 | 340 { |
| 341 case VRAM_WRITE: | |
| 342 context->vdpmem[context->address] = context->dma_val; | |
| 343 break; | |
| 344 case CRAM_WRITE: | |
| 345 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
|
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346 //printf("CRAM DMA Copy | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->regs[REG_DMASRC_L] & (CRAM_SIZE-1), context->cycles); |
| 75 | 347 break; |
| 348 case VSRAM_WRITE: | |
| 349 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 350 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 351 } | |
| 352 break; | |
| 353 } | |
| 354 context->flags &= ~FLAG_DMA_PROG; | |
| 355 } else { | |
| 356 //I assume, that DMA copy copies from the same RAM as the destination | |
| 357 //but it's possible I'm mistaken | |
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358 switch(context->dma_cd & 0xF) |
| 75 | 359 { |
| 360 case VRAM_WRITE: | |
| 361 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
| 362 break; | |
| 363 case CRAM_WRITE: | |
| 364 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
| 365 break; | |
| 366 case VSRAM_WRITE: | |
| 367 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
| 368 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
| 369 } else { | |
| 370 context->dma_val = 0; | |
| 371 } | |
| 372 break; | |
| 373 } | |
| 374 context->flags |= FLAG_DMA_PROG; | |
|
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375 } |
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376 break; |
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377 } |
| 75 | 378 if (!(context->flags & FLAG_DMA_PROG)) { |
| 379 context->address += context->regs[REG_AUTOINC]; | |
| 380 context->regs[REG_DMASRC_L] += 1; | |
| 135 | 381 if (!context->regs[REG_DMASRC_L]) { |
| 382 context->regs[REG_DMASRC_M] += 1; | |
| 383 } | |
| 75 | 384 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
| 385 context->regs[REG_DMALEN_H] = dma_len >> 8; | |
| 386 context->regs[REG_DMALEN_L] = dma_len; | |
| 387 if (!dma_len) { | |
| 388 context->flags &= ~FLAG_DMA_RUN; | |
| 389 } | |
|
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390 } |
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391 } else { |
| 75 | 392 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
| 393 if (context->fifo_cur != start && start->cycle <= context->cycles) { | |
| 394 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { | |
| 395 context->flags |= FLAG_DMA_RUN; | |
| 396 context->dma_val = start->value; | |
| 138 | 397 context->address = start->address; //undo auto-increment |
|
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398 context->dma_cd = context->cd; |
| 75 | 399 } else { |
| 138 | 400 switch (start->cd & 0xF) |
| 75 | 401 { |
| 402 case VRAM_WRITE: | |
| 403 if (start->partial) { | |
| 404 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); | |
| 138 | 405 context->vdpmem[start->address ^ 1] = start->value; |
| 75 | 406 } else { |
| 407 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); | |
| 138 | 408 context->vdpmem[start->address] = start->value >> 8; |
| 75 | 409 start->partial = 1; |
| 410 //skip auto-increment and removal of entry from fifo | |
| 411 return; | |
| 412 } | |
| 413 break; | |
| 414 case CRAM_WRITE: | |
|
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415 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
| 138 | 416 context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value; |
| 75 | 417 break; |
| 418 case VSRAM_WRITE: | |
| 138 | 419 if (((start->address/2) & 63) < VSRAM_SIZE) { |
| 75 | 420 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
| 138 | 421 context->vsram[(start->address/2) & 63] = start->value; |
| 75 | 422 } |
| 423 break; | |
| 424 } | |
| 138 | 425 //context->address += context->regs[REG_AUTOINC]; |
| 75 | 426 } |
| 427 fifo_entry * cur = start+1; | |
| 428 if (cur < context->fifo_cur) { | |
| 429 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); | |
| 430 } | |
| 431 context->fifo_cur -= 1; | |
| 432 } else { | |
| 433 context->flags |= FLAG_UNUSED_SLOT; | |
| 434 } | |
|
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435 } |
|
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436 } |
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437 |
| 40 | 438 #define WINDOW_RIGHT 0x80 |
| 439 #define WINDOW_DOWN 0x80 | |
| 440 | |
|
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441 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
|
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442 { |
|
417
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443 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
|
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444 if (context->double_res) { |
|
413
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445 line *= 2; |
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446 if (context->framebuf != context->oddbuf) { |
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447 line++; |
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448 } |
|
417
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449 window_line_shift = 4; |
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450 v_offset_mask = 0xF; |
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451 vscroll_shift = 4; |
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452 } else { |
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453 window_line_shift = 3; |
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454 v_offset_mask = 0x7; |
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455 vscroll_shift = 3; |
|
414
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456 } |
| 40 | 457 if (!vsram_off) { |
| 458 uint16_t left_col, right_col; | |
| 459 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
|
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460 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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461 right_col = 42; |
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462 } else { |
| 40 | 463 left_col = 0; |
| 464 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
| 465 if (right_col) { | |
| 466 right_col += 2; | |
| 467 } | |
| 468 } | |
|
41
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469 uint16_t top_line, bottom_line; |
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470 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
|
417
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471 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
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472 bottom_line = context->double_res ? 481 : 241; |
|
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473 } else { |
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474 top_line = 0; |
|
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475 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
|
41
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476 } |
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477 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
|
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478 uint16_t address = context->regs[REG_WINDOW] << 10; |
|
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479 uint16_t line_offset, offset, mask; |
|
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480 if (context->latched_mode & BIT_H40) { |
|
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481 address &= 0xF000; |
|
417
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|
482 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
|
41
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diff
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|
483 mask = 0x7F; |
|
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|
484 |
|
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|
485 } else { |
|
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|
486 address &= 0xF800; |
|
417
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415
diff
changeset
|
487 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
|
41
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40
diff
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|
488 mask = 0x3F; |
|
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|
489 } |
|
417
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415
diff
changeset
|
490 if (context->double_res) { |
|
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415
diff
changeset
|
491 mask <<= 1; |
|
acdd6c5240fe
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415
diff
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|
492 mask |= 1; |
|
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415
diff
changeset
|
493 } |
|
42
6653e67a6811
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Mike Pavone <pavone@retrodev.com>
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41
diff
changeset
|
494 offset = address + line_offset + (((column - 2) * 2) & mask); |
|
41
e591004487bc
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40
diff
changeset
|
495 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
54
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43
diff
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|
496 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
|
42
6653e67a6811
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Mike Pavone <pavone@retrodev.com>
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41
diff
changeset
|
497 offset = address + line_offset + (((column - 1) * 2) & mask); |
|
41
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40
diff
changeset
|
498 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
417
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415
diff
changeset
|
499 context->v_offset = (line) & v_offset_mask; |
|
41
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40
diff
changeset
|
500 context->flags |= FLAG_WINDOW; |
|
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40
diff
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|
501 return; |
| 40 | 502 } |
| 503 context->flags &= ~FLAG_WINDOW; | |
| 504 } | |
|
20
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|
505 uint16_t vscroll; |
|
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|
506 switch(context->regs[REG_SCROLL] & 0x30) |
|
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|
507 { |
|
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|
508 case 0: |
|
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changeset
|
509 vscroll = 0xFF; |
|
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changeset
|
510 break; |
|
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changeset
|
511 case 0x10: |
|
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|
512 vscroll = 0x1FF; |
|
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changeset
|
513 break; |
|
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changeset
|
514 case 0x20: |
|
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changeset
|
515 //TODO: Verify this behavior |
|
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|
516 vscroll = 0; |
|
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|
517 break; |
|
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changeset
|
518 case 0x30: |
|
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|
519 vscroll = 0x3FF; |
|
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changeset
|
520 break; |
|
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changeset
|
521 } |
|
414
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413
diff
changeset
|
522 if (context->double_res) { |
|
413
36fbbced25c2
Initial work on interlace
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337
diff
changeset
|
523 vscroll <<= 1; |
|
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changeset
|
524 vscroll |= 1; |
|
414
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413
diff
changeset
|
525 } |
|
327
1b00258b1f29
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323
diff
changeset
|
526 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? column : 0) + vsram_off] + line); |
|
414
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413
diff
changeset
|
527 context->v_offset = vscroll & v_offset_mask; |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
528 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
|
414
51ee0f117365
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413
diff
changeset
|
529 vscroll >>= vscroll_shift; |
|
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changeset
|
530 uint16_t hscroll_mask; |
|
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changeset
|
531 uint16_t v_mul; |
|
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changeset
|
532 switch(context->regs[REG_SCROLL] & 0x3) |
|
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diff
changeset
|
533 { |
|
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diff
changeset
|
534 case 0: |
|
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
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87
diff
changeset
|
535 hscroll_mask = 0x1F; |
|
20
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diff
changeset
|
536 v_mul = 64; |
|
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537 break; |
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538 case 0x1: |
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539 hscroll_mask = 0x3F; |
|
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540 v_mul = 128; |
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541 break; |
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542 case 0x2: |
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543 //TODO: Verify this behavior |
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544 hscroll_mask = 0; |
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545 v_mul = 0; |
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546 break; |
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547 case 0x3: |
|
108
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548 hscroll_mask = 0x7F; |
|
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549 v_mul = 256; |
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|
550 break; |
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551 } |
| 28 | 552 uint16_t hscroll, offset; |
| 553 for (int i = 0; i < 2; i++) { | |
|
39
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38
diff
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|
554 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
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555 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
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556 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
| 28 | 557 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
| 558 if (i) { | |
| 559 context->col_2 = col_val; | |
| 560 } else { | |
| 561 context->col_1 = col_val; | |
| 562 } | |
| 563 } | |
|
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564 } |
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565 |
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566 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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567 { |
|
25
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568 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
|
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569 } |
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570 |
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571 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
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572 { |
|
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573 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
|
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574 } |
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575 |
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576 void render_map(uint16_t col, uint8_t * tmp_buf, vdp_context * context) |
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577 { |
|
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578 uint16_t address; |
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579 uint8_t shift, add; |
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580 if (context->double_res) { |
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581 address = ((col & 0x3FF) << 6); |
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582 shift = 1; |
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583 add = context->framebuf != context->oddbuf ? 1 : 0; |
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584 } else { |
|
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585 address = ((col & 0x7FF) << 5); |
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586 shift = 0; |
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|
587 add = 0; |
|
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|
588 } |
|
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589 if (col & MAP_BIT_V_FLIP) { |
|
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413
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590 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
|
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591 } else { |
|
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592 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
|
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593 } |
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594 uint16_t pal_priority = (col >> 9) & 0x70; |
|
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595 int32_t dir; |
|
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596 if (col & MAP_BIT_H_FLIP) { |
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597 tmp_buf += 7; |
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598 dir = -1; |
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599 } else { |
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|
600 dir = 1; |
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|
601 } |
|
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602 for (uint32_t i=0; i < 4; i++, address++) |
|
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|
603 { |
|
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604 *tmp_buf = pal_priority | (context->vdpmem[address] >> 4); |
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605 tmp_buf += dir; |
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606 *tmp_buf = pal_priority | (context->vdpmem[address] & 0xF); |
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607 tmp_buf += dir; |
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|
608 } |
|
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609 } |
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|
610 |
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|
611 void render_map_1(vdp_context * context) |
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612 { |
|
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|
613 render_map(context->col_1, context->tmp_buf_a+SCROLL_BUFFER_DRAW, context); |
|
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614 } |
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|
615 |
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|
616 void render_map_2(vdp_context * context) |
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|
617 { |
|
39
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|
618 render_map(context->col_2, context->tmp_buf_a+SCROLL_BUFFER_DRAW+8, context); |
|
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|
619 } |
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|
620 |
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|
621 void render_map_3(vdp_context * context) |
|
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|
622 { |
|
39
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|
623 render_map(context->col_1, context->tmp_buf_b+SCROLL_BUFFER_DRAW, context); |
|
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624 } |
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|
625 |
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|
626 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
|
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|
627 { |
|
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|
628 if (line >= 240) { |
|
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|
629 return; |
|
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|
630 } |
|
39
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|
631 render_map(context->col_2, context->tmp_buf_b+SCROLL_BUFFER_DRAW+8, context); |
|
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632 uint16_t *dst, *end; |
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633 uint8_t *sprite_buf, *plane_a, *plane_b; |
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634 if (col) |
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|
635 { |
|
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|
636 col-=2; |
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637 dst = context->framebuf + line * 320 + col * 8; |
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|
638 sprite_buf = context->linebuf + col * 8; |
|
43
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diff
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|
639 uint16_t a_src; |
| 40 | 640 if (context->flags & FLAG_WINDOW) { |
| 641 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW; | |
|
43
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|
642 a_src = FBUF_SRC_W; |
| 40 | 643 } else { |
| 644 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW - (context->hscroll_a & 0xF); | |
|
43
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|
645 a_src = FBUF_SRC_A; |
| 40 | 646 } |
|
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diff
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|
647 plane_b = context->tmp_buf_b + SCROLL_BUFFER_DRAW - (context->hscroll_b & 0xF); |
| 30 | 648 end = dst + 16; |
|
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|
649 uint16_t src; |
| 30 | 650 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
|
230
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651 |
|
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652 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
|
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|
653 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
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654 uint8_t pixel; |
|
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|
655 |
|
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|
656 src = 0; |
|
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|
657 uint8_t sprite_color = *sprite_buf & 0x3F; |
|
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|
658 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
|
232
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|
659 if (sprite_color == 0x3F) { |
|
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|
660 src = FBUF_SHADOW; |
|
230
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|
661 } else { |
|
232
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diff
changeset
|
662 src = FBUF_HILIGHT; |
|
230
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diff
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|
663 } |
|
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diff
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|
664 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
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Mike Pavone <pavone@retrodev.com>
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diff
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|
665 pixel = *plane_a; |
|
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Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
666 src |= a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
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|
667 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
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parents:
191
diff
changeset
|
668 pixel = *plane_b; |
|
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Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
669 src |= FBUF_SRC_B; |
|
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Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
670 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
671 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
672 src |= a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
673 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
674 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
675 src |= FBUF_SRC_B; |
|
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
676 } else { |
|
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
677 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
678 src |= FBUF_SRC_BG; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
679 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
680 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
681 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
682 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
683 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
684 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
685 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
686 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
687 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
688 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
689 src = FBUF_SRC_B; |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
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232
diff
changeset
|
690 } else { |
|
9d10669f2579
Less broken implementation of shadow/highlight
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232
diff
changeset
|
691 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
|
9d10669f2579
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Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
692 src = FBUF_SHADOW; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
693 } |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
694 if (*sprite_buf & 0xF) { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
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232
diff
changeset
|
695 pixel = *sprite_buf; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
696 if (*sprite_buf & 0xF == 0xE) { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
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232
diff
changeset
|
697 src = FBUF_SRC_S; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
698 } else { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
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232
diff
changeset
|
699 src |= FBUF_SRC_S; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
700 } |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
701 } else if (*plane_a & 0xF) { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
702 pixel = *plane_a; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
703 src |= a_src; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
704 } else if (*plane_b & 0xF){ |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
705 pixel = *plane_b; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
706 src |= FBUF_SRC_B; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
707 } else { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
708 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
709 src |= FBUF_SRC_BG; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
710 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
711 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
712 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
713 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
715 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
716 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
717 uint8_t pixel; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
718 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
719 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
720 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
721 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
722 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
723 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
724 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
725 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
726 src = FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
727 } else if (*sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
728 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
729 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
730 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
731 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
732 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
733 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
734 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
735 src = FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
736 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
737 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
738 src = FBUF_SRC_BG; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
739 } |
|
291
eea3b118940d
Make sure all rendering operations mask CRAM with 0xEEE before using it
Mike Pavone <pavone@retrodev.com>
parents:
233
diff
changeset
|
740 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
741 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 } else { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 //dst = context->framebuf + line * 320; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 //sprite_buf = context->linebuf + col * 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 //end = dst + 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 |
| 40 | 751 uint16_t remaining; |
| 752 if (!(context->flags & FLAG_WINDOW)) { | |
| 753 remaining = context->hscroll_a & 0xF; | |
| 754 memcpy(context->tmp_buf_a + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_a + SCROLL_BUFFER_SIZE - remaining, remaining); | |
| 755 } | |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
756 remaining = context->hscroll_b & 0xF; |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
757 memcpy(context->tmp_buf_b + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_b + SCROLL_BUFFER_SIZE - remaining, remaining); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 external_slot(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
776 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
777 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
778 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 uint16_t address; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 uint32_t mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 case 0: |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
819 context->cur_slot = MAX_DRAWS-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 memset(context->linebuf, 0, LINEBUF_SIZE); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 case 2: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
824 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
825 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
826 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
827 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
828 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 //sprite attribute table scan starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 case 4: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
832 render_sprite_cells( context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 context->sprite_index = 0x80; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 context->slot_counter = MAX_SPRITES_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 case 13: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 case 14: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 case 19: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 //!HSYNC asserted |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 case 22: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
856 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case 26: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 case 27: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 case 28: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 case 31: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 case 32: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 case 33: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 case 34: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
873 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 case 35: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 mask = 0; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 if (context->regs[REG_MODE_3] & 0x2) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 mask |= 0xF8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 if (context->regs[REG_MODE_3] & 0x1) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 mask |= 0x7; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 line &= mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 address += line * 4; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
889 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 case 36: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 //!HSYNC high |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 case 37: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 case 38: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case 39: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
896 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 case 40: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 read_map_scroll_a(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 case 41: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
903 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 case 42: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 render_map_1(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 case 43: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 render_map_2(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 case 44: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 read_map_scroll_b(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 case 45: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
918 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 case 46: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 render_map_3(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 case 47: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 render_map_output(line, 0, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 //reverse context slot counter so it counts the number of sprite slots |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 //filled rather than the number of available slots |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
930 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
|
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
931 context->cur_slot = MAX_SPRITES_LINE-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 context->sprite_draws = MAX_DRAWS; |
|
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
933 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 COLUMN_RENDER_BLOCK(2, 48) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 COLUMN_RENDER_BLOCK(4, 56) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 COLUMN_RENDER_BLOCK(6, 64) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 COLUMN_RENDER_BLOCK(10, 80) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 COLUMN_RENDER_BLOCK(12, 88) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 COLUMN_RENDER_BLOCK(14, 96) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 COLUMN_RENDER_BLOCK(18, 112) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 COLUMN_RENDER_BLOCK(20, 120) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 COLUMN_RENDER_BLOCK(22, 128) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 COLUMN_RENDER_BLOCK(26, 144) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 COLUMN_RENDER_BLOCK(28, 152) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 COLUMN_RENDER_BLOCK(30, 160) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 COLUMN_RENDER_BLOCK(34, 176) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 COLUMN_RENDER_BLOCK(36, 184) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 COLUMN_RENDER_BLOCK(38, 192) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 case 208: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 case 209: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 default: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 //leftovers from HSYNC clock change nonsense |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 { |
| 37 | 967 uint16_t address; |
| 968 uint32_t mask; | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 case 0: |
| 37 | 973 context->cur_slot = MAX_DRAWS_H32-1; |
| 974 memset(context->linebuf, 0, LINEBUF_SIZE); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 case 2: |
| 37 | 977 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
978 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
979 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
980 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
981 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
982 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 break; |
| 37 | 984 //sprite attribute table scan starts |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 case 4: |
| 37 | 986 render_sprite_cells( context); |
| 987 context->sprite_index = 0x80; | |
| 988 context->slot_counter = MAX_SPRITES_LINE_H32; | |
| 989 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 case 13: |
| 37 | 1000 render_sprite_cells(context); |
| 1001 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 case 14: |
| 37 | 1003 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 case 19: |
| 37 | 1010 //HSYNC start |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 case 22: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 case 26: |
| 37 | 1018 render_sprite_cells(context); |
| 1019 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 case 27: |
| 37 | 1022 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 case 28: |
| 37 | 1025 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
| 1026 mask = 0; | |
| 1027 if (context->regs[REG_MODE_3] & 0x2) { | |
| 1028 mask |= 0xF8; | |
| 1029 } | |
| 1030 if (context->regs[REG_MODE_3] & 0x1) { | |
| 1031 mask |= 0x7; | |
| 1032 } | |
| 1033 line &= mask; | |
| 1034 address += line * 4; | |
| 1035 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
| 1036 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
| 1037 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 case 31: |
| 37 | 1042 case 32: |
| 1043 render_sprite_cells(context); | |
| 1044 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 break; |
| 37 | 1046 //!HSYNC high |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 case 33: |
| 37 | 1048 read_map_scroll_a(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1049 break; |
|
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diff
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|
1050 case 34: |
| 37 | 1051 render_sprite_cells(context); |
| 1052 scan_sprite_table(line, context); | |
|
20
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|
1053 break; |
|
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diff
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|
1054 case 35: |
| 37 | 1055 render_map_1(context); |
| 1056 scan_sprite_table(line, context);//Just a guess | |
|
20
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|
1057 break; |
|
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|
1058 case 36: |
| 37 | 1059 render_map_2(context); |
| 1060 scan_sprite_table(line, context);//Just a guess | |
|
20
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|
1061 break; |
|
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|
1062 case 37: |
| 37 | 1063 read_map_scroll_b(0, line, context); |
|
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diff
changeset
|
1064 break; |
|
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diff
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|
1065 case 38: |
| 37 | 1066 render_sprite_cells(context); |
| 1067 scan_sprite_table(line, context); | |
|
20
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diff
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|
1068 break; |
|
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diff
changeset
|
1069 case 39: |
| 37 | 1070 render_map_3(context); |
| 1071 scan_sprite_table(line, context);//Just a guess | |
|
20
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diff
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|
1072 break; |
|
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diff
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|
1073 case 40: |
| 37 | 1074 render_map_output(line, 0, context); |
| 1075 scan_sprite_table(line, context);//Just a guess | |
| 1076 //reverse context slot counter so it counts the number of sprite slots | |
| 1077 //filled rather than the number of available slots | |
| 1078 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
| 1079 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
| 1080 context->sprite_draws = MAX_DRAWS_H32; | |
| 1081 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
|
20
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diff
changeset
|
1082 break; |
| 37 | 1083 COLUMN_RENDER_BLOCK(2, 41) |
| 1084 COLUMN_RENDER_BLOCK(4, 49) | |
| 1085 COLUMN_RENDER_BLOCK(6, 57) | |
| 1086 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
| 1087 COLUMN_RENDER_BLOCK(10, 73) | |
| 1088 COLUMN_RENDER_BLOCK(12, 81) | |
| 1089 COLUMN_RENDER_BLOCK(14, 89) | |
| 1090 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
| 1091 COLUMN_RENDER_BLOCK(18, 105) | |
| 1092 COLUMN_RENDER_BLOCK(20, 113) | |
| 1093 COLUMN_RENDER_BLOCK(22, 121) | |
| 1094 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
| 1095 COLUMN_RENDER_BLOCK(26, 137) | |
| 1096 COLUMN_RENDER_BLOCK(28, 145) | |
| 1097 COLUMN_RENDER_BLOCK(30, 153) | |
| 1098 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
|
20
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|
1099 case 169: |
|
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diff
changeset
|
1100 case 170: |
| 37 | 1101 external_slot(context); |
|
20
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|
1102 break; |
|
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parents:
diff
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|
1103 } |
|
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|
1104 } |
|
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|
1105 void latch_mode(vdp_context * context) |
|
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|
1106 { |
|
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|
1107 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
|
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diff
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|
1108 } |
|
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|
1109 |
|
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|
1110 int is_refresh(vdp_context * context, uint32_t slot) |
|
54
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|
1111 { |
|
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|
1112 if (context->latched_mode & BIT_H40) { |
|
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1113 //TODO: Figure out the exact behavior that reduces DMA slots for direct color DMA demos |
|
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1114 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210 || (slot < 6 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
54
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|
1115 } else { |
|
189
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|
1116 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
|
191
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1117 //These numbers are guesses based on H40 numbers |
|
330
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|
1118 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152 || (slot < 5 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
189
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|
1119 //The numbers below are the refresh slots during active display |
|
330
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|
1120 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
|
54
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diff
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|
1121 } |
|
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|
1122 } |
|
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diff
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|
1123 |
|
330
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|
1124 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
|
54
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43
diff
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|
1125 { |
|
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43
diff
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|
1126 if (line > 0) { |
|
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43
diff
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|
1127 line -= 1; |
|
3b79cbcf6846
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43
diff
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|
1128 uint16_t * start = NULL, *end = NULL; |
|
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43
diff
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|
1129 if (context->latched_mode & BIT_H40) { |
|
330
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|
1130 if (slot >= 50 && slot < 210) { |
|
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|
1131 uint32_t x = (slot-50)*2; |
|
54
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43
diff
changeset
|
1132 start = context->framebuf + line * 320 + x; |
|
190
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189
diff
changeset
|
1133 end = start + 2; |
|
54
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diff
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|
1134 } |
|
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diff
changeset
|
1135 } else { |
|
330
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|
1136 if (slot >= 43 && slot < 171) { |
|
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329
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|
1137 uint32_t x = (slot-43)*2; |
|
191
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190
diff
changeset
|
1138 start = context->framebuf + line * 320 + x; |
|
190
4cb8a3891e26
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189
diff
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|
1139 end = start + 2; |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1140 } |
|
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43
diff
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|
1141 } |
|
291
eea3b118940d
Make sure all rendering operations mask CRAM with 0xEEE before using it
Mike Pavone <pavone@retrodev.com>
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233
diff
changeset
|
1142 uint16_t color = (context->cram[context->regs[REG_BG_COLOR] & 0x3F] & 0xEEE); |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1143 while (start != end) { |
|
189
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Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
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diff
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|
1144 *start = color; |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1145 ++start; |
|
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1146 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1147 } |
|
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1148 } |
|
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Get Flavio's color bar demo kind of sort of working
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diff
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|
1149 |
|
20
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diff
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|
1150 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
|
f664eeb55cb4
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parents:
diff
changeset
|
1151 { |
|
f664eeb55cb4
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parents:
diff
changeset
|
1152 while(context->cycles < target_cycles) |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1153 { |
|
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parents:
diff
changeset
|
1154 uint32_t line = context->cycles / MCLKS_LINE; |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1155 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
334
4c91470e1a53
Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents:
333
diff
changeset
|
1156 if (!context->cycles) { |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1157 latch_mode(context); |
|
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43
diff
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|
1158 } |
|
317
e5e8b48ad157
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291
diff
changeset
|
1159 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
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291
diff
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|
1160 if (linecyc == 0) { |
|
e5e8b48ad157
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291
diff
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|
1161 if (line <= 1 || line >= active_lines) { |
|
e5e8b48ad157
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diff
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|
1162 context->hint_counter = context->regs[REG_HINT]; |
|
e5e8b48ad157
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291
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|
1163 } else if (context->hint_counter) { |
|
e5e8b48ad157
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291
diff
changeset
|
1164 context->hint_counter--; |
|
e5e8b48ad157
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291
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|
1165 } else { |
|
e5e8b48ad157
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|
1166 context->flags2 |= FLAG2_HINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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|
1167 context->hint_counter = context->regs[REG_HINT]; |
|
e5e8b48ad157
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diff
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|
1168 } |
|
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
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291
diff
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|
1169 } else if(line == active_lines) { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
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330
diff
changeset
|
1170 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
|
317
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diff
changeset
|
1171 if (linecyc == intcyc) { |
|
e5e8b48ad157
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291
diff
changeset
|
1172 context->flags2 |= FLAG2_VINT_PENDING; |
|
e5e8b48ad157
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291
diff
changeset
|
1173 } |
|
e5e8b48ad157
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291
diff
changeset
|
1174 } |
|
330
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|
1175 uint32_t inccycles, slot; |
|
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|
1176 if (context->latched_mode & BIT_H40){ |
|
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|
1177 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
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|
1178 slot = linecyc/MCLKS_SLOT_H40; |
|
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|
1179 inccycles = MCLKS_SLOT_H40; |
|
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|
1180 } else if(linecyc < MCLK_WEIRD_END) { |
|
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diff
changeset
|
1181 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1182 { |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1183 case 0: |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1184 inccycles = 19; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1185 slot = 0; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1186 break; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1187 case 19: |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1188 slot = 1; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1189 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1190 break; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1191 case 39: |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1192 slot = 2; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1193 inccycles = 20; |
|
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329
diff
changeset
|
1194 break; |
|
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329
diff
changeset
|
1195 case 59: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1196 slot = 3; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1197 inccycles = 20; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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diff
changeset
|
1198 break; |
|
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329
diff
changeset
|
1199 case 79: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
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parents:
331
diff
changeset
|
1200 slot = 4; |
|
330
57453d3d8be4
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329
diff
changeset
|
1201 inccycles = 18; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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diff
changeset
|
1202 break; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1203 case 97: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1204 slot = 5; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1205 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1206 break; |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1207 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1208 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1209 inccycles = 20; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1210 break; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1211 case 137: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1212 slot = 7; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1213 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1214 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1215 case 157: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1216 slot = 8; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1217 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1218 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1219 case 175: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1220 slot = 9; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1221 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1222 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1223 case 195: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1224 slot = 10; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1225 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1226 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1227 case 215: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1228 slot = 11; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1229 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1230 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1231 case 235: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1232 slot = 12; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1233 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1234 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1235 case 253: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1236 slot = 13; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1237 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1238 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1239 case 273: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1240 slot = 14; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1241 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1242 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1243 case 293: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1244 slot = 15; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1245 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1246 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1247 case 313: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1248 slot = 16; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1249 inccycles = 19; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1250 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1251 default: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1252 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1253 exit(1); |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1254 } |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1255 slot += HSYNC_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1256 } else { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1257 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1258 inccycles = MCLKS_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1259 } |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1260 } else { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1261 inccycles = MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1262 slot = linecyc/MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1263 } |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1264 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1265 //first sort-of active line is treated as 255 internally |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1266 //it's used for gathering sprite info for line |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1267 line = (line - 1) & 0xFF; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1268 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1269 //Convert to slot number |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1270 if (context->latched_mode & BIT_H40){ |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1271 vdp_h40(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1272 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1273 vdp_h32(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1274 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1275 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1276 if (!is_refresh(context, slot)) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1277 external_slot(context); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1278 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1279 if (line < active_lines) { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1280 check_render_bg(context, line, slot); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1281 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1282 } |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1283 context->cycles += inccycles; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1284 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1285 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1286 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1287 uint32_t vdp_run_to_vblank(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1288 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1289 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1290 vdp_run_context(context, target_cycles); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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|
1291 return context->cycles; |
|
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1292 } |
|
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1293 |
| 75 | 1294 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
| 1295 { | |
| 1296 for(;;) { | |
| 1297 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
| 1298 if (!dmalen) { | |
| 1299 dmalen = 0x10000; | |
| 1300 } | |
| 1301 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
| 1302 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
| 1303 //DMA copies take twice as long to complete since they require a read and a write | |
| 1304 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
| 1305 min_dma_complete *= 2; | |
| 1306 } | |
| 1307 min_dma_complete += context->cycles; | |
| 1308 if (target_cycles < min_dma_complete) { | |
| 1309 vdp_run_context(context, target_cycles); | |
| 1310 return; | |
| 1311 } else { | |
| 1312 vdp_run_context(context, min_dma_complete); | |
| 1313 if (!(context->flags & FLAG_DMA_RUN)) { | |
| 1314 return; | |
| 1315 } | |
| 1316 } | |
| 1317 } | |
| 1318 } | |
| 1319 | |
| 1320 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
|
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|
1321 { |
|
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|
1322 //printf("control port write: %X\n", value); |
|
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1323 if (context->flags & FLAG_DMA_RUN) { |
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|
1324 return -1; |
|
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1325 } |
|
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|
1326 if (context->flags & FLAG_PENDING) { |
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1327 context->address = (context->address & 0x3FFF) | (value << 14); |
|
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1328 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
| 75 | 1329 context->flags &= ~FLAG_PENDING; |
|
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|
1330 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
|
327
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1331 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
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1332 // |
| 75 | 1333 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
| 1334 //DMA copy or 68K -> VDP, transfer starts immediately | |
| 1335 context->flags |= FLAG_DMA_RUN; | |
|
131
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|
1336 context->dma_cd = context->cd; |
| 75 | 1337 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
|
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1338 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
| 75 | 1339 return 1; |
|
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1340 } else { |
|
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1341 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
| 75 | 1342 } |
|
327
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1343 } else { |
|
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|
1344 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
| 75 | 1345 } |
|
63
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diff
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|
1346 } |
|
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1347 } else { |
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1348 if ((value & 0xC000) == 0x8000) { |
|
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1349 //Register write |
|
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|
1350 uint8_t reg = (value >> 8) & 0x1F; |
|
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|
1351 if (reg < VDP_REGS) { |
|
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|
1352 //printf("register %d set to %X\n", reg, value & 0xFF); |
|
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|
1353 context->regs[reg] = value; |
|
151
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|
1354 if (reg == REG_MODE_2) { |
|
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|
1355 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
|
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|
1356 } |
|
413
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|
1357 if (reg == REG_MODE_4) { |
|
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|
1358 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
|
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
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|
1359 if (!context->double_res) { |
|
8c60c8c09a0f
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|
1360 context->framebuf = context->oddbuf; |
|
8c60c8c09a0f
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|
1361 } |
|
413
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|
1362 } |
|
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1363 } |
|
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|
1364 } else { |
|
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|
1365 context->flags |= FLAG_PENDING; |
|
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1366 context->address = (context->address &0xC000) | (value & 0x3FFF); |
|
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|
1367 context->cd = (context->cd &0x3C) | (value >> 14); |
|
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1368 } |
|
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1369 } |
| 75 | 1370 return 0; |
|
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1371 } |
|
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|
1372 |
|
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|
1373 int vdp_data_port_write(vdp_context * context, uint16_t value) |
|
54
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|
1374 { |
|
58
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|
1375 //printf("data port write: %X\n", value); |
|
149
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|
1376 if (context->flags & FLAG_DMA_RUN) { |
|
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|
1377 return -1; |
|
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|
1378 } |
|
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|
1379 if (!(context->cd & 1)) { |
|
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|
1380 //ignore writes when cd is configured for read |
|
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|
1381 return 0; |
|
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|
1382 } |
|
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|
1383 context->flags &= ~FLAG_PENDING; |
|
109
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|
1384 /*if (context->fifo_cur == context->fifo_end) { |
|
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|
1385 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
|
109
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|
1386 }*/ |
|
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|
1387 while (context->fifo_cur == context->fifo_end) { |
|
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|
1388 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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|
1389 } |
|
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|
1390 context->fifo_cur->cycle = context->cycles; |
| 138 | 1391 context->fifo_cur->address = context->address; |
|
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|
1392 context->fifo_cur->value = value; |
| 138 | 1393 context->fifo_cur->cd = context->cd; |
|
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|
1394 context->fifo_cur->partial = 0; |
|
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|
1395 context->fifo_cur++; |
| 138 | 1396 context->address += context->regs[REG_AUTOINC]; |
|
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1397 return 0; |
|
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1398 } |
|
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1399 |
|
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|
1400 uint16_t vdp_control_port_read(vdp_context * context) |
|
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1401 { |
|
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1402 context->flags &= ~FLAG_PENDING; |
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1403 uint16_t value = 0x3400; |
|
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1404 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
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1405 value |= 0x200; |
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1406 } |
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1407 if (context->fifo_cur == context->fifo_end) { |
|
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|
1408 value |= 0x100; |
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1409 } |
|
317
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|
1410 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
413
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|
1411 value |= 0x80; |
|
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|
1412 } |
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|
1413 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
|
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1414 value |= 0x10; |
|
317
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1415 } |
|
318
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|
1416 uint32_t line= context->cycles / MCLKS_LINE; |
|
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1417 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
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1418 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
|
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1419 value |= 0x8; |
|
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1420 } |
|
331
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|
1421 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
|
318
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1422 value |= 0x4; |
|
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1423 } |
|
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1424 if (context->flags & FLAG_DMA_RUN) { |
|
141
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Fix DMA in progress flag in VDP status register
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parents:
138
diff
changeset
|
1425 value |= 0x2; |
| 75 | 1426 } |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1427 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1428 value |= 0x1; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1429 } |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1430 //TODO: Sprite overflow, sprite collision, odd frame flag |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1431 return value; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1432 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1433 |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1434 uint16_t vdp_data_port_read(vdp_context * context) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1435 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1436 context->flags &= ~FLAG_PENDING; |
| 138 | 1437 if (context->cd & 1) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1438 return 0; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1439 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1440 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1441 context->flags &= ~FLAG_UNUSED_SLOT; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1442 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1443 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1444 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1445 uint16_t value = 0; |
| 138 | 1446 switch (context->cd & 0xF) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1447 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1448 case VRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1449 value = context->vdpmem[context->address] << 8; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1450 context->flags &= ~FLAG_UNUSED_SLOT; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1451 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1452 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1453 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1454 value |= context->vdpmem[context->address ^ 1]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1455 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1456 case CRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1457 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1458 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1459 case VSRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1460 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1461 value = context->vsram[context->address & 63]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1462 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1463 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1464 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1465 context->address += context->regs[REG_AUTOINC]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1466 return value; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1467 } |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1468 |
| 137 | 1469 uint16_t vdp_hv_counter_read(vdp_context * context) |
| 1470 { | |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1471 //TODO: deal with clock adjustemnts handled in vdp_run_context |
| 137 | 1472 uint32_t line= context->cycles / MCLKS_LINE; |
| 1473 if (!line) { | |
| 1474 line = 0xFF; | |
| 1475 } else { | |
| 1476 line--; | |
| 1477 if (line > 0xEA) { | |
| 1478 line = (line + 0xFA) & 0xFF; | |
| 1479 } | |
| 1480 } | |
| 1481 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
| 1482 if (context->latched_mode & BIT_H40) { | |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1483 uint32_t slot; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1484 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1485 slot = linecyc/MCLKS_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1486 } else if(linecyc < MCLK_WEIRD_END) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1487 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1488 { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1489 case 0: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1490 slot = 0; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1491 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1492 case 19: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1493 slot = 1; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1494 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1495 case 39: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1496 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1497 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1498 case 59: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1499 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1500 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1501 case 79: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1502 slot = 3; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1503 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1504 case 97: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1505 slot = 4; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1506 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1507 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1508 slot = 5; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1509 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1510 case 137: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1511 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1512 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1513 case 157: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1514 slot = 7; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1515 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1516 case 175: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1517 slot = 8; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1518 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1519 case 195: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1520 slot = 9; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1521 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1522 case 215: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1523 slot = 11; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1524 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1525 case 235: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1526 slot = 12; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1527 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1528 case 253: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1529 slot = 13; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1530 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1531 case 273: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1532 slot = 14; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1533 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1534 case 293: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1535 slot = 15; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1536 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1537 case 313: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1538 slot = 16; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1539 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1540 default: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1541 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1542 exit(1); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1543 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1544 slot += HSYNC_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1545 } else { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1546 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1547 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1548 linecyc = slot * 2; |
| 137 | 1549 if (linecyc >= 86) { |
| 1550 linecyc -= 86; | |
| 1551 } else { | |
| 1552 linecyc += 334; | |
| 1553 } | |
| 1554 if (linecyc > 0x16C) { | |
| 1555 linecyc += 92; | |
| 1556 } | |
| 1557 } else { | |
| 1558 linecyc /= 10; | |
| 1559 if (linecyc >= 74) { | |
| 1560 linecyc -= 74; | |
| 1561 } else { | |
| 1562 linecyc += 268; | |
| 1563 } | |
| 1564 if (linecyc > 0x127) { | |
| 1565 linecyc += 170; | |
| 1566 } | |
| 1567 } | |
| 1568 linecyc &= 0xFF; | |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1569 if (context->double_res) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1570 line <<= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1571 if (line & 0x100) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1572 line |= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1573 } |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1574 } |
| 137 | 1575 return (line << 8) | linecyc; |
| 1576 } | |
| 1577 | |
|
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1578 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1579 { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1580 context->cycles -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1581 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1582 if (start->cycle >= deduction) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1583 start->cycle -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1584 } else { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1585 start->cycle = 0; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1586 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1587 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1588 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1589 |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1590 uint32_t vdp_next_hint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1591 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1592 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1593 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1594 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1595 if (context->flags2 & FLAG2_HINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1596 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1597 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1598 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1599 uint32_t line = context->cycles / MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1600 if (line >= active_lines) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1601 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1602 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1603 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1604 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1605 if (!line) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1606 hcycle += MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1607 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1608 return hcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1609 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1610 |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1611 uint32_t vdp_next_vint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1612 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1613 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1614 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1615 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1616 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1617 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1618 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1619 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1620 uint32_t vcycle = MCLKS_LINE * active_lines; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1621 if (context->latched_mode & BIT_H40) { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1622 vcycle += VINT_CYCLE_H40; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1623 } else { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1624 vcycle += VINT_CYCLE_H32; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1625 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1626 if (vcycle < context->cycles) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1627 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1628 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1629 return vcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1630 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1631 |
| 333 | 1632 uint32_t vdp_next_vint_z80(vdp_context * context) |
| 1633 { | |
| 1634 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
| 1635 uint32_t vcycle = MCLKS_LINE * active_lines; | |
| 1636 if (context->latched_mode & BIT_H40) { | |
| 1637 vcycle += VINT_CYCLE_H40; | |
| 1638 } else { | |
| 1639 vcycle += VINT_CYCLE_H32; | |
| 1640 } | |
| 1641 return vcycle; | |
| 1642 } | |
| 1643 | |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1644 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1645 { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1646 if (int_num == 6) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1647 context->flags2 &= ~FLAG2_VINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1648 } else if(int_num ==4) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1649 context->flags2 &= ~FLAG2_HINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1650 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1651 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1652 |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1653 #define GST_VDP_REGS 0xFA |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1654 #define GST_VDP_MEM 0x12478 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1655 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1656 void vdp_load_savestate(vdp_context * context, FILE * state_file) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1657 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1658 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1659 fseek(state_file, GST_VDP_REGS, SEEK_SET); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1660 fread(context->regs, 1, VDP_REGS, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1661 latch_mode(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1662 fread(tmp_buf, 1, sizeof(tmp_buf), state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1663 for (int i = 0; i < CRAM_SIZE; i++) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1664 context->cram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1665 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1666 fread(tmp_buf, 2, VSRAM_SIZE, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1667 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
23
3e924bb56560
Fix endianness of VSRAM when read from Genecyst save state
Mike Pavone <pavone@retrodev.com>
parents:
22
diff
changeset
|
1668 context->vsram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1669 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1670 fseek(state_file, GST_VDP_MEM, SEEK_SET); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1671 fread(context->vdpmem, 1, VRAM_SIZE, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1672 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1673 |
|
56
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1674 void vdp_save_state(vdp_context * context, FILE * outfile) |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1675 { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1676 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1677 fseek(outfile, GST_VDP_REGS, SEEK_SET); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1678 fwrite(context->regs, 1, VDP_REGS, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1679 for (int i = 0; i < CRAM_SIZE; i++) { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1680 tmp_buf[i*2] = context->cram[i]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1681 tmp_buf[i*2+1] = context->cram[i] >> 8; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1682 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
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1683 fwrite(tmp_buf, 1, sizeof(tmp_buf), outfile); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
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1684 for (int i = 0; i < VSRAM_SIZE; i++) { |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1685 tmp_buf[i*2] = context->vsram[i]; |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1686 tmp_buf[i*2+1] = context->vsram[i] >> 8; |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1687 } |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1688 fwrite(tmp_buf, 2, VSRAM_SIZE, outfile); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1689 fseek(outfile, GST_VDP_MEM, SEEK_SET); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1690 fwrite(context->vdpmem, 1, VRAM_SIZE, outfile); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1691 } |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1692 |