annotate vdp.c @ 415:8c60c8c09a0f

Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
author Mike Pavone <pavone@retrodev.com>
date Sun, 23 Jun 2013 10:17:40 -0700
parents 51ee0f117365
children acdd6c5240fe
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 #include "vdp.h"
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2 #include "blastem.h"
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 #include <stdlib.h>
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 #include <string.h>
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #define NTSC_ACTIVE 225
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 #define PAL_ACTIVE 241
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 #define BUF_BIT_PRIORITY 0x40
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 #define MAP_BIT_PRIORITY 0x8000
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10 #define MAP_BIT_H_FLIP 0x800
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 #define MAP_BIT_V_FLIP 0x1000
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
13 #define SCROLL_BUFFER_SIZE 32
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
14 #define SCROLL_BUFFER_DRAW 16
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
15
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
16 #define FIFO_SIZE 4
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
17
328
bf7ed23efa40 Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents: 327
diff changeset
18 #define MCLKS_SLOT_H40 16
bf7ed23efa40 Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents: 327
diff changeset
19 #define MCLKS_SLOT_H32 20
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
20 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
21 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
22 #define HSYNC_SLOT_H40 21
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
23 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332)
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
24 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17)
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
25 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32)
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
26 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4)
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
27 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5)
328
bf7ed23efa40 Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents: 327
diff changeset
28
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 void init_vdp_context(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 {
58
a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents: 56
diff changeset
31 memset(context, 0, sizeof(*context));
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 context->vdpmem = malloc(VRAM_SIZE);
58
a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents: 56
diff changeset
33 memset(context->vdpmem, 0, VRAM_SIZE);
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
34 context->oddbuf = context->framebuf = malloc(FRAMEBUF_SIZE);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
35 memset(context->framebuf, 0, FRAMEBUF_SIZE);
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
36 context->evenbuf = malloc(FRAMEBUF_SIZE);
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
37 memset(context->evenbuf, 0, FRAMEBUF_SIZE);
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
38 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
39 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
41 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
42 context->sprite_draws = MAX_DRAWS;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
43 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
44 context->fifo_end = context->fifo_cur + FIFO_SIZE;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
47 void render_sprite_cells(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 {
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
49 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
50 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
51
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
60 }
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
61 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
62 context->cur_slot--;
143
e5487ef04619 Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents: 142
diff changeset
63 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
64 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
65 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
66 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
67 x += dir;
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
68 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
70 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
71 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
72 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
73 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
74 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
75
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
76 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
77 {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
78 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
79 uint16_t current_index = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
80 uint8_t count = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
81 do {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
82 uint16_t address = current_index * 8 + sat_address;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
83 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
84 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
85 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
86 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF;
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
87 uint16_t link = context->vdpmem[address+3] & 0x7F;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
88 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
89 uint8_t pri = context->vdpmem[address + 4] >> 7;
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
90 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5;
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
91 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
92 current_index = link;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
93 count++;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
94 } while (current_index != 0 && count < 80);
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
95 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
96
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
97 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
98 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
99 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
100 printf("**Mode Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
101 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
102 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
103 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
104 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
105 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
106 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
107 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
108 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
109 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
110 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
111 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
112 printf("\n**Table Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
113 "02: %.2X | Scroll A Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
114 "03: %.2X | Window Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
115 "04: %.2X | Scroll B Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
116 "05: %.2X | Sprite Attribute Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
117 "0D: %.2X | HScroll Data Table: $%.4X\n",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
118 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
119 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
120 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
121 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
122 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10);
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
123 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
124 printf("\n**Misc Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
125 "07: %.2X | Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
126 "0A: %.2X | H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
127 "0F: %.2X | Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
128 "10: %.2X | Scroll A/B Size: %sx%s\n",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
129 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
130 context->regs[REG_HINT], context->regs[REG_HINT],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
131 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
132 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
133
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
134 //TODO: Window Group, DMA Group
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
135 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
136
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
137 void scan_sprite_table(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
139 if (context->sprite_index && context->slot_counter) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
141 line &= 0xFF;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
142 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
143 uint8_t height_mult;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
144 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
145 line *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
146 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
147 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
148 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
149 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
150 ymin = 256;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
151 height_mult = 16;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
152 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
153 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
154 ymin = 128;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
155 height_mult = 8;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
156 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
157 context->sprite_index &= 0x7F;
38
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
158 if (context->latched_mode & BIT_H40) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
159 if (context->sprite_index >= MAX_SPRITES_FRAME) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
160 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
161 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
162 }
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
163 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
164 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
165 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
166 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
167 //TODO: Read from SAT cache rather than from VRAM
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
168 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
169 uint16_t address = context->sprite_index * 8 + sat_address;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
170 line += ymin;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
171 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
172 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
173 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
174 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
175 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
178 context->sprite_info_list[context->slot_counter].y = y-ymin;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 context->sprite_index = context->vdpmem[address+3] & 0x7F;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 if (context->sprite_index && context->slot_counter)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 address = context->sprite_index * 8 + sat_address;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
184 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
185 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
186 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
187 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
188 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
191 context->sprite_info_list[context->slot_counter].y = y-ymin;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 }
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
193 context->sprite_index = context->vdpmem[address+3] & 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
195 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 void read_sprite_x(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
199 {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
200 if (context->cur_slot >= context->slot_counter) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
201 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
202 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
203 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
204 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
205 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
206 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
207 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
208 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
209 line *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
210 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
211 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
212 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
213 height *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
214 }
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
215 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
216 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1];
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
217 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
218 uint8_t row;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
219 if (tileinfo & MAP_BIT_V_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
220 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
221 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
222 row = line-context->sprite_info_list[context->cur_slot].y;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
223 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
224 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
225 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
226 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
227 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
228 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
229 }
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
230 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
231 if (x) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
232 context->flags |= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
233 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
234 context->flags |= FLAG_MASKED;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
235 }
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
236
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
237 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
238 int16_t i;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
239 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
240 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
241 --context->sprite_draws;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
242 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
243 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
244 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
245 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
246 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
247 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
248 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
249 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
250 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
251 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
252 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
253 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
254 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35
233c7737c152 Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents: 34
diff changeset
255 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
256 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
257 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
258 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
259 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
260 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
261 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
262 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
263 if (i < width) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
264 context->flags |= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
265 }
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
266 context->cur_slot--;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
268 context->flags |= FLAG_DOT_OFLOW;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
270 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
271 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
272
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
273 #define VRAM_READ 0
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
274 #define VRAM_WRITE 1
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
275 #define CRAM_READ 8
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
276 #define CRAM_WRITE 3
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
277 #define VSRAM_READ 4
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
278 #define VSRAM_WRITE 5
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
279 #define DMA_START 0x20
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
280
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
281 void external_slot(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
283 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
284 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
285 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
286 if(context->flags & FLAG_DMA_RUN) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
287 uint16_t dma_len;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
288 switch(context->regs[REG_DMASRC_H] & 0xC0)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
289 {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
290 //68K -> VDP
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
291 case 0:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
292 case 0x40:
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
293 switch(context->dma_cd & 0xF)
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
294 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
295 case VRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
296 if (context->flags & FLAG_DMA_PROG) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
297 context->vdpmem[context->address ^ 1] = context->dma_val;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
298 context->flags &= ~FLAG_DMA_PROG;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
299 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
300 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
301 context->vdpmem[context->address] = context->dma_val >> 8;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
302 context->flags |= FLAG_DMA_PROG;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
303 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
304 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
305 case CRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
306 context->cram[(context->address/2) & (CRAM_SIZE-1)] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
307 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
308 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
309 case VSRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
310 if (((context->address/2) & 63) < VSRAM_SIZE) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
311 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
312 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
313 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
314 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
315 break;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
316 //Fill
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
317 case 0x80:
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
318 switch(context->dma_cd & 0xF)
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
319 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
320 case VRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
321 //Charles MacDonald's VDP doc says that the low byte gets written first
142
b42bcfa09cce Fix DMA fills to VRAM
Mike Pavone <pavone@retrodev.com>
parents: 141
diff changeset
322 context->vdpmem[context->address] = context->dma_val;
b42bcfa09cce Fix DMA fills to VRAM
Mike Pavone <pavone@retrodev.com>
parents: 141
diff changeset
323 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
324 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
325 case CRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
326 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val;
337
f8c6f8684cd6 Fix background color regsiter number
Mike Pavone <pavone@retrodev.com>
parents: 334
diff changeset
327 //printf("CRAM DMA Fill | %X set to %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->cycles);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
328 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
329 case VSRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
330 if (((context->address/2) & 63) < VSRAM_SIZE) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
331 context->vsram[(context->address/2) & 63] = context->dma_val;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
332 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
333 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
334 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
335 break;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
336 //Copy
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
337 case 0xC0:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
338 if (context->flags & FLAG_DMA_PROG) {
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
339 switch(context->dma_cd & 0xF)
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
340 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
341 case VRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
342 context->vdpmem[context->address] = context->dma_val;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
343 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
344 case CRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
345 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val;
337
f8c6f8684cd6 Fix background color regsiter number
Mike Pavone <pavone@retrodev.com>
parents: 334
diff changeset
346 //printf("CRAM DMA Copy | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->regs[REG_DMASRC_L] & (CRAM_SIZE-1), context->cycles);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
347 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
348 case VSRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
349 if (((context->address/2) & 63) < VSRAM_SIZE) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
350 context->vsram[(context->address/2) & 63] = context->dma_val;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
351 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
352 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
353 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
354 context->flags &= ~FLAG_DMA_PROG;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
355 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
356 //I assume, that DMA copy copies from the same RAM as the destination
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
357 //but it's possible I'm mistaken
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
358 switch(context->dma_cd & 0xF)
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
359 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
360 case VRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
361 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
362 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
363 case CRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
364 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
365 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
366 case VSRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
367 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
368 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
369 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
370 context->dma_val = 0;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
371 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
372 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
373 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
374 context->flags |= FLAG_DMA_PROG;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
375 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
376 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
377 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
378 if (!(context->flags & FLAG_DMA_PROG)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
379 context->address += context->regs[REG_AUTOINC];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
380 context->regs[REG_DMASRC_L] += 1;
135
a81c548cf353 Fix 68K->VDP DMA
Mike Pavone <pavone@retrodev.com>
parents: 131
diff changeset
381 if (!context->regs[REG_DMASRC_L]) {
a81c548cf353 Fix 68K->VDP DMA
Mike Pavone <pavone@retrodev.com>
parents: 131
diff changeset
382 context->regs[REG_DMASRC_M] += 1;
a81c548cf353 Fix 68K->VDP DMA
Mike Pavone <pavone@retrodev.com>
parents: 131
diff changeset
383 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
384 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
385 context->regs[REG_DMALEN_H] = dma_len >> 8;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
386 context->regs[REG_DMALEN_L] = dma_len;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
387 if (!dma_len) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
388 context->flags &= ~FLAG_DMA_RUN;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
389 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
390 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
391 } else {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
392 fifo_entry * start = (context->fifo_end - FIFO_SIZE);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
393 if (context->fifo_cur != start && start->cycle <= context->cycles) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
394 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
395 context->flags |= FLAG_DMA_RUN;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
396 context->dma_val = start->value;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
397 context->address = start->address; //undo auto-increment
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
398 context->dma_cd = context->cd;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
399 } else {
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
400 switch (start->cd & 0xF)
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
401 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
402 case VRAM_WRITE:
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
403 if (start->partial) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
404 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1);
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
405 context->vdpmem[start->address ^ 1] = start->value;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
406 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
407 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address);
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
408 context->vdpmem[start->address] = start->value >> 8;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
409 start->partial = 1;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
410 //skip auto-increment and removal of entry from fifo
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
411 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
412 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
413 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
414 case CRAM_WRITE:
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
415 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
416 context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
417 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
418 case VSRAM_WRITE:
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
419 if (((start->address/2) & 63) < VSRAM_SIZE) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
420 //printf("VSRAM Write: %X to %X\n", start->value, context->address);
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
421 context->vsram[(start->address/2) & 63] = start->value;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
422 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
423 break;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
424 }
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
425 //context->address += context->regs[REG_AUTOINC];
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
426 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
427 fifo_entry * cur = start+1;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
428 if (cur < context->fifo_cur) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
429 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur));
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
430 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
431 context->fifo_cur -= 1;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
432 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
433 context->flags |= FLAG_UNUSED_SLOT;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
434 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
435 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
436 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
437
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
438 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
439 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
440
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
441 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
442 {
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
443 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
444 line *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
445 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
446 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
447 }
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
448 }
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
449 if (!vsram_off) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
450 uint16_t left_col, right_col;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
451 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
452 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
453 right_col = 42;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
454 } else {
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
455 left_col = 0;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
456 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
457 if (right_col) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
458 right_col += 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
459 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
460 }
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
461 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
462 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
463 top_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
464 bottom_line = 241;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
465 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
466 top_line = 0;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
467 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
468 }
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
469 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
470 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
471 uint16_t line_offset, offset, mask;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
472 if (context->latched_mode & BIT_H40) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
473 address &= 0xF000;
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
474 line_offset = (((line) / 8) * 64 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
475 mask = 0x7F;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
476
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
477 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
478 address &= 0xF800;
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
479 line_offset = (((line) / 8) * 32 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
480 mask = 0x3F;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
481 }
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
482 offset = address + line_offset + (((column - 2) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
483 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
484 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
485 offset = address + line_offset + (((column - 1) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
486 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
487 context->v_offset = (line) & 0x7;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
488 context->flags |= FLAG_WINDOW;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
489 return;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
490 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
491 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
492 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
493 uint16_t vscroll;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
494 switch(context->regs[REG_SCROLL] & 0x30)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
495 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
496 case 0:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
497 vscroll = 0xFF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
498 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
499 case 0x10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
500 vscroll = 0x1FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
501 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
502 case 0x20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
503 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
504 vscroll = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
505 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
506 case 0x30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
507 vscroll = 0x3FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
508 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
509 }
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
510 uint16_t v_offset_mask, vscroll_shift;
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
511 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
512 vscroll <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
513 vscroll |= 1;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
514 v_offset_mask = 0xF;
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
515 vscroll_shift = 4;
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
516 } else {
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
517 v_offset_mask = 0x7;
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
518 vscroll_shift = 3;
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
519 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
520 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? column : 0) + vsram_off] + line);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
521 context->v_offset = vscroll & v_offset_mask;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
522 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
523 vscroll >>= vscroll_shift;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
524 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
525 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
526 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
527 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
528 case 0:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
529 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
530 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
531 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
532 case 0x1:
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
533 hscroll_mask = 0x3F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
534 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
535 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
536 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
537 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
538 hscroll_mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
539 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
540 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
541 case 0x3:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
542 hscroll_mask = 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
543 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
544 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
545 }
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
546 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
547 for (int i = 0; i < 2; i++) {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
548 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
549 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
550 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
551 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
552 if (i) {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
553 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
554 } else {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
555 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
556 }
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
557 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
558 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
559
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
560 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
561 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
562 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
563 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
564
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
565 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
566 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
567 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
568 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
569
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
570 void render_map(uint16_t col, uint8_t * tmp_buf, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
571 {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
572 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
573 uint8_t shift, add;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
574 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
575 address = ((col & 0x3FF) << 6);
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
576 shift = 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
577 add = context->framebuf != context->oddbuf ? 1 : 0;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
578 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
579 address = ((col & 0x7FF) << 5);
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
580 shift = 0;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
581 add = 0;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
582 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
583 if (col & MAP_BIT_V_FLIP) {
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
584 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
585 } else {
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
586 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
587 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
588 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
589 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
590 if (col & MAP_BIT_H_FLIP) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
591 tmp_buf += 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
592 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
593 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
594 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
595 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
596 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
597 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
598 *tmp_buf = pal_priority | (context->vdpmem[address] >> 4);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
599 tmp_buf += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
600 *tmp_buf = pal_priority | (context->vdpmem[address] & 0xF);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
601 tmp_buf += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
602 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
603 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
604
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
605 void render_map_1(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
606 {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
607 render_map(context->col_1, context->tmp_buf_a+SCROLL_BUFFER_DRAW, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
608 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
609
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
610 void render_map_2(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
611 {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
612 render_map(context->col_2, context->tmp_buf_a+SCROLL_BUFFER_DRAW+8, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
613 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
614
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
615 void render_map_3(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
616 {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
617 render_map(context->col_1, context->tmp_buf_b+SCROLL_BUFFER_DRAW, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
618 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
619
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
620 void render_map_output(uint32_t line, int32_t col, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
621 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
622 if (line >= 240) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
623 return;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
624 }
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
625 render_map(context->col_2, context->tmp_buf_b+SCROLL_BUFFER_DRAW+8, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
626 uint16_t *dst, *end;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
627 uint8_t *sprite_buf, *plane_a, *plane_b;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
628 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
629 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
630 col-=2;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
631 dst = context->framebuf + line * 320 + col * 8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
632 sprite_buf = context->linebuf + col * 8;
43
3fc57e1a2c56 Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents: 42
diff changeset
633 uint16_t a_src;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
634 if (context->flags & FLAG_WINDOW) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
635 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW;
43
3fc57e1a2c56 Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents: 42
diff changeset
636 a_src = FBUF_SRC_W;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
637 } else {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
638 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW - (context->hscroll_a & 0xF);
43
3fc57e1a2c56 Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents: 42
diff changeset
639 a_src = FBUF_SRC_A;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
640 }
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
641 plane_b = context->tmp_buf_b + SCROLL_BUFFER_DRAW - (context->hscroll_b & 0xF);
30
03f9bb57cc54 Small cleanup
Mike Pavone <pavone@retrodev.com>
parents: 29
diff changeset
642 end = dst + 16;
43
3fc57e1a2c56 Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents: 42
diff changeset
643 uint16_t src;
30
03f9bb57cc54 Small cleanup
Mike Pavone <pavone@retrodev.com>
parents: 29
diff changeset
644 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
645
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
646 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
647 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
648 uint8_t pixel;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
649
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
650 src = 0;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
651 uint8_t sprite_color = *sprite_buf & 0x3F;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
652 if (sprite_color == 0x3E || sprite_color == 0x3F) {
232
54873acb982e Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents: 230
diff changeset
653 if (sprite_color == 0x3F) {
54873acb982e Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents: 230
diff changeset
654 src = FBUF_SHADOW;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
655 } else {
232
54873acb982e Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents: 230
diff changeset
656 src = FBUF_HILIGHT;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
657 }
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
658 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
659 pixel = *plane_a;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
660 src |= a_src;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
661 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
662 pixel = *plane_b;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
663 src |= FBUF_SRC_B;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
664 } else if (*plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
665 pixel = *plane_a;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
666 src |= a_src;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
667 } else if (*plane_b & 0xF){
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
668 pixel = *plane_b;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
669 src |= FBUF_SRC_B;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
670 } else {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
671 pixel = context->regs[REG_BG_COLOR] & 0x3F;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
672 src |= FBUF_SRC_BG;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
673 }
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
674 } else {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
675 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
676 pixel = *sprite_buf;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
677 src = FBUF_SRC_S;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
678 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
679 pixel = *plane_a;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
680 src = a_src;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
681 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
682 pixel = *plane_b;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
683 src = FBUF_SRC_B;
233
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
684 } else {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
685 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
686 src = FBUF_SHADOW;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
687 }
233
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
688 if (*sprite_buf & 0xF) {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
689 pixel = *sprite_buf;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
690 if (*sprite_buf & 0xF == 0xE) {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
691 src = FBUF_SRC_S;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
692 } else {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
693 src |= FBUF_SRC_S;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
694 }
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
695 } else if (*plane_a & 0xF) {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
696 pixel = *plane_a;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
697 src |= a_src;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
698 } else if (*plane_b & 0xF){
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
699 pixel = *plane_b;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
700 src |= FBUF_SRC_B;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
701 } else {
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
702 pixel = context->regs[REG_BG_COLOR] & 0x3F;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
703 src |= FBUF_SRC_BG;
9d10669f2579 Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents: 232
diff changeset
704 }
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
705 }
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
706 }
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
707 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
708 }
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
709 } else {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
710 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
711 uint8_t pixel;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
712 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
713 pixel = *sprite_buf;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
714 src = FBUF_SRC_S;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
715 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
716 pixel = *plane_a;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
717 src = a_src;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
718 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
719 pixel = *plane_b;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
720 src = FBUF_SRC_B;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
721 } else if (*sprite_buf & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
722 pixel = *sprite_buf;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
723 src = FBUF_SRC_S;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
724 } else if (*plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
725 pixel = *plane_a;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
726 src = a_src;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
727 } else if (*plane_b & 0xF){
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
728 pixel = *plane_b;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
729 src = FBUF_SRC_B;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
730 } else {
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
731 pixel = context->regs[REG_BG_COLOR] & 0x3F;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
732 src = FBUF_SRC_BG;
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
733 }
291
eea3b118940d Make sure all rendering operations mask CRAM with 0xEEE before using it
Mike Pavone <pavone@retrodev.com>
parents: 233
diff changeset
734 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
735 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
736 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
737 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
738 //dst = context->framebuf + line * 320;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
739 //sprite_buf = context->linebuf + col * 8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
740 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
741 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
742 //end = dst + 8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
743 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
744
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
745 uint16_t remaining;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
746 if (!(context->flags & FLAG_WINDOW)) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
747 remaining = context->hscroll_a & 0xF;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
748 memcpy(context->tmp_buf_a + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_a + SCROLL_BUFFER_SIZE - remaining, remaining);
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
749 }
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
750 remaining = context->hscroll_b & 0xF;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
751 memcpy(context->tmp_buf_b + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_b + SCROLL_BUFFER_SIZE - remaining, remaining);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
752 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
753
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
754 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
755 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
756 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
757 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
758 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
759 external_slot(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
760 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
761 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
762 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
763 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
764 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
765 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
766 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
767 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
768 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
769 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
770 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
771 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
772 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
773 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
774 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
775 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
776 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
777 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
778 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
779
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
780 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
781 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
782 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
783 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
784 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
785 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
786 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
787 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
788 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
789 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
790 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
791 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
792 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
793 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
794 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
795 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
796 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
797 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
798 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
799 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
800 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
801 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
802 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
803 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
804
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
805 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
806 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
807 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
808 uint32_t mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
809 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
810 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
811 //sprite render to line buffer starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
812 case 0:
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
813 context->cur_slot = MAX_DRAWS-1;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
814 memset(context->linebuf, 0, LINEBUF_SIZE);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
815 case 1:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
816 case 2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
817 case 3:
329
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
818 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
819 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
820 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
821 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
822 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
823 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
824 //sprite attribute table scan starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
825 case 4:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
826 render_sprite_cells( context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
827 context->sprite_index = 0x80;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
828 context->slot_counter = MAX_SPRITES_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
829 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
830 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
831 case 5:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
832 case 6:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
833 case 7:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
834 case 8:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
835 case 9:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
836 case 10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
837 case 11:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
838 case 12:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
839 case 13:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
840 case 14:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
841 case 15:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
842 case 16:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
843 case 17:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
844 case 18:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
845 case 19:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
846 case 20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
847 //!HSYNC asserted
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
848 case 21:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
849 case 22:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
850 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
851 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
852 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
853 case 23:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
854 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
855 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
856 case 24:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
857 case 25:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
858 case 26:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
859 case 27:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
860 case 28:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
861 case 29:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
862 case 30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
863 case 31:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
864 case 32:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
865 case 33:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
866 case 34:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
867 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
868 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
869 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
870 case 35:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
871 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
872 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
873 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
874 mask |= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
875 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
876 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
877 mask |= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
878 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
879 line &= mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
880 address += line * 4;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
881 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
882 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
883 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
884 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
885 case 36:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
886 //!HSYNC high
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
887 case 37:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
888 case 38:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
889 case 39:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
890 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
891 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
892 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
893 case 40:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
894 read_map_scroll_a(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
895 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
896 case 41:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
897 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
898 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
899 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
900 case 42:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
901 render_map_1(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
902 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
903 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
904 case 43:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
905 render_map_2(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
906 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
907 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
908 case 44:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
909 read_map_scroll_b(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
910 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
911 case 45:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
912 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
913 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
914 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
915 case 46:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
916 render_map_3(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
917 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
918 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
919 case 47:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
920 render_map_output(line, 0, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
921 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
922 //reverse context slot counter so it counts the number of sprite slots
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
923 //filled rather than the number of available slots
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
924 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
925 context->cur_slot = MAX_SPRITES_LINE-1;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
926 context->sprite_draws = MAX_DRAWS;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
927 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
928 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
929 COLUMN_RENDER_BLOCK(2, 48)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
930 COLUMN_RENDER_BLOCK(4, 56)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
931 COLUMN_RENDER_BLOCK(6, 64)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
932 COLUMN_RENDER_BLOCK_REFRESH(8, 72)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
933 COLUMN_RENDER_BLOCK(10, 80)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
934 COLUMN_RENDER_BLOCK(12, 88)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
935 COLUMN_RENDER_BLOCK(14, 96)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
936 COLUMN_RENDER_BLOCK_REFRESH(16, 104)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
937 COLUMN_RENDER_BLOCK(18, 112)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
938 COLUMN_RENDER_BLOCK(20, 120)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
939 COLUMN_RENDER_BLOCK(22, 128)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
940 COLUMN_RENDER_BLOCK_REFRESH(24, 136)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
941 COLUMN_RENDER_BLOCK(26, 144)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
942 COLUMN_RENDER_BLOCK(28, 152)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
943 COLUMN_RENDER_BLOCK(30, 160)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
944 COLUMN_RENDER_BLOCK_REFRESH(32, 168)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
945 COLUMN_RENDER_BLOCK(34, 176)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
946 COLUMN_RENDER_BLOCK(36, 184)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
947 COLUMN_RENDER_BLOCK(38, 192)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
948 COLUMN_RENDER_BLOCK_REFRESH(40, 200)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
949 case 208:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
950 case 209:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
951 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
952 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
953 default:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
954 //leftovers from HSYNC clock change nonsense
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
955 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
956 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
957 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
958
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
959 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
960 {
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
961 uint16_t address;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
962 uint32_t mask;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
963 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
964 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
965 //sprite render to line buffer starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
966 case 0:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
967 context->cur_slot = MAX_DRAWS_H32-1;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
968 memset(context->linebuf, 0, LINEBUF_SIZE);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
969 case 1:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
970 case 2:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
971 case 3:
329
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
972 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
973 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
974 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
975 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
976 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
977 break;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
978 //sprite attribute table scan starts
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
979 case 4:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
980 render_sprite_cells( context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
981 context->sprite_index = 0x80;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
982 context->slot_counter = MAX_SPRITES_LINE_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
983 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
984 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
985 case 5:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
986 case 6:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
987 case 7:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
988 case 8:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
989 case 9:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
990 case 10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
991 case 11:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
992 case 12:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
993 case 13:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
994 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
995 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
996 case 14:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
997 external_slot(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
998 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
999 case 15:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1000 case 16:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1001 case 17:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1002 case 18:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1003 case 19:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1004 //HSYNC start
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1005 case 20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1006 case 21:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1007 case 22:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1008 case 23:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1009 case 24:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1010 case 25:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1011 case 26:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1012 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1013 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1014 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1015 case 27:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1016 external_slot(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1017 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 case 28:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1019 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1020 mask = 0;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1021 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1022 mask |= 0xF8;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1023 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1024 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1025 mask |= 0x7;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1026 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1027 line &= mask;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1028 address += line * 4;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1029 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1030 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1031 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1032 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1033 case 29:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1034 case 30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1035 case 31:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1036 case 32:
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1037 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1038 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1039 break;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1040 //!HSYNC high
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1041 case 33:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1042 read_map_scroll_a(0, line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1043 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1044 case 34:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1045 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1046 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1047 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1048 case 35:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1049 render_map_1(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1050 scan_sprite_table(line, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1051 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1052 case 36:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1053 render_map_2(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1054 scan_sprite_table(line, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1055 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1056 case 37:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1057 read_map_scroll_b(0, line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 case 38:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1060 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1061 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 case 39:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1064 render_map_3(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1065 scan_sprite_table(line, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1066 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1067 case 40:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1068 render_map_output(line, 0, context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1069 scan_sprite_table(line, context);//Just a guess
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1070 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1071 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1072 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1073 context->cur_slot = MAX_SPRITES_LINE_H32-1;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1074 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1075 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1076 break;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1077 COLUMN_RENDER_BLOCK(2, 41)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1078 COLUMN_RENDER_BLOCK(4, 49)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1079 COLUMN_RENDER_BLOCK(6, 57)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1080 COLUMN_RENDER_BLOCK_REFRESH(8, 65)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1081 COLUMN_RENDER_BLOCK(10, 73)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1082 COLUMN_RENDER_BLOCK(12, 81)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1083 COLUMN_RENDER_BLOCK(14, 89)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1084 COLUMN_RENDER_BLOCK_REFRESH(16, 97)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1085 COLUMN_RENDER_BLOCK(18, 105)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1086 COLUMN_RENDER_BLOCK(20, 113)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1087 COLUMN_RENDER_BLOCK(22, 121)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1088 COLUMN_RENDER_BLOCK_REFRESH(24, 129)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1089 COLUMN_RENDER_BLOCK(26, 137)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1090 COLUMN_RENDER_BLOCK(28, 145)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1091 COLUMN_RENDER_BLOCK(30, 153)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1092 COLUMN_RENDER_BLOCK_REFRESH(32, 161)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1093 case 169:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1094 case 170:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1095 external_slot(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1096 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1097 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1098 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1099 void latch_mode(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1100 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1101 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1102 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1103
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1104 int is_refresh(vdp_context * context, uint32_t slot)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1105 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1106 if (context->latched_mode & BIT_H40) {
189
806c3b7a6f2a Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
1107 //TODO: Figure out the exact behavior that reduces DMA slots for direct color DMA demos
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1108 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210 || (slot < 6 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE)));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1109 } else {
189
806c3b7a6f2a Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
1110 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
191
1b4d856b067a Fixes for direct color dma stuff
Mike Pavone <pavone@retrodev.com>
parents: 190
diff changeset
1111 //These numbers are guesses based on H40 numbers
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1112 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152 || (slot < 5 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE)));
189
806c3b7a6f2a Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
1113 //The numbers below are the refresh slots during active display
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1114 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1115 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1116 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1117
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1118 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1119 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1120 if (line > 0) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1121 line -= 1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1122 uint16_t * start = NULL, *end = NULL;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1123 if (context->latched_mode & BIT_H40) {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1124 if (slot >= 50 && slot < 210) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1125 uint32_t x = (slot-50)*2;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1126 start = context->framebuf + line * 320 + x;
190
4cb8a3891e26 Small fix to bg drawing that yields the proper res for direct color DMA
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
1127 end = start + 2;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1128 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1129 } else {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1130 if (slot >= 43 && slot < 171) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1131 uint32_t x = (slot-43)*2;
191
1b4d856b067a Fixes for direct color dma stuff
Mike Pavone <pavone@retrodev.com>
parents: 190
diff changeset
1132 start = context->framebuf + line * 320 + x;
190
4cb8a3891e26 Small fix to bg drawing that yields the proper res for direct color DMA
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
1133 end = start + 2;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1134 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1135 }
291
eea3b118940d Make sure all rendering operations mask CRAM with 0xEEE before using it
Mike Pavone <pavone@retrodev.com>
parents: 233
diff changeset
1136 uint16_t color = (context->cram[context->regs[REG_BG_COLOR] & 0x3F] & 0xEEE);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1137 while (start != end) {
189
806c3b7a6f2a Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
1138 *start = color;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1139 ++start;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1140 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1141 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1142 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1143
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1144 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1145 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1146 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1147 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1148 uint32_t line = context->cycles / MCLKS_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
334
4c91470e1a53 Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents: 333
diff changeset
1150 if (!context->cycles) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1151 latch_mode(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1152 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1153 uint32_t linecyc = context->cycles % MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1154 if (linecyc == 0) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1155 if (line <= 1 || line >= active_lines) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1156 context->hint_counter = context->regs[REG_HINT];
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1157 } else if (context->hint_counter) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1158 context->hint_counter--;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1159 } else {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1160 context->flags2 |= FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1161 context->hint_counter = context->regs[REG_HINT];
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1162 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1163 } else if(line == active_lines) {
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1164 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1165 if (linecyc == intcyc) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1166 context->flags2 |= FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1167 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1168 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1169 uint32_t inccycles, slot;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1170 if (context->latched_mode & BIT_H40){
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1171 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1172 slot = linecyc/MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1173 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1174 } else if(linecyc < MCLK_WEIRD_END) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1175 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1176 {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1177 case 0:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1178 inccycles = 19;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1179 slot = 0;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1180 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1181 case 19:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1182 slot = 1;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1183 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1184 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1185 case 39:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1186 slot = 2;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1187 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1188 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1189 case 59:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1190 slot = 3;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1191 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1192 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1193 case 79:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1194 slot = 4;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1195 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1196 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1197 case 97:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1198 slot = 5;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1199 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1200 break;
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1201 case 117:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1202 slot = 6;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1203 inccycles = 20;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1204 break;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1205 case 137:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1206 slot = 7;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1207 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1208 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1209 case 157:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1210 slot = 8;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1211 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1212 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1213 case 175:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1214 slot = 9;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1215 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1216 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1217 case 195:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1218 slot = 10;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1219 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1220 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1221 case 215:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1222 slot = 11;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1223 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1224 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1225 case 235:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1226 slot = 12;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1227 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1228 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1229 case 253:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1230 slot = 13;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1231 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1232 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1233 case 273:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1234 slot = 14;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1235 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1236 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1237 case 293:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1238 slot = 15;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1239 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1240 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1241 case 313:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1242 slot = 16;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1243 inccycles = 19;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1244 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1245 default:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1246 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1247 exit(1);
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1248 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1249 slot += HSYNC_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1250 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1251 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1252 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1253 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1254 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1255 inccycles = MCLKS_SLOT_H32;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1256 slot = linecyc/MCLKS_SLOT_H32;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1257 }
329
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1258 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) {
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1259 //first sort-of active line is treated as 255 internally
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1260 //it's used for gathering sprite info for line
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1261 line = (line - 1) & 0xFF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1262
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1263 //Convert to slot number
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1264 if (context->latched_mode & BIT_H40){
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1265 vdp_h40(line, slot, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1266 } else {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1267 vdp_h32(line, slot, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1268 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1269 } else {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1270 if (!is_refresh(context, slot)) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1271 external_slot(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1272 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1273 if (line < active_lines) {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1274 check_render_bg(context, line, slot);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1275 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1276 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1277 context->cycles += inccycles;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1278 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1279 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1280
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1281 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1282 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1283 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1284 vdp_run_context(context, target_cycles);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1285 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1286 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1287
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1288 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1289 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1290 for(;;) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1291 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1292 if (!dmalen) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1293 dmalen = 0x10000;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1294 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1295 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1296 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1297 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1298 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1299 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1300 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1301 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1302 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1303 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1304 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1305 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1306 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1307 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1308 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1309 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1310 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1311 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1312 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1313
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1314 int vdp_control_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1315 {
58
a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents: 56
diff changeset
1316 //printf("control port write: %X\n", value);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1317 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1318 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1319 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1320 if (context->flags & FLAG_PENDING) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1321 context->address = (context->address & 0x3FFF) | (value << 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1322 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1323 context->flags &= ~FLAG_PENDING;
87
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
1324 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1325 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1326 //
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1327 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1328 //DMA copy or 68K -> VDP, transfer starts immediately
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1329 context->flags |= FLAG_DMA_RUN;
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
1330 context->dma_cd = context->cd;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1331 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1332 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1333 return 1;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1334 } else {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1335 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1336 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1337 } else {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1338 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1339 }
63
a6dd5b7a971b Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents: 58
diff changeset
1340 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1341 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1342 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1343 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1344 uint8_t reg = (value >> 8) & 0x1F;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1345 if (reg < VDP_REGS) {
87
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
1346 //printf("register %d set to %X\n", reg, value & 0xFF);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1347 context->regs[reg] = value;
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
1348 if (reg == REG_MODE_2) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
1349 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled");
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
1350 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1351 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1352 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
1353 if (!context->double_res) {
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
1354 context->framebuf = context->oddbuf;
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
1355 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1356 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1357 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1358 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1359 context->flags |= FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1360 context->address = (context->address &0xC000) | (value & 0x3FFF);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1361 context->cd = (context->cd &0x3C) | (value >> 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1362 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1363 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1364 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1365 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1366
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1367 int vdp_data_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1368 {
58
a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents: 56
diff changeset
1369 //printf("data port write: %X\n", value);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1370 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1371 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1372 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1373 if (!(context->cd & 1)) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1374 //ignore writes when cd is configured for read
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1375 return 0;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1376 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1377 context->flags &= ~FLAG_PENDING;
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
1378 /*if (context->fifo_cur == context->fifo_end) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1379 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
1380 }*/
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1381 while (context->fifo_cur == context->fifo_end) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1382 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1383 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1384 context->fifo_cur->cycle = context->cycles;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1385 context->fifo_cur->address = context->address;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1386 context->fifo_cur->value = value;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1387 context->fifo_cur->cd = context->cd;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1388 context->fifo_cur->partial = 0;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1389 context->fifo_cur++;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1390 context->address += context->regs[REG_AUTOINC];
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1391 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1392 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1393
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1394 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1395 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1396 context->flags &= ~FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1397 uint16_t value = 0x3400;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1398 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1399 value |= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1400 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1401 if (context->fifo_cur == context->fifo_end) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1402 value |= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1403 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1404 if (context->flags2 & FLAG2_VINT_PENDING) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1405 value |= 0x80;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1406 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1407 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1408 value |= 0x10;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1409 }
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1410 uint32_t line= context->cycles / MCLKS_LINE;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1411 uint32_t linecyc = context->cycles % MCLKS_LINE;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1412 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) {
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1413 value |= 0x8;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1414 }
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1415 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) {
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1416 value |= 0x4;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1417 }
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1418 if (context->flags & FLAG_DMA_RUN) {
141
576f55711d8d Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
1419 value |= 0x2;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1420 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1421 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1422 value |= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1423 }
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1424 //TODO: Sprite overflow, sprite collision, odd frame flag
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1425 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1426 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1427
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1428 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1429 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1430 context->flags &= ~FLAG_PENDING;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1431 if (context->cd & 1) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1432 return 0;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1433 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1434 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1435 context->flags &= ~FLAG_UNUSED_SLOT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1436 while (!(context->flags & FLAG_UNUSED_SLOT)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1437 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1438 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1439 uint16_t value = 0;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1440 switch (context->cd & 0xF)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1441 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1442 case VRAM_READ:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1443 value = context->vdpmem[context->address] << 8;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1444 context->flags &= ~FLAG_UNUSED_SLOT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1445 while (!(context->flags & FLAG_UNUSED_SLOT)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1446 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1447 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1448 value |= context->vdpmem[context->address ^ 1];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1449 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1450 case CRAM_READ:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1451 value = context->cram[(context->address/2) & (CRAM_SIZE-1)];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1452 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1453 case VSRAM_READ:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1454 if (((context->address / 2) & 63) < VSRAM_SIZE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1455 value = context->vsram[context->address & 63];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1456 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1457 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1458 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1459 context->address += context->regs[REG_AUTOINC];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1460 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1461 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1462
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1463 uint16_t vdp_hv_counter_read(vdp_context * context)
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1464 {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1465 //TODO: deal with clock adjustemnts handled in vdp_run_context
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1466 uint32_t line= context->cycles / MCLKS_LINE;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1467 if (!line) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1468 line = 0xFF;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1469 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1470 line--;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1471 if (line > 0xEA) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1472 line = (line + 0xFA) & 0xFF;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1473 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1474 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1475 uint32_t linecyc = context->cycles % MCLKS_LINE;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1476 if (context->latched_mode & BIT_H40) {
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1477 uint32_t slot;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1478 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1479 slot = linecyc/MCLKS_SLOT_H40;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1480 } else if(linecyc < MCLK_WEIRD_END) {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1481 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1482 {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1483 case 0:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1484 slot = 0;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1485 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1486 case 19:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1487 slot = 1;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1488 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1489 case 39:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1490 slot = 2;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1491 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1492 case 59:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1493 slot = 2;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1494 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1495 case 79:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1496 slot = 3;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1497 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1498 case 97:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1499 slot = 4;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1500 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1501 case 117:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1502 slot = 5;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1503 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1504 case 137:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1505 slot = 6;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1506 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1507 case 157:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1508 slot = 7;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1509 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1510 case 175:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1511 slot = 8;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1512 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1513 case 195:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1514 slot = 9;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1515 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1516 case 215:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1517 slot = 11;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1518 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1519 case 235:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1520 slot = 12;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1521 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1522 case 253:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1523 slot = 13;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1524 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1525 case 273:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1526 slot = 14;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1527 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1528 case 293:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1529 slot = 15;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1530 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1531 case 313:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1532 slot = 16;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1533 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1534 default:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1535 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1536 exit(1);
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1537 }
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1538 slot += HSYNC_SLOT_H40;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1539 } else {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1540 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1541 }
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1542 linecyc = slot * 2;
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1543 if (linecyc >= 86) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1544 linecyc -= 86;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1545 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1546 linecyc += 334;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1547 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1548 if (linecyc > 0x16C) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1549 linecyc += 92;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1550 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1551 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1552 linecyc /= 10;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1553 if (linecyc >= 74) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1554 linecyc -= 74;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1555 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1556 linecyc += 268;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1557 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1558 if (linecyc > 0x127) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1559 linecyc += 170;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1560 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1561 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1562 linecyc &= 0xFF;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1563 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1564 line <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1565 if (line & 0x100) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1566 line |= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1567 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1568 }
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1569 return (line << 8) | linecyc;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1570 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1571
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1572 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1573 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1574 context->cycles -= deduction;
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1575 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1576 if (start->cycle >= deduction) {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1577 start->cycle -= deduction;
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1578 } else {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1579 start->cycle = 0;
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1580 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1581 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1582 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1583
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1584 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1585 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1586 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1587 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1588 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1589 if (context->flags2 & FLAG2_HINT_PENDING) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1590 return context->cycles;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1591 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1592 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1593 uint32_t line = context->cycles / MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1594 if (line >= active_lines) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1595 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1596 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1597 uint32_t linecyc = context->cycles % MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1598 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1599 if (!line) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1600 hcycle += MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1601 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1602 return hcycle;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1603 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1604
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1605 uint32_t vdp_next_vint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1606 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1607 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1608 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1609 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1610 if (context->flags2 & FLAG2_VINT_PENDING) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1611 return context->cycles;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1612 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1613 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1614 uint32_t vcycle = MCLKS_LINE * active_lines;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1615 if (context->latched_mode & BIT_H40) {
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1616 vcycle += VINT_CYCLE_H40;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1617 } else {
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1618 vcycle += VINT_CYCLE_H32;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1619 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1620 if (vcycle < context->cycles) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1621 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1622 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1623 return vcycle;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1624 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1625
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1626 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1627 {
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1628 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1629 uint32_t vcycle = MCLKS_LINE * active_lines;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1630 if (context->latched_mode & BIT_H40) {
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1631 vcycle += VINT_CYCLE_H40;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1632 } else {
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1633 vcycle += VINT_CYCLE_H32;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1634 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1635 return vcycle;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1636 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1637
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1638 void vdp_int_ack(vdp_context * context, uint16_t int_num)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1639 {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1640 if (int_num == 6) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1641 context->flags2 &= ~FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1642 } else if(int_num ==4) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1643 context->flags2 &= ~FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1644 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1645 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1646
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1647 #define GST_VDP_REGS 0xFA
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1648 #define GST_VDP_MEM 0x12478
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1649
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1650 void vdp_load_savestate(vdp_context * context, FILE * state_file)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1651 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1652 uint8_t tmp_buf[CRAM_SIZE*2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1653 fseek(state_file, GST_VDP_REGS, SEEK_SET);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1654 fread(context->regs, 1, VDP_REGS, state_file);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1655 latch_mode(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1656 fread(tmp_buf, 1, sizeof(tmp_buf), state_file);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1657 for (int i = 0; i < CRAM_SIZE; i++) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1658 context->cram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1659 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1660 fread(tmp_buf, 2, VSRAM_SIZE, state_file);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1661 for (int i = 0; i < VSRAM_SIZE; i++) {
23
3e924bb56560 Fix endianness of VSRAM when read from Genecyst save state
Mike Pavone <pavone@retrodev.com>
parents: 22
diff changeset
1662 context->vsram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2];
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1663 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1664 fseek(state_file, GST_VDP_MEM, SEEK_SET);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1665 fread(context->vdpmem, 1, VRAM_SIZE, state_file);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1666 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1667
56
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1668 void vdp_save_state(vdp_context * context, FILE * outfile)
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1669 {
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1670 uint8_t tmp_buf[CRAM_SIZE*2];
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1671 fseek(outfile, GST_VDP_REGS, SEEK_SET);
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1672 fwrite(context->regs, 1, VDP_REGS, outfile);
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1673 for (int i = 0; i < CRAM_SIZE; i++) {
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1674 tmp_buf[i*2] = context->cram[i];
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1675 tmp_buf[i*2+1] = context->cram[i] >> 8;
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1676 }
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1677 fwrite(tmp_buf, 1, sizeof(tmp_buf), outfile);
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1678 for (int i = 0; i < VSRAM_SIZE; i++) {
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1679 tmp_buf[i*2] = context->vsram[i];
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1680 tmp_buf[i*2+1] = context->vsram[i] >> 8;
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1681 }
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1682 fwrite(tmp_buf, 2, VSRAM_SIZE, outfile);
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1683 fseek(outfile, GST_VDP_MEM, SEEK_SET);
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1684 fwrite(context->vdpmem, 1, VRAM_SIZE, outfile);
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1685 }
a28b1dfe1af2 Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1686