Mercurial > repos > blastem
annotate vdp.c @ 430:7f84090ab1cd
Add config file parser and default config file
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Wed, 10 Jul 2013 09:38:05 -0700 |
| parents | 2802318c14e1 |
| children | e341fd5aa996 |
| rev | line source |
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1 #include "vdp.h" |
| 75 | 2 #include "blastem.h" |
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3 #include <stdlib.h> |
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4 #include <string.h> |
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5 #include "render.h" |
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6 |
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7 #define NTSC_ACTIVE 225 |
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8 #define PAL_ACTIVE 241 |
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9 #define BUF_BIT_PRIORITY 0x40 |
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10 #define MAP_BIT_PRIORITY 0x8000 |
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11 #define MAP_BIT_H_FLIP 0x800 |
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12 #define MAP_BIT_V_FLIP 0x1000 |
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13 |
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14 #define SCROLL_BUFFER_SIZE 32 |
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15 #define SCROLL_BUFFER_DRAW 16 |
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16 |
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17 #define FIFO_SIZE 4 |
| 40 | 18 |
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19 #define MCLKS_SLOT_H40 16 |
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20 #define MCLKS_SLOT_H32 20 |
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21 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
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22 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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23 #define HSYNC_SLOT_H40 21 |
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24 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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25 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
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26 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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27 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
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28 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
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29 |
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30 int32_t color_map[1 << 12]; |
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31 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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32 |
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33 uint8_t color_map_init_done; |
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34 |
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35 void init_vdp_context(vdp_context * context) |
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36 { |
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37 memset(context, 0, sizeof(*context)); |
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38 context->vdpmem = malloc(VRAM_SIZE); |
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39 memset(context->vdpmem, 0, VRAM_SIZE); |
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40 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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41 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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42 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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43 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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44 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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45 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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46 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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47 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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48 context->sprite_draws = MAX_DRAWS; |
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49 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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50 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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51 context->b32 = render_depth() == 32; |
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52 if (!color_map_init_done) { |
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53 uint8_t b,g,r; |
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54 for (uint16_t color = 0; color < (1 << 12); color++) { |
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55 if (color & FBUF_SHADOW) { |
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56 b = levels[(color >> 9) & 0x7]; |
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57 g = levels[(color >> 5) & 0x7]; |
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58 r = levels[(color >> 1) & 0x7]; |
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59 } else if(color & FBUF_HILIGHT) { |
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60 b = levels[((color >> 9) & 0x7) + 7]; |
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61 g = levels[((color >> 5) & 0x7) + 7]; |
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62 r = levels[((color >> 1) & 0x7) + 7]; |
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63 } else { |
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64 b = levels[(color >> 8) & 0xE]; |
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65 g = levels[(color >> 4) & 0xE]; |
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66 r = levels[color & 0xE]; |
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67 } |
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68 color_map[color] = render_map_color(r, g, b); |
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69 } |
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70 color_map_init_done = 1; |
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71 } |
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72 } |
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73 |
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74 void render_sprite_cells(vdp_context * context) |
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75 { |
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76 if (context->cur_slot >= context->sprite_draws) { |
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77 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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78 |
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79 uint16_t dir; |
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80 int16_t x; |
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81 if (d->h_flip) { |
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82 x = d->x_pos + 7; |
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83 dir = -1; |
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84 } else { |
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85 x = d->x_pos; |
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86 dir = 1; |
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87 } |
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88 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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89 context->cur_slot--; |
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90 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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91 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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92 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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93 } |
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94 x += dir; |
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95 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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96 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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97 } |
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98 x += dir; |
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99 } |
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100 } |
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101 } |
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102 |
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103 void vdp_print_sprite_table(vdp_context * context) |
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104 { |
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105 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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106 uint16_t current_index = 0; |
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107 uint8_t count = 0; |
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108 do { |
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109 uint16_t address = current_index * 8 + sat_address; |
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110 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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111 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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112 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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113 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
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114 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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115 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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116 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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117 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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118 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
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119 current_index = link; |
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120 count++; |
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121 } while (current_index != 0 && count < 80); |
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122 } |
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123 |
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124 void vdp_print_reg_explain(vdp_context * context) |
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125 { |
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126 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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127 printf("**Mode Group**\n" |
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128 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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129 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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130 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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131 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
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132 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
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133 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
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134 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
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135 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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136 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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137 hscroll[context->regs[REG_MODE_3] & 0x3], |
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138 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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139 printf("\n**Table Group**\n" |
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140 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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141 "03: %.2X | Window Name Table: $%.4X\n" |
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142 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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143 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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144 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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145 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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146 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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147 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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148 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
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149 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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150 char * sizes[] = {"32", "64", "invalid", "128"}; |
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151 printf("\n**Misc Group**\n" |
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152 "07: %.2X | Backdrop Color: $%X\n" |
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153 "0A: %.2X | H-Int Counter: %u\n" |
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154 "0F: %.2X | Auto-increment: $%X\n" |
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155 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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156 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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157 context->regs[REG_HINT], context->regs[REG_HINT], |
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158 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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159 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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160 |
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161 //TODO: Window Group, DMA Group |
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162 } |
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163 |
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164 void scan_sprite_table(uint32_t line, vdp_context * context) |
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165 { |
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166 if (context->sprite_index && context->slot_counter) { |
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167 line += 1; |
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168 line &= 0xFF; |
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169 uint16_t ymask, ymin; |
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170 uint8_t height_mult; |
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171 if (context->double_res) { |
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172 line *= 2; |
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173 if (context->framebuf != context->oddbuf) { |
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174 line++; |
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175 } |
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176 ymask = 0x3FF; |
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177 ymin = 256; |
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178 height_mult = 16; |
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179 } else { |
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180 ymask = 0x1FF; |
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181 ymin = 128; |
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182 height_mult = 8; |
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183 } |
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184 context->sprite_index &= 0x7F; |
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185 if (context->latched_mode & BIT_H40) { |
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186 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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187 context->sprite_index = 0; |
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188 return; |
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189 } |
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190 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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191 context->sprite_index = 0; |
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192 return; |
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193 } |
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194 //TODO: Read from SAT cache rather than from VRAM |
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195 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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196 uint16_t address = context->sprite_index * 8 + sat_address; |
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413
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197 line += ymin; |
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198 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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199 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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200 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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201 if (y <= line && line < (y + height)) { |
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202 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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203 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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204 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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205 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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206 } |
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207 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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208 if (context->sprite_index && context->slot_counter) |
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209 { |
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210 address = context->sprite_index * 8 + sat_address; |
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211 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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212 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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213 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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214 if (y <= line && line < (y + height)) { |
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215 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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216 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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217 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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218 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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219 } |
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220 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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221 } |
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222 } |
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223 } |
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224 |
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225 void read_sprite_x(uint32_t line, vdp_context * context) |
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226 { |
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227 if (context->cur_slot >= context->slot_counter) { |
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228 if (context->sprite_draws) { |
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229 line += 1; |
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230 line &= 0xFF; |
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231 //in tiles |
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232 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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233 //in pixels |
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234 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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235 if (context->double_res) { |
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236 line *= 2; |
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237 if (context->framebuf != context->oddbuf) { |
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238 line++; |
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239 } |
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240 height *= 2; |
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241 } |
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242 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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243 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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244 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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245 uint8_t row; |
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246 if (tileinfo & MAP_BIT_V_FLIP) { |
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247 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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248 } else { |
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249 row = line-context->sprite_info_list[context->cur_slot].y; |
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250 } |
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251 uint16_t address; |
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252 if (context->double_res) { |
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253 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
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254 } else { |
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255 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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256 } |
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257 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
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258 if (x) { |
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259 context->flags |= FLAG_CAN_MASK; |
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260 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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261 context->flags |= FLAG_MASKED; |
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262 } |
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263 |
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264 context->flags &= ~FLAG_DOT_OFLOW; |
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265 int16_t i; |
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266 if (context->flags & FLAG_MASKED) { |
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267 for (i=0; i < width && context->sprite_draws; i++) { |
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268 --context->sprite_draws; |
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269 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
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270 } |
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271 } else { |
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272 x -= 128; |
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273 int16_t base_x = x; |
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274 int16_t dir; |
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275 if (tileinfo & MAP_BIT_H_FLIP) { |
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276 x += (width-1) * 8; |
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277 dir = -8; |
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278 } else { |
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279 dir = 8; |
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280 } |
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281 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
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282 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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283 --context->sprite_draws; |
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284 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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285 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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286 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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287 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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288 } |
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289 } |
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290 if (i < width) { |
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291 context->flags |= FLAG_DOT_OFLOW; |
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292 } |
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293 context->cur_slot--; |
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294 } else { |
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295 context->flags |= FLAG_DOT_OFLOW; |
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296 } |
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297 } |
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298 } |
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299 |
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300 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
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301 { |
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302 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
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303 context->cram[addr] = value; |
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304 context->colors[addr] = color_map[value & 0xEEE]; |
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305 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
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306 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
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307 } |
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308 |
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309 #define VRAM_READ 0 |
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310 #define VRAM_WRITE 1 |
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311 #define CRAM_READ 8 |
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312 #define CRAM_WRITE 3 |
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313 #define VSRAM_READ 4 |
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314 #define VSRAM_WRITE 5 |
| 75 | 315 #define DMA_START 0x20 |
|
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316 |
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317 void external_slot(vdp_context * context) |
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318 { |
| 75 | 319 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
| 320 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
| 321 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
|
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322 if(context->flags & FLAG_DMA_RUN) { |
| 75 | 323 uint16_t dma_len; |
| 324 switch(context->regs[REG_DMASRC_H] & 0xC0) | |
|
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325 { |
| 75 | 326 //68K -> VDP |
| 327 case 0: | |
| 328 case 0x40: | |
|
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329 switch(context->dma_cd & 0xF) |
| 75 | 330 { |
| 331 case VRAM_WRITE: | |
| 332 if (context->flags & FLAG_DMA_PROG) { | |
| 333 context->vdpmem[context->address ^ 1] = context->dma_val; | |
| 334 context->flags &= ~FLAG_DMA_PROG; | |
| 335 } else { | |
| 336 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 337 context->vdpmem[context->address] = context->dma_val >> 8; | |
| 338 context->flags |= FLAG_DMA_PROG; | |
| 339 } | |
| 340 break; | |
|
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341 case CRAM_WRITE: { |
|
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342 write_cram(context, context->address, read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L])); |
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343 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles); |
| 75 | 344 break; |
|
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345 } |
| 75 | 346 case VSRAM_WRITE: |
| 347 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 348 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 349 } | |
| 350 break; | |
|
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351 } |
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352 break; |
| 75 | 353 //Fill |
| 354 case 0x80: | |
|
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355 switch(context->dma_cd & 0xF) |
| 75 | 356 { |
| 357 case VRAM_WRITE: | |
| 358 //Charles MacDonald's VDP doc says that the low byte gets written first | |
| 142 | 359 context->vdpmem[context->address] = context->dma_val; |
| 360 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF); | |
| 75 | 361 break; |
|
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362 case CRAM_WRITE: |
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363 write_cram(context, context->address, context->dma_val); |
|
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364 //printf("CRAM DMA Fill | %X set to %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->cycles); |
| 75 | 365 break; |
| 366 case VSRAM_WRITE: | |
| 367 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 368 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 369 } | |
| 370 break; | |
| 371 } | |
|
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372 break; |
| 75 | 373 //Copy |
| 374 case 0xC0: | |
| 375 if (context->flags & FLAG_DMA_PROG) { | |
|
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376 switch(context->dma_cd & 0xF) |
| 75 | 377 { |
| 378 case VRAM_WRITE: | |
| 379 context->vdpmem[context->address] = context->dma_val; | |
| 380 break; | |
|
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381 case CRAM_WRITE: { |
|
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382 write_cram(context, context->address, context->dma_val); |
|
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383 //printf("CRAM DMA Copy | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->regs[REG_DMASRC_L] & (CRAM_SIZE-1), context->cycles); |
| 75 | 384 break; |
|
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385 } |
| 75 | 386 case VSRAM_WRITE: |
| 387 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 388 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 389 } | |
| 390 break; | |
| 391 } | |
| 392 context->flags &= ~FLAG_DMA_PROG; | |
| 393 } else { | |
| 394 //I assume, that DMA copy copies from the same RAM as the destination | |
| 395 //but it's possible I'm mistaken | |
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396 switch(context->dma_cd & 0xF) |
| 75 | 397 { |
| 398 case VRAM_WRITE: | |
| 399 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
| 400 break; | |
| 401 case CRAM_WRITE: | |
| 402 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
| 403 break; | |
| 404 case VSRAM_WRITE: | |
| 405 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
| 406 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
| 407 } else { | |
| 408 context->dma_val = 0; | |
| 409 } | |
| 410 break; | |
| 411 } | |
| 412 context->flags |= FLAG_DMA_PROG; | |
|
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413 } |
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414 break; |
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415 } |
| 75 | 416 if (!(context->flags & FLAG_DMA_PROG)) { |
| 417 context->address += context->regs[REG_AUTOINC]; | |
| 418 context->regs[REG_DMASRC_L] += 1; | |
| 135 | 419 if (!context->regs[REG_DMASRC_L]) { |
| 420 context->regs[REG_DMASRC_M] += 1; | |
| 421 } | |
| 75 | 422 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
| 423 context->regs[REG_DMALEN_H] = dma_len >> 8; | |
| 424 context->regs[REG_DMALEN_L] = dma_len; | |
| 425 if (!dma_len) { | |
| 426 context->flags &= ~FLAG_DMA_RUN; | |
| 427 } | |
|
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428 } |
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429 } else { |
| 75 | 430 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
| 431 if (context->fifo_cur != start && start->cycle <= context->cycles) { | |
| 432 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { | |
| 433 context->flags |= FLAG_DMA_RUN; | |
| 434 context->dma_val = start->value; | |
| 138 | 435 context->address = start->address; //undo auto-increment |
|
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436 context->dma_cd = context->cd; |
| 75 | 437 } else { |
| 138 | 438 switch (start->cd & 0xF) |
| 75 | 439 { |
| 440 case VRAM_WRITE: | |
| 441 if (start->partial) { | |
| 442 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); | |
| 138 | 443 context->vdpmem[start->address ^ 1] = start->value; |
| 75 | 444 } else { |
| 445 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); | |
| 138 | 446 context->vdpmem[start->address] = start->value >> 8; |
| 75 | 447 start->partial = 1; |
| 448 //skip auto-increment and removal of entry from fifo | |
| 449 return; | |
| 450 } | |
| 451 break; | |
|
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452 case CRAM_WRITE: { |
|
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453 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
|
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454 write_cram(context, start->address, start->value); |
| 75 | 455 break; |
|
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456 } |
| 75 | 457 case VSRAM_WRITE: |
| 138 | 458 if (((start->address/2) & 63) < VSRAM_SIZE) { |
| 75 | 459 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
| 138 | 460 context->vsram[(start->address/2) & 63] = start->value; |
| 75 | 461 } |
| 462 break; | |
| 463 } | |
| 138 | 464 //context->address += context->regs[REG_AUTOINC]; |
| 75 | 465 } |
| 466 fifo_entry * cur = start+1; | |
| 467 if (cur < context->fifo_cur) { | |
| 468 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); | |
| 469 } | |
| 470 context->fifo_cur -= 1; | |
| 471 } else { | |
| 472 context->flags |= FLAG_UNUSED_SLOT; | |
| 473 } | |
|
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474 } |
|
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475 } |
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476 |
| 40 | 477 #define WINDOW_RIGHT 0x80 |
| 478 #define WINDOW_DOWN 0x80 | |
| 479 | |
|
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480 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
|
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481 { |
|
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482 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
|
414
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483 if (context->double_res) { |
|
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484 line *= 2; |
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485 if (context->framebuf != context->oddbuf) { |
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486 line++; |
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487 } |
|
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488 window_line_shift = 4; |
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489 v_offset_mask = 0xF; |
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490 vscroll_shift = 4; |
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491 } else { |
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492 window_line_shift = 3; |
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493 v_offset_mask = 0x7; |
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494 vscroll_shift = 3; |
|
414
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495 } |
| 40 | 496 if (!vsram_off) { |
| 497 uint16_t left_col, right_col; | |
| 498 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
|
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499 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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500 right_col = 42; |
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501 } else { |
| 40 | 502 left_col = 0; |
| 503 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
| 504 if (right_col) { | |
| 505 right_col += 2; | |
| 506 } | |
| 507 } | |
|
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508 uint16_t top_line, bottom_line; |
|
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509 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
|
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510 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
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511 bottom_line = context->double_res ? 481 : 241; |
|
41
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512 } else { |
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513 top_line = 0; |
|
417
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514 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
|
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515 } |
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516 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
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diff
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|
517 uint16_t address = context->regs[REG_WINDOW] << 10; |
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diff
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518 uint16_t line_offset, offset, mask; |
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519 if (context->latched_mode & BIT_H40) { |
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diff
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|
520 address &= 0xF000; |
|
417
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|
521 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
|
41
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diff
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|
522 mask = 0x7F; |
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|
523 |
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diff
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|
524 } else { |
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|
525 address &= 0xF800; |
|
417
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526 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
|
41
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527 mask = 0x3F; |
|
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|
528 } |
|
417
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|
529 if (context->double_res) { |
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|
530 mask <<= 1; |
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|
531 mask |= 1; |
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|
532 } |
|
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
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41
diff
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|
533 offset = address + line_offset + (((column - 2) * 2) & mask); |
|
41
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diff
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|
534 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
535 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
|
42
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Fix bug in tile address masking. Remove some debug code from window plane.
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diff
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|
536 offset = address + line_offset + (((column - 1) * 2) & mask); |
|
41
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|
537 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
417
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parents:
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diff
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|
538 context->v_offset = (line) & v_offset_mask; |
|
41
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diff
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|
539 context->flags |= FLAG_WINDOW; |
|
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540 return; |
| 40 | 541 } |
| 542 context->flags &= ~FLAG_WINDOW; | |
| 543 } | |
|
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544 uint16_t vscroll; |
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545 switch(context->regs[REG_SCROLL] & 0x30) |
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|
546 { |
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|
547 case 0: |
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548 vscroll = 0xFF; |
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549 break; |
|
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|
550 case 0x10: |
|
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|
551 vscroll = 0x1FF; |
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diff
changeset
|
552 break; |
|
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|
553 case 0x20: |
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554 //TODO: Verify this behavior |
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555 vscroll = 0; |
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|
556 break; |
|
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|
557 case 0x30: |
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558 vscroll = 0x3FF; |
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|
559 break; |
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|
560 } |
|
414
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|
561 if (context->double_res) { |
|
413
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562 vscroll <<= 1; |
|
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|
563 vscroll |= 1; |
|
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413
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|
564 } |
|
327
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
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323
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|
565 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? column : 0) + vsram_off] + line); |
|
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413
diff
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|
566 context->v_offset = vscroll & v_offset_mask; |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
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567 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
|
414
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|
568 vscroll >>= vscroll_shift; |
|
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diff
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569 uint16_t hscroll_mask; |
|
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diff
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|
570 uint16_t v_mul; |
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parents:
diff
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|
571 switch(context->regs[REG_SCROLL] & 0x3) |
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|
572 { |
|
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changeset
|
573 case 0: |
|
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
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87
diff
changeset
|
574 hscroll_mask = 0x1F; |
|
20
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575 v_mul = 64; |
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|
576 break; |
|
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diff
changeset
|
577 case 0x1: |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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38
diff
changeset
|
578 hscroll_mask = 0x3F; |
|
20
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changeset
|
579 v_mul = 128; |
|
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diff
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|
580 break; |
|
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diff
changeset
|
581 case 0x2: |
|
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diff
changeset
|
582 //TODO: Verify this behavior |
|
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diff
changeset
|
583 hscroll_mask = 0; |
|
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diff
changeset
|
584 v_mul = 0; |
|
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diff
changeset
|
585 break; |
|
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parents:
diff
changeset
|
586 case 0x3: |
|
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
587 hscroll_mask = 0x7F; |
|
20
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diff
changeset
|
588 v_mul = 256; |
|
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parents:
diff
changeset
|
589 break; |
|
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parents:
diff
changeset
|
590 } |
| 28 | 591 uint16_t hscroll, offset; |
| 592 for (int i = 0; i < 2; i++) { | |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
593 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
594 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
595 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
| 28 | 596 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
| 597 if (i) { | |
| 598 context->col_2 = col_val; | |
| 599 } else { | |
| 600 context->col_1 = col_val; | |
| 601 } | |
| 602 } | |
|
20
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diff
changeset
|
603 } |
|
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diff
changeset
|
604 |
|
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parents:
diff
changeset
|
605 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
|
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parents:
diff
changeset
|
606 { |
|
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
607 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
|
20
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parents:
diff
changeset
|
608 } |
|
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parents:
diff
changeset
|
609 |
|
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parents:
diff
changeset
|
610 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
|
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parents:
diff
changeset
|
611 { |
|
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
612 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
|
20
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parents:
diff
changeset
|
613 } |
|
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parents:
diff
changeset
|
614 |
|
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parents:
diff
changeset
|
615 void render_map(uint16_t col, uint8_t * tmp_buf, vdp_context * context) |
|
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diff
changeset
|
616 { |
|
413
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Initial work on interlace
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337
diff
changeset
|
617 uint16_t address; |
|
36fbbced25c2
Initial work on interlace
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337
diff
changeset
|
618 uint8_t shift, add; |
|
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diff
changeset
|
619 if (context->double_res) { |
|
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diff
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|
620 address = ((col & 0x3FF) << 6); |
|
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337
diff
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|
621 shift = 1; |
|
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diff
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|
622 add = context->framebuf != context->oddbuf ? 1 : 0; |
|
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337
diff
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|
623 } else { |
|
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337
diff
changeset
|
624 address = ((col & 0x7FF) << 5); |
|
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337
diff
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|
625 shift = 0; |
|
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337
diff
changeset
|
626 add = 0; |
|
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337
diff
changeset
|
627 } |
|
20
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parents:
diff
changeset
|
628 if (col & MAP_BIT_V_FLIP) { |
|
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
629 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
|
20
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parents:
diff
changeset
|
630 } else { |
|
414
51ee0f117365
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Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
631 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
|
20
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parents:
diff
changeset
|
632 } |
|
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parents:
diff
changeset
|
633 uint16_t pal_priority = (col >> 9) & 0x70; |
|
f664eeb55cb4
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parents:
diff
changeset
|
634 int32_t dir; |
|
f664eeb55cb4
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parents:
diff
changeset
|
635 if (col & MAP_BIT_H_FLIP) { |
|
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parents:
diff
changeset
|
636 tmp_buf += 7; |
|
f664eeb55cb4
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parents:
diff
changeset
|
637 dir = -1; |
|
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parents:
diff
changeset
|
638 } else { |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
639 dir = 1; |
|
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640 } |
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641 for (uint32_t i=0; i < 4; i++, address++) |
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642 { |
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643 *tmp_buf = pal_priority | (context->vdpmem[address] >> 4); |
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644 tmp_buf += dir; |
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645 *tmp_buf = pal_priority | (context->vdpmem[address] & 0xF); |
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646 tmp_buf += dir; |
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647 } |
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648 } |
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649 |
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650 void render_map_1(vdp_context * context) |
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651 { |
|
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652 render_map(context->col_1, context->tmp_buf_a+SCROLL_BUFFER_DRAW, context); |
|
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653 } |
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|
654 |
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|
655 void render_map_2(vdp_context * context) |
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656 { |
|
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657 render_map(context->col_2, context->tmp_buf_a+SCROLL_BUFFER_DRAW+8, context); |
|
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658 } |
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|
659 |
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660 void render_map_3(vdp_context * context) |
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661 { |
|
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662 render_map(context->col_1, context->tmp_buf_b+SCROLL_BUFFER_DRAW, context); |
|
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663 } |
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|
664 |
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665 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
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666 { |
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667 if (line >= 240) { |
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668 return; |
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669 } |
|
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|
670 render_map(context->col_2, context->tmp_buf_b+SCROLL_BUFFER_DRAW+8, context); |
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671 uint16_t *dst; |
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672 uint32_t *dst32; |
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673 uint8_t *sprite_buf, *plane_a, *plane_b; |
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674 if (col) |
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|
675 { |
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676 col-=2; |
|
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677 if (context->b32) { |
|
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678 dst32 = context->framebuf; |
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679 dst32 += line * 320 + col * 8; |
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680 } else { |
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681 dst = context->framebuf; |
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682 dst += line * 320 + col * 8; |
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683 } |
|
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684 sprite_buf = context->linebuf + col * 8; |
|
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|
685 uint16_t a_src; |
| 40 | 686 if (context->flags & FLAG_WINDOW) { |
| 687 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW; | |
|
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|
688 //a_src = FBUF_SRC_W; |
| 40 | 689 } else { |
| 690 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW - (context->hscroll_a & 0xF); | |
|
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691 //a_src = FBUF_SRC_A; |
| 40 | 692 } |
|
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38
diff
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|
693 plane_b = context->tmp_buf_b + SCROLL_BUFFER_DRAW - (context->hscroll_b & 0xF); |
|
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|
694 uint16_t src; |
| 30 | 695 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
|
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|
696 |
|
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697 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
|
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|
698 for (int i = 0; i < 16; ++plane_a, ++plane_b, ++sprite_buf, ++i) { |
|
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|
699 uint8_t pixel; |
|
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|
700 |
|
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|
701 src = 0; |
|
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diff
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|
702 uint8_t sprite_color = *sprite_buf & 0x3F; |
|
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191
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|
703 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
|
232
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230
diff
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|
704 if (sprite_color == 0x3F) { |
|
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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|
705 src = CRAM_SIZE;//FBUF_SHADOW; |
|
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|
706 } else { |
|
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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diff
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|
707 src = CRAM_SIZE*2;//FBUF_HILIGHT; |
|
230
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|
708 } |
|
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|
709 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
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|
710 pixel = *plane_a; |
|
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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|
711 //src |= a_src; |
|
230
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|
712 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
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|
713 pixel = *plane_b; |
|
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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|
714 //src |= FBUF_SRC_B; |
|
230
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diff
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|
715 } else if (*plane_a & 0xF) { |
|
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191
diff
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|
716 pixel = *plane_a; |
|
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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diff
changeset
|
717 //src |= a_src; |
|
230
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|
718 } else if (*plane_b & 0xF){ |
|
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Implemented shadow hilight mode.
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191
diff
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|
719 pixel = *plane_b; |
|
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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424
diff
changeset
|
720 //src |= FBUF_SRC_B; |
|
230
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191
diff
changeset
|
721 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
722 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
723 //src |= FBUF_SRC_BG; |
|
230
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Implemented shadow hilight mode.
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191
diff
changeset
|
724 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
725 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
726 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
727 pixel = *sprite_buf; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents:
424
diff
changeset
|
728 //src = FBUF_SRC_S; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
729 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
730 pixel = *plane_a; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
731 //src = a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
732 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
733 pixel = *plane_b; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
734 //src = FBUF_SRC_B; |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
735 } else { |
|
9d10669f2579
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Mike Pavone <pavone@retrodev.com>
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232
diff
changeset
|
736 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
737 src = CRAM_SIZE;//FBUF_SHADOW; |
|
230
d3266cee02c9
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191
diff
changeset
|
738 } |
|
233
9d10669f2579
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232
diff
changeset
|
739 if (*sprite_buf & 0xF) { |
|
9d10669f2579
Less broken implementation of shadow/highlight
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232
diff
changeset
|
740 pixel = *sprite_buf; |
|
9d10669f2579
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232
diff
changeset
|
741 if (*sprite_buf & 0xF == 0xE) { |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
742 src = 0;//FBUF_SRC_S; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
743 } /*else { |
|
233
9d10669f2579
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Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
744 src |= FBUF_SRC_S; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
745 }*/ |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
746 } else if (*plane_a & 0xF) { |
|
9d10669f2579
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Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
747 pixel = *plane_a; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
748 //src |= a_src; |
|
233
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749 } else if (*plane_b & 0xF){ |
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|
750 pixel = *plane_b; |
|
426
add9e2f5c0e3
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424
diff
changeset
|
751 //src |= FBUF_SRC_B; |
|
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diff
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|
752 } else { |
|
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232
diff
changeset
|
753 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
426
add9e2f5c0e3
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diff
changeset
|
754 //src |= FBUF_SRC_BG; |
|
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232
diff
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|
755 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
756 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
757 } |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
758 pixel &= 0x3F; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
759 pixel += src; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
760 if (context->b32) { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
761 *(dst32++) = context->colors[pixel]; |
|
add9e2f5c0e3
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Mike Pavone <pavone@retrodev.com>
parents:
424
diff
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|
762 } else { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
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|
763 *(dst++) = context->colors[pixel]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
764 } |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
765 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
20
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diff
changeset
|
766 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
767 } else { |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
changeset
|
768 for (int i = 0; i < 16; ++plane_a, ++plane_b, ++sprite_buf, ++i) { |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
769 uint8_t pixel; |
|
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
770 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
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parents:
191
diff
changeset
|
771 pixel = *sprite_buf; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
772 //src = FBUF_SRC_S; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
773 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
774 pixel = *plane_a; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
775 //src = a_src; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
776 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
777 pixel = *plane_b; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
778 //src = FBUF_SRC_B; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
779 } else if (*sprite_buf & 0xF) { |
|
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
780 pixel = *sprite_buf; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
781 //src = FBUF_SRC_S; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
782 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
783 pixel = *plane_a; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
784 //src = a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
785 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
786 pixel = *plane_b; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
787 //src = FBUF_SRC_B; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
788 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
789 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
790 //src = FBUF_SRC_BG; |
|
230
d3266cee02c9
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Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
791 } |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
792 if (context->b32) { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
793 *(dst32++) = context->colors[pixel & 0x3F]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
794 } else { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
795 *(dst++) = context->colors[pixel & 0x3F]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
796 } |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
797 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
798 } |
|
20
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
799 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 } else { |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 //dst = context->framebuf + line * 320; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 //sprite_buf = context->linebuf + col * 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
803 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 //end = dst + 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 |
| 40 | 808 uint16_t remaining; |
| 809 if (!(context->flags & FLAG_WINDOW)) { | |
| 810 remaining = context->hscroll_a & 0xF; | |
| 811 memcpy(context->tmp_buf_a + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_a + SCROLL_BUFFER_SIZE - remaining, remaining); | |
| 812 } | |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
813 remaining = context->hscroll_b & 0xF; |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
814 memcpy(context->tmp_buf_b + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_b + SCROLL_BUFFER_SIZE - remaining, remaining); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 break;\ |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 external_slot(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 uint16_t address; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 uint32_t mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 case 0: |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
876 context->cur_slot = MAX_DRAWS-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 memset(context->linebuf, 0, LINEBUF_SIZE); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 case 2: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
881 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
882 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
883 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
884 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
885 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 //sprite attribute table scan starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 case 4: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
889 render_sprite_cells( context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 context->sprite_index = 0x80; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 context->slot_counter = MAX_SPRITES_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 case 13: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 case 14: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 case 19: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 //!HSYNC asserted |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 case 22: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
913 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 case 26: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 case 27: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 case 28: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 case 31: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 case 32: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 case 33: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 case 34: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
930 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 case 35: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 mask = 0; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 if (context->regs[REG_MODE_3] & 0x2) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 mask |= 0xF8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 if (context->regs[REG_MODE_3] & 0x1) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 mask |= 0x7; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 line &= mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 address += line * 4; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
946 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 case 36: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 //!HSYNC high |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 case 37: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 case 38: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 case 39: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
953 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 case 40: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 read_map_scroll_a(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 case 41: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
960 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 case 42: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 render_map_1(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 case 43: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 render_map_2(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 44: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 read_map_scroll_b(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 case 45: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
975 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 case 46: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 render_map_3(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 case 47: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 render_map_output(line, 0, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 //reverse context slot counter so it counts the number of sprite slots |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 //filled rather than the number of available slots |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
987 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
|
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
988 context->cur_slot = MAX_SPRITES_LINE-1; |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 context->sprite_draws = MAX_DRAWS; |
|
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
990 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 COLUMN_RENDER_BLOCK(2, 48) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 COLUMN_RENDER_BLOCK(4, 56) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 COLUMN_RENDER_BLOCK(6, 64) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 COLUMN_RENDER_BLOCK(10, 80) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 COLUMN_RENDER_BLOCK(12, 88) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 COLUMN_RENDER_BLOCK(14, 96) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 COLUMN_RENDER_BLOCK(18, 112) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 COLUMN_RENDER_BLOCK(20, 120) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 COLUMN_RENDER_BLOCK(22, 128) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 COLUMN_RENDER_BLOCK(26, 144) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 COLUMN_RENDER_BLOCK(28, 152) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 COLUMN_RENDER_BLOCK(30, 160) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 COLUMN_RENDER_BLOCK(34, 176) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 COLUMN_RENDER_BLOCK(36, 184) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 COLUMN_RENDER_BLOCK(38, 192) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 case 208: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 case 209: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 default: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 //leftovers from HSYNC clock change nonsense |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 { |
| 37 | 1024 uint16_t address; |
| 1025 uint32_t mask; | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 case 0: |
| 37 | 1030 context->cur_slot = MAX_DRAWS_H32-1; |
| 1031 memset(context->linebuf, 0, LINEBUF_SIZE); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 case 2: |
| 37 | 1034 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1035 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1036 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1037 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1038 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1039 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 break; |
| 37 | 1041 //sprite attribute table scan starts |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 case 4: |
| 37 | 1043 render_sprite_cells( context); |
| 1044 context->sprite_index = 0x80; | |
| 1045 context->slot_counter = MAX_SPRITES_LINE_H32; | |
| 1046 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 case 13: |
| 37 | 1057 render_sprite_cells(context); |
| 1058 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 case 14: |
| 37 | 1060 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 case 19: |
| 37 | 1067 //HSYNC start |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 case 22: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 case 26: |
| 37 | 1075 render_sprite_cells(context); |
| 1076 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 case 27: |
| 37 | 1079 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 case 28: |
| 37 | 1082 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
| 1083 mask = 0; | |
| 1084 if (context->regs[REG_MODE_3] & 0x2) { | |
| 1085 mask |= 0xF8; | |
| 1086 } | |
| 1087 if (context->regs[REG_MODE_3] & 0x1) { | |
| 1088 mask |= 0x7; | |
| 1089 } | |
| 1090 line &= mask; | |
| 1091 address += line * 4; | |
| 1092 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
| 1093 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
| 1094 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 case 31: |
| 37 | 1099 case 32: |
| 1100 render_sprite_cells(context); | |
| 1101 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1102 break; |
| 37 | 1103 //!HSYNC high |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1104 case 33: |
| 37 | 1105 read_map_scroll_a(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1106 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 case 34: |
| 37 | 1108 render_sprite_cells(context); |
| 1109 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1110 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1111 case 35: |
| 37 | 1112 render_map_1(context); |
| 1113 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 case 36: |
| 37 | 1116 render_map_2(context); |
| 1117 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 case 37: |
| 37 | 1120 read_map_scroll_b(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 case 38: |
| 37 | 1123 render_sprite_cells(context); |
| 1124 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1125 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1126 case 39: |
| 37 | 1127 render_map_3(context); |
| 1128 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 case 40: |
| 37 | 1131 render_map_output(line, 0, context); |
| 1132 scan_sprite_table(line, context);//Just a guess | |
| 1133 //reverse context slot counter so it counts the number of sprite slots | |
| 1134 //filled rather than the number of available slots | |
| 1135 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
| 1136 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
| 1137 context->sprite_draws = MAX_DRAWS_H32; | |
| 1138 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 break; |
| 37 | 1140 COLUMN_RENDER_BLOCK(2, 41) |
| 1141 COLUMN_RENDER_BLOCK(4, 49) | |
| 1142 COLUMN_RENDER_BLOCK(6, 57) | |
| 1143 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
| 1144 COLUMN_RENDER_BLOCK(10, 73) | |
| 1145 COLUMN_RENDER_BLOCK(12, 81) | |
| 1146 COLUMN_RENDER_BLOCK(14, 89) | |
| 1147 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
| 1148 COLUMN_RENDER_BLOCK(18, 105) | |
| 1149 COLUMN_RENDER_BLOCK(20, 113) | |
| 1150 COLUMN_RENDER_BLOCK(22, 121) | |
| 1151 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
| 1152 COLUMN_RENDER_BLOCK(26, 137) | |
| 1153 COLUMN_RENDER_BLOCK(28, 145) | |
| 1154 COLUMN_RENDER_BLOCK(30, 153) | |
| 1155 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
|
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1156 case 169: |
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1157 case 170: |
| 37 | 1158 external_slot(context); |
|
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|
1159 break; |
|
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|
1160 } |
|
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|
1161 } |
|
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|
1162 void latch_mode(vdp_context * context) |
|
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|
1163 { |
|
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|
1164 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
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1165 } |
|
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1166 |
|
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1167 int is_refresh(vdp_context * context, uint32_t slot) |
|
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1168 { |
|
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1169 if (context->latched_mode & BIT_H40) { |
|
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1170 //TODO: Figure out the exact behavior that reduces DMA slots for direct color DMA demos |
|
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1171 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210 || (slot < 6 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
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1172 } else { |
|
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1173 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
|
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1174 //These numbers are guesses based on H40 numbers |
|
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1175 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152 || (slot < 5 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
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1176 //The numbers below are the refresh slots during active display |
|
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1177 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
|
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1178 } |
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1179 } |
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|
1180 |
|
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1181 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
|
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1182 { |
|
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1183 if (line > 0) { |
|
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1184 line -= 1; |
|
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|
1185 int starti = -1; |
|
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1186 if (context->latched_mode & BIT_H40) { |
|
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1187 if (slot >= 50 && slot < 210) { |
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1188 uint32_t x = (slot-50)*2; |
|
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1189 starti = line * 320 + x; |
|
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1190 } |
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|
1191 } else { |
|
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1192 if (slot >= 43 && slot < 171) { |
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1193 uint32_t x = (slot-43)*2; |
|
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1194 starti = line * 320 + x; |
|
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1195 } |
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1196 } |
|
426
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1197 if (starti >= 0) { |
|
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1198 if (context->b32) { |
|
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1199 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
|
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1200 uint32_t * start = context->framebuf; |
|
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1201 start += starti; |
|
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1202 for (int i = 0; i < 2; i++) { |
|
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1203 *(start++) = color; |
|
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1204 } |
|
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|
1205 } else { |
|
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1206 uint16_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
|
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|
1207 uint16_t * start = context->framebuf; |
|
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|
1208 start += starti; |
|
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1209 for (int i = 0; i < 2; i++) { |
|
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1210 *(start++) = color; |
|
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1211 } |
|
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|
1212 } |
|
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|
1213 } |
|
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|
1214 } |
|
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|
1215 } |
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|
1216 |
|
20
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|
1217 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
|
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|
1218 { |
|
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diff
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|
1219 while(context->cycles < target_cycles) |
|
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|
1220 { |
|
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|
1221 uint32_t line = context->cycles / MCLKS_LINE; |
|
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|
1222 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
334
4c91470e1a53
Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
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333
diff
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|
1223 if (!context->cycles) { |
|
54
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|
1224 latch_mode(context); |
|
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|
1225 } |
|
317
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|
1226 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
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|
1227 if (linecyc == 0) { |
|
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|
1228 if (line <= 1 || line >= active_lines) { |
|
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|
1229 context->hint_counter = context->regs[REG_HINT]; |
|
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1230 } else if (context->hint_counter) { |
|
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|
1231 context->hint_counter--; |
|
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1232 } else { |
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|
1233 context->flags2 |= FLAG2_HINT_PENDING; |
|
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1234 context->hint_counter = context->regs[REG_HINT]; |
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|
1235 } |
|
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|
1236 } else if(line == active_lines) { |
|
331
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|
1237 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
|
317
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1238 if (linecyc == intcyc) { |
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|
1239 context->flags2 |= FLAG2_VINT_PENDING; |
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1240 } |
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1241 } |
|
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|
1242 uint32_t inccycles, slot; |
|
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1243 if (context->latched_mode & BIT_H40){ |
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1244 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
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1245 slot = linecyc/MCLKS_SLOT_H40; |
|
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1246 inccycles = MCLKS_SLOT_H40; |
|
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|
1247 } else if(linecyc < MCLK_WEIRD_END) { |
|
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|
1248 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
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|
1249 { |
|
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|
1250 case 0: |
|
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1251 inccycles = 19; |
|
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diff
changeset
|
1252 slot = 0; |
|
57453d3d8be4
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parents:
329
diff
changeset
|
1253 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1254 case 19: |
|
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Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1255 slot = 1; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1256 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1257 break; |
|
57453d3d8be4
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parents:
329
diff
changeset
|
1258 case 39: |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1259 slot = 2; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1260 inccycles = 20; |
|
57453d3d8be4
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parents:
329
diff
changeset
|
1261 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1262 case 59: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1263 slot = 3; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1264 inccycles = 20; |
|
57453d3d8be4
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parents:
329
diff
changeset
|
1265 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1266 case 79: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1267 slot = 4; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1268 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1269 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1270 case 97: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1271 slot = 5; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1272 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1273 break; |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1274 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1275 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1276 inccycles = 20; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1277 break; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1278 case 137: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1279 slot = 7; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1280 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1281 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1282 case 157: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1283 slot = 8; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1284 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1285 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1286 case 175: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1287 slot = 9; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1288 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1289 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1290 case 195: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1291 slot = 10; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1292 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1293 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1294 case 215: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1295 slot = 11; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1296 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1297 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1298 case 235: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1299 slot = 12; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1300 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1301 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1302 case 253: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1303 slot = 13; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1304 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1305 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1306 case 273: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1307 slot = 14; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1308 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1309 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1310 case 293: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1311 slot = 15; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1312 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1313 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1314 case 313: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1315 slot = 16; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1316 inccycles = 19; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1317 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1318 default: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1319 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1320 exit(1); |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1321 } |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1322 slot += HSYNC_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1323 } else { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1324 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1325 inccycles = MCLKS_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1326 } |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1327 } else { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1328 inccycles = MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1329 slot = linecyc/MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1330 } |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1331 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1332 //first sort-of active line is treated as 255 internally |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1333 //it's used for gathering sprite info for line |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1334 line = (line - 1) & 0xFF; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1335 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1336 //Convert to slot number |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1337 if (context->latched_mode & BIT_H40){ |
|
330
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parents:
329
diff
changeset
|
1338 vdp_h40(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1339 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1340 vdp_h32(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1341 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1342 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1343 if (!is_refresh(context, slot)) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1344 external_slot(context); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1345 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1346 if (line < active_lines) { |
|
330
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1347 check_render_bg(context, line, slot); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1348 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1349 } |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1350 context->cycles += inccycles; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1351 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1352 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1353 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1354 uint32_t vdp_run_to_vblank(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1355 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1356 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1357 vdp_run_context(context, target_cycles); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1358 return context->cycles; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1359 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1360 |
| 75 | 1361 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
| 1362 { | |
| 1363 for(;;) { | |
| 1364 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
| 1365 if (!dmalen) { | |
| 1366 dmalen = 0x10000; | |
| 1367 } | |
| 1368 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
| 1369 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
| 1370 //DMA copies take twice as long to complete since they require a read and a write | |
| 1371 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
| 1372 min_dma_complete *= 2; | |
| 1373 } | |
| 1374 min_dma_complete += context->cycles; | |
| 1375 if (target_cycles < min_dma_complete) { | |
| 1376 vdp_run_context(context, target_cycles); | |
| 1377 return; | |
| 1378 } else { | |
| 1379 vdp_run_context(context, min_dma_complete); | |
| 1380 if (!(context->flags & FLAG_DMA_RUN)) { | |
| 1381 return; | |
| 1382 } | |
| 1383 } | |
| 1384 } | |
| 1385 } | |
| 1386 | |
| 1387 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
|
54
3b79cbcf6846
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parents:
43
diff
changeset
|
1388 { |
|
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents:
56
diff
changeset
|
1389 //printf("control port write: %X\n", value); |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1390 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1391 return -1; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1392 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1393 if (context->flags & FLAG_PENDING) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1394 context->address = (context->address & 0x3FFF) | (value << 14); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1395 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
| 75 | 1396 context->flags &= ~FLAG_PENDING; |
|
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
1397 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1398 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
|
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1399 // |
| 75 | 1400 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
| 1401 //DMA copy or 68K -> VDP, transfer starts immediately | |
| 1402 context->flags |= FLAG_DMA_RUN; | |
|
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1403 context->dma_cd = context->cd; |
| 75 | 1404 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1405 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
| 75 | 1406 return 1; |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1407 } else { |
|
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1408 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
| 75 | 1409 } |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1410 } else { |
|
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1411 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
| 75 | 1412 } |
|
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1413 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1414 } else { |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1415 if ((value & 0xC000) == 0x8000) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1416 //Register write |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1417 uint8_t reg = (value >> 8) & 0x1F; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1418 if (reg < VDP_REGS) { |
|
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
1419 //printf("register %d set to %X\n", reg, value & 0xFF); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1420 context->regs[reg] = value; |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1421 if (reg == REG_MODE_2) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1422 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1423 } |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1424 if (reg == REG_MODE_4) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1425 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
|
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1426 if (!context->double_res) { |
|
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1427 context->framebuf = context->oddbuf; |
|
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1428 } |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1429 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1430 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1431 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1432 context->flags |= FLAG_PENDING; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1433 context->address = (context->address &0xC000) | (value & 0x3FFF); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1434 context->cd = (context->cd &0x3C) | (value >> 14); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1435 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1436 } |
| 75 | 1437 return 0; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1438 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1439 |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1440 int vdp_data_port_write(vdp_context * context, uint16_t value) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1441 { |
|
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents:
56
diff
changeset
|
1442 //printf("data port write: %X\n", value); |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1443 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1444 return -1; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1445 } |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1446 if (!(context->cd & 1)) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1447 //ignore writes when cd is configured for read |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1448 return 0; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1449 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1450 context->flags &= ~FLAG_PENDING; |
|
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1451 /*if (context->fifo_cur == context->fifo_end) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1452 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
|
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1453 }*/ |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1454 while (context->fifo_cur == context->fifo_end) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1455 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1456 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1457 context->fifo_cur->cycle = context->cycles; |
| 138 | 1458 context->fifo_cur->address = context->address; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1459 context->fifo_cur->value = value; |
| 138 | 1460 context->fifo_cur->cd = context->cd; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1461 context->fifo_cur->partial = 0; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1462 context->fifo_cur++; |
| 138 | 1463 context->address += context->regs[REG_AUTOINC]; |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1464 return 0; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1465 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1466 |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1467 uint16_t vdp_control_port_read(vdp_context * context) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1468 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1469 context->flags &= ~FLAG_PENDING; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1470 uint16_t value = 0x3400; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1471 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1472 value |= 0x200; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1473 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1474 if (context->fifo_cur == context->fifo_end) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1475 value |= 0x100; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1476 } |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1477 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1478 value |= 0x80; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1479 } |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1480 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1481 value |= 0x10; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1482 } |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1483 uint32_t line= context->cycles / MCLKS_LINE; |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1484 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1485 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1486 value |= 0x8; |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1487 } |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1488 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1489 value |= 0x4; |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1490 } |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1491 if (context->flags & FLAG_DMA_RUN) { |
|
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1492 value |= 0x2; |
| 75 | 1493 } |
|
317
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1494 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1495 value |= 0x1; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1496 } |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1497 //TODO: Sprite overflow, sprite collision, odd frame flag |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1498 return value; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1499 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1500 |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1501 uint16_t vdp_data_port_read(vdp_context * context) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1502 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1503 context->flags &= ~FLAG_PENDING; |
| 138 | 1504 if (context->cd & 1) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1505 return 0; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1506 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1507 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1508 context->flags &= ~FLAG_UNUSED_SLOT; |
|
3b79cbcf6846
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parents:
43
diff
changeset
|
1509 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1510 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1511 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1512 uint16_t value = 0; |
| 138 | 1513 switch (context->cd & 0xF) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1514 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1515 case VRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1516 value = context->vdpmem[context->address] << 8; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1517 context->flags &= ~FLAG_UNUSED_SLOT; |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1518 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1519 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1520 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1521 value |= context->vdpmem[context->address ^ 1]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1522 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1523 case CRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1524 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1525 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1526 case VSRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1527 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1528 value = context->vsram[context->address & 63]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1529 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1530 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1531 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1532 context->address += context->regs[REG_AUTOINC]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1533 return value; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1534 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1535 |
| 137 | 1536 uint16_t vdp_hv_counter_read(vdp_context * context) |
| 1537 { | |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1538 //TODO: deal with clock adjustemnts handled in vdp_run_context |
| 137 | 1539 uint32_t line= context->cycles / MCLKS_LINE; |
| 1540 if (!line) { | |
| 1541 line = 0xFF; | |
| 1542 } else { | |
| 1543 line--; | |
| 1544 if (line > 0xEA) { | |
| 1545 line = (line + 0xFA) & 0xFF; | |
| 1546 } | |
| 1547 } | |
| 1548 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
| 1549 if (context->latched_mode & BIT_H40) { | |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1550 uint32_t slot; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1551 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1552 slot = linecyc/MCLKS_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1553 } else if(linecyc < MCLK_WEIRD_END) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1554 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1555 { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1556 case 0: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1557 slot = 0; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1558 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1559 case 19: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1560 slot = 1; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1561 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1562 case 39: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1563 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1564 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1565 case 59: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1566 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1567 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1568 case 79: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1569 slot = 3; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1570 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1571 case 97: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1572 slot = 4; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1573 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1574 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1575 slot = 5; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1576 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1577 case 137: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1578 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1579 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1580 case 157: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1581 slot = 7; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1582 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1583 case 175: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1584 slot = 8; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1585 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1586 case 195: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1587 slot = 9; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1588 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1589 case 215: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1590 slot = 11; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1591 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1592 case 235: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1593 slot = 12; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1594 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1595 case 253: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1596 slot = 13; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1597 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1598 case 273: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1599 slot = 14; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1600 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1601 case 293: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1602 slot = 15; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1603 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1604 case 313: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1605 slot = 16; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1606 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1607 default: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1608 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1609 exit(1); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1610 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1611 slot += HSYNC_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1612 } else { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1613 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1614 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1615 linecyc = slot * 2; |
| 137 | 1616 if (linecyc >= 86) { |
| 1617 linecyc -= 86; | |
| 1618 } else { | |
| 1619 linecyc += 334; | |
| 1620 } | |
| 1621 if (linecyc > 0x16C) { | |
| 1622 linecyc += 92; | |
| 1623 } | |
| 1624 } else { | |
| 1625 linecyc /= 10; | |
| 1626 if (linecyc >= 74) { | |
| 1627 linecyc -= 74; | |
| 1628 } else { | |
| 1629 linecyc += 268; | |
| 1630 } | |
| 1631 if (linecyc > 0x127) { | |
| 1632 linecyc += 170; | |
| 1633 } | |
| 1634 } | |
| 1635 linecyc &= 0xFF; | |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1636 if (context->double_res) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1637 line <<= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1638 if (line & 0x100) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1639 line |= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1640 } |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1641 } |
| 137 | 1642 return (line << 8) | linecyc; |
| 1643 } | |
| 1644 | |
|
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1645 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1646 { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1647 context->cycles -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1648 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1649 if (start->cycle >= deduction) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1650 start->cycle -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1651 } else { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1652 start->cycle = 0; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1653 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1654 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1655 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1656 |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1657 uint32_t vdp_next_hint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1658 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1659 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1660 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1661 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1662 if (context->flags2 & FLAG2_HINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1663 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1664 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1665 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1666 uint32_t line = context->cycles / MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1667 if (line >= active_lines) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1668 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1669 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1670 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1671 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1672 if (!line) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1673 hcycle += MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1674 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1675 return hcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1676 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1677 |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1678 uint32_t vdp_next_vint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1679 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1680 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1681 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1682 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1683 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1684 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1685 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1686 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1687 uint32_t vcycle = MCLKS_LINE * active_lines; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1688 if (context->latched_mode & BIT_H40) { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1689 vcycle += VINT_CYCLE_H40; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1690 } else { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1691 vcycle += VINT_CYCLE_H32; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1692 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1693 if (vcycle < context->cycles) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1694 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1695 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1696 return vcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1697 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1698 |
| 333 | 1699 uint32_t vdp_next_vint_z80(vdp_context * context) |
| 1700 { | |
| 1701 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
| 1702 uint32_t vcycle = MCLKS_LINE * active_lines; | |
| 1703 if (context->latched_mode & BIT_H40) { | |
| 1704 vcycle += VINT_CYCLE_H40; | |
| 1705 } else { | |
| 1706 vcycle += VINT_CYCLE_H32; | |
| 1707 } | |
| 1708 return vcycle; | |
| 1709 } | |
| 1710 | |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1711 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1712 { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1713 if (int_num == 6) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1714 context->flags2 &= ~FLAG2_VINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1715 } else if(int_num ==4) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1716 context->flags2 &= ~FLAG2_HINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1717 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1718 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1719 |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1720 #define GST_VDP_REGS 0xFA |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1721 #define GST_VDP_MEM 0x12478 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1722 |
|
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1723 uint8_t vdp_load_gst(vdp_context * context, FILE * state_file) |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1724 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1725 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1726 fseek(state_file, GST_VDP_REGS, SEEK_SET); |
|
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1727 if (fread(context->regs, 1, VDP_REGS, state_file) != VDP_REGS) { |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1728 fputs("Failed to read VDP registers from savestate\n", stderr); |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1729 return 0; |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1730 } |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1731 context->double_res = (context->regs[REG_MODE_4] & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1732 if (!context->double_res) { |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1733 context->framebuf = context->oddbuf; |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1734 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1735 latch_mode(context); |
|
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1736 if (fread(tmp_buf, 1, sizeof(tmp_buf), state_file) != sizeof(tmp_buf)) { |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1737 fputs("Failed to read CRAM from savestate\n", stderr); |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1738 return 0; |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1739 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1740 for (int i = 0; i < CRAM_SIZE; i++) { |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1741 uint16_t value; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1742 context->cram[i] = value = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1743 context->colors[i] = color_map[value & 0xEEE]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1744 context->colors[i + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1745 context->colors[i + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1746 } |
|
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1747 if (fread(tmp_buf, 2, VSRAM_SIZE, state_file) != VSRAM_SIZE) { |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1748 fputs("Failed to read VSRAM from savestate\n", stderr); |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1749 return 0; |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1750 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1751 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
23
3e924bb56560
Fix endianness of VSRAM when read from Genecyst save state
Mike Pavone <pavone@retrodev.com>
parents:
22
diff
changeset
|
1752 context->vsram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1753 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1754 fseek(state_file, GST_VDP_MEM, SEEK_SET); |
|
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1755 if (fread(context->vdpmem, 1, VRAM_SIZE, state_file) != VRAM_SIZE) { |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1756 fputs("Failed to read VRAM from savestate\n", stderr); |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1757 return 0; |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1758 } |
|
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
417
diff
changeset
|
1759 return 1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1760 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1761 |
|
56
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1762 void vdp_save_state(vdp_context * context, FILE * outfile) |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1763 { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1764 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1765 fseek(outfile, GST_VDP_REGS, SEEK_SET); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1766 fwrite(context->regs, 1, VDP_REGS, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1767 for (int i = 0; i < CRAM_SIZE; i++) { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1768 tmp_buf[i*2] = context->cram[i]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1769 tmp_buf[i*2+1] = context->cram[i] >> 8; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1770 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1771 fwrite(tmp_buf, 1, sizeof(tmp_buf), outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1772 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1773 tmp_buf[i*2] = context->vsram[i]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1774 tmp_buf[i*2+1] = context->vsram[i] >> 8; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1775 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1776 fwrite(tmp_buf, 2, VSRAM_SIZE, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1777 fseek(outfile, GST_VDP_MEM, SEEK_SET); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1778 fwrite(context->vdpmem, 1, VRAM_SIZE, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1779 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1780 |