Mercurial > repos > blastem
annotate vdp.c @ 467:140af5509ce7
Added copyright notice to source files and added GPL license text in COPYING
author | Mike Pavone <pavone@retrodev.com> |
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date | Tue, 10 Sep 2013 23:31:08 -0700 |
parents | 5677c053edd6 |
children | 541c1ae8abf3 |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "vdp.h" |
75 | 7 #include "blastem.h" |
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8 #include <stdlib.h> |
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9 #include <string.h> |
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10 #include "render.h" |
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11 |
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12 #define NTSC_ACTIVE 225 |
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13 #define PAL_ACTIVE 241 |
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14 #define BUF_BIT_PRIORITY 0x40 |
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15 #define MAP_BIT_PRIORITY 0x8000 |
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16 #define MAP_BIT_H_FLIP 0x800 |
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17 #define MAP_BIT_V_FLIP 0x1000 |
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18 |
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19 #define SCROLL_BUFFER_SIZE 32 |
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20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
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21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
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22 |
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23 #define FIFO_SIZE 4 |
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25 #define MCLKS_SLOT_H40 16 |
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26 #define MCLKS_SLOT_H32 20 |
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27 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
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28 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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29 #define HSYNC_SLOT_H40 21 |
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30 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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31 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
331
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32 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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33 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
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34 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
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35 #define FIFO_LATENCY 3 |
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36 |
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37 int32_t color_map[1 << 12]; |
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38 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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39 |
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40 uint8_t debug_base[][3] = { |
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41 {127, 127, 127}, //BG |
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42 {0, 0, 127}, //A |
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43 {127, 0, 0}, //Window |
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44 {0, 127, 0}, //B |
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45 {127, 0, 127} //Sprites |
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46 }; |
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47 |
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48 uint8_t color_map_init_done; |
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49 |
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50 void init_vdp_context(vdp_context * context) |
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51 { |
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52 memset(context, 0, sizeof(*context)); |
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53 context->vdpmem = malloc(VRAM_SIZE); |
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54 memset(context->vdpmem, 0, VRAM_SIZE); |
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55 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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56 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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57 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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58 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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59 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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60 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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61 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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62 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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63 context->sprite_draws = MAX_DRAWS; |
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64 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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65 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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66 context->b32 = render_depth() == 32; |
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67 if (!color_map_init_done) { |
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68 uint8_t b,g,r; |
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69 for (uint16_t color = 0; color < (1 << 12); color++) { |
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70 if (color & FBUF_SHADOW) { |
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71 b = levels[(color >> 9) & 0x7]; |
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72 g = levels[(color >> 5) & 0x7]; |
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73 r = levels[(color >> 1) & 0x7]; |
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74 } else if(color & FBUF_HILIGHT) { |
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75 b = levels[((color >> 9) & 0x7) + 7]; |
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76 g = levels[((color >> 5) & 0x7) + 7]; |
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77 r = levels[((color >> 1) & 0x7) + 7]; |
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78 } else { |
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79 b = levels[(color >> 8) & 0xE]; |
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80 g = levels[(color >> 4) & 0xE]; |
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81 r = levels[color & 0xE]; |
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82 } |
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83 color_map[color] = render_map_color(r, g, b); |
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84 } |
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85 color_map_init_done = 1; |
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86 } |
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87 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
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88 { |
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89 uint8_t src = color & DBG_SRC_MASK; |
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90 if (src > DBG_SRC_S) { |
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91 context->debugcolors[color] = 0; |
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92 } else { |
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93 uint8_t r,g,b; |
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94 b = debug_base[src][0]; |
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95 g = debug_base[src][1]; |
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96 r = debug_base[src][2]; |
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97 if (color & DBG_PRIORITY) |
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98 { |
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99 if (b) { |
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100 b += 48; |
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101 } |
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102 if (g) { |
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103 g += 48; |
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104 } |
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105 if (r) { |
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106 r += 48; |
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107 } |
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108 } |
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109 if (color & DBG_SHADOW) { |
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110 b /= 2; |
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111 g /= 2; |
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112 r /=2 ; |
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113 } |
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114 if (color & DBG_HILIGHT) { |
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115 if (b) { |
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116 b += 72; |
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117 } |
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118 if (g) { |
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119 g += 72; |
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120 } |
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121 if (r) { |
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122 r += 72; |
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123 } |
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124 } |
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125 context->debugcolors[color] = render_map_color(r, g, b); |
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126 } |
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127 } |
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128 } |
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129 |
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130 int is_refresh(vdp_context * context, uint32_t slot) |
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131 { |
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132 if (context->latched_mode & BIT_H40) { |
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133 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210); |
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134 } else { |
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135 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
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136 //These numbers are guesses based on H40 numbers |
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137 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152); |
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138 //The numbers below are the refresh slots during active display |
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139 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
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140 } |
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141 } |
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142 |
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143 void render_sprite_cells(vdp_context * context) |
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144 { |
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145 if (context->cur_slot >= context->sprite_draws) { |
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146 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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147 |
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148 uint16_t dir; |
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149 int16_t x; |
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150 if (d->h_flip) { |
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151 x = d->x_pos + 7; |
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152 dir = -1; |
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153 } else { |
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154 x = d->x_pos; |
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155 dir = 1; |
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156 } |
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157 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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158 context->cur_slot--; |
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159 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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160 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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161 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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162 } |
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163 x += dir; |
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164 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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165 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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166 } |
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167 x += dir; |
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168 } |
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169 } |
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170 } |
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171 |
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172 void vdp_print_sprite_table(vdp_context * context) |
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173 { |
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174 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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175 uint16_t current_index = 0; |
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176 uint8_t count = 0; |
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177 do { |
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178 uint16_t address = current_index * 8 + sat_address; |
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179 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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180 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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181 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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182 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
322
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183 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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184 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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185 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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186 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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187 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
322
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188 current_index = link; |
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189 count++; |
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190 } while (current_index != 0 && count < 80); |
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191 } |
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192 |
327
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193 void vdp_print_reg_explain(vdp_context * context) |
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194 { |
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195 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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196 printf("**Mode Group**\n" |
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197 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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198 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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199 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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200 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
450
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201 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
327
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202 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
450
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203 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
327
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204 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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205 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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206 hscroll[context->regs[REG_MODE_3] & 0x3], |
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207 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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208 printf("\n**Table Group**\n" |
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209 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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210 "03: %.2X | Window Name Table: $%.4X\n" |
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211 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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212 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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213 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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214 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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215 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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216 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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217 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
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218 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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219 char * sizes[] = {"32", "64", "invalid", "128"}; |
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220 printf("\n**Misc Group**\n" |
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221 "07: %.2X | Backdrop Color: $%X\n" |
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222 "0A: %.2X | H-Int Counter: %u\n" |
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223 "0F: %.2X | Auto-increment: $%X\n" |
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224 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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225 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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226 context->regs[REG_HINT], context->regs[REG_HINT], |
327
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227 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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228 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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229 printf("\n**Internal Group**\n" |
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230 "Address: %X\n" |
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231 "CD: %X\n" |
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232 "Pending: %s\n", |
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233 context->address, context->cd, (context->flags & FLAG_PENDING) ? "true" : "false"); |
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234 |
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235 //TODO: Window Group, DMA Group |
327
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236 } |
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237 |
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238 void scan_sprite_table(uint32_t line, vdp_context * context) |
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239 { |
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240 if (context->sprite_index && context->slot_counter) { |
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241 line += 1; |
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242 line &= 0xFF; |
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243 uint16_t ymask, ymin; |
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244 uint8_t height_mult; |
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245 if (context->double_res) { |
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246 line *= 2; |
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247 if (context->framebuf != context->oddbuf) { |
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248 line++; |
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249 } |
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250 ymask = 0x3FF; |
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251 ymin = 256; |
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252 height_mult = 16; |
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253 } else { |
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254 ymask = 0x1FF; |
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255 ymin = 128; |
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256 height_mult = 8; |
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257 } |
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258 context->sprite_index &= 0x7F; |
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259 if (context->latched_mode & BIT_H40) { |
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260 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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261 context->sprite_index = 0; |
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262 return; |
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263 } |
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264 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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265 context->sprite_index = 0; |
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266 return; |
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267 } |
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268 //TODO: Read from SAT cache rather than from VRAM |
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269 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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270 uint16_t address = context->sprite_index * 8 + sat_address; |
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271 line += ymin; |
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272 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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273 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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274 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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275 if (y <= line && line < (y + height)) { |
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276 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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277 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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278 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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279 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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280 } |
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281 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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282 if (context->sprite_index && context->slot_counter) |
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283 { |
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284 address = context->sprite_index * 8 + sat_address; |
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285 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
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286 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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287 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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288 if (y <= line && line < (y + height)) { |
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289 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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290 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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291 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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292 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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293 } |
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294 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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295 } |
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296 } |
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297 } |
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298 |
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299 void read_sprite_x(uint32_t line, vdp_context * context) |
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300 { |
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301 if (context->cur_slot >= context->slot_counter) { |
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302 if (context->sprite_draws) { |
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303 line += 1; |
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304 line &= 0xFF; |
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305 //in tiles |
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306 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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307 //in pixels |
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308 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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309 if (context->double_res) { |
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310 line *= 2; |
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311 if (context->framebuf != context->oddbuf) { |
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312 line++; |
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313 } |
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314 height *= 2; |
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315 } |
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316 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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317 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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318 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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319 uint8_t row; |
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320 if (tileinfo & MAP_BIT_V_FLIP) { |
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321 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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322 } else { |
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323 row = line-context->sprite_info_list[context->cur_slot].y; |
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324 } |
413
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325 uint16_t address; |
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326 if (context->double_res) { |
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327 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
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328 } else { |
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329 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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330 } |
323
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331 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
36
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332 if (x) { |
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333 context->flags |= FLAG_CAN_MASK; |
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334 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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335 context->flags |= FLAG_MASKED; |
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336 } |
450
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337 |
36
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338 context->flags &= ~FLAG_DOT_OFLOW; |
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339 int16_t i; |
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340 if (context->flags & FLAG_MASKED) { |
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341 for (i=0; i < width && context->sprite_draws; i++) { |
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342 --context->sprite_draws; |
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343 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
34
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344 } |
36
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345 } else { |
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346 x -= 128; |
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347 int16_t base_x = x; |
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348 int16_t dir; |
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349 if (tileinfo & MAP_BIT_H_FLIP) { |
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350 x += (width-1) * 8; |
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351 dir = -8; |
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352 } else { |
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353 dir = 8; |
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354 } |
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355 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
35
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356 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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357 --context->sprite_draws; |
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358 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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359 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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360 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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361 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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362 } |
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363 } |
36
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364 if (i < width) { |
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365 context->flags |= FLAG_DOT_OFLOW; |
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366 } |
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367 context->cur_slot--; |
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368 } else { |
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369 context->flags |= FLAG_DOT_OFLOW; |
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370 } |
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371 } |
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372 } |
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373 |
427
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374 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
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375 { |
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376 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
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377 context->cram[addr] = value; |
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378 context->colors[addr] = color_map[value & 0xEEE]; |
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379 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
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380 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
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381 } |
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382 |
54
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diff
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|
383 #define VRAM_READ 0 |
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384 #define VRAM_WRITE 1 |
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385 #define CRAM_READ 8 |
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386 #define CRAM_WRITE 3 |
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387 #define VSRAM_READ 4 |
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388 #define VSRAM_WRITE 5 |
75 | 389 #define DMA_START 0x20 |
54
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390 |
20
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391 void external_slot(vdp_context * context) |
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392 { |
460
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393 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
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394 if (context->fifo_cur != start && start->cycle <= context->cycles) { |
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395 switch (start->cd & 0xF) |
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396 { |
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397 case VRAM_WRITE: |
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398 if (start->partial) { |
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399 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); |
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400 context->vdpmem[start->address ^ 1] = start->value; |
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401 } else { |
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402 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); |
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403 context->vdpmem[start->address] = start->value >> 8; |
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404 start->partial = 1; |
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|
405 //skip auto-increment and removal of entry from fifo |
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diff
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|
406 return; |
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diff
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|
407 } |
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|
408 break; |
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diff
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|
409 case CRAM_WRITE: { |
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diff
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|
410 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
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411 write_cram(context, start->address, start->value); |
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|
412 break; |
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|
413 } |
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diff
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|
414 case VSRAM_WRITE: |
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|
415 if (((start->address/2) & 63) < VSRAM_SIZE) { |
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416 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
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417 context->vsram[(start->address/2) & 63] = start->value; |
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|
418 } |
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419 |
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|
420 break; |
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|
421 } |
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diff
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|
422 fifo_entry * cur = start+1; |
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423 if (cur < context->fifo_cur) { |
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424 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); |
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425 } |
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426 context->fifo_cur -= 1; |
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|
427 } else { |
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428 context->flags |= FLAG_UNUSED_SLOT; |
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429 } |
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|
430 } |
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431 |
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432 void run_dma_src(vdp_context * context, uint32_t slot) |
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433 { |
75 | 434 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
435 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
436 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
460
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437 if (context->fifo_cur == context->fifo_end) { |
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438 return; |
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439 } |
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440 uint16_t read_val; |
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441 uint8_t ran_source = 0, partial = 0; |
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442 uint16_t dma_len; |
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443 switch(context->regs[REG_DMASRC_H] & 0xC0) |
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444 { |
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445 //68K -> VDP |
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446 case 0: |
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447 case 0x40: |
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448 if (!slot || !is_refresh(context, slot-1)) { |
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449 read_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
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450 ran_source = 1; |
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451 } |
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452 break; |
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453 //Copy |
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454 case 0xC0: |
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455 if (context->flags & FLAG_UNUSED_SLOT) { |
131
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456 switch(context->dma_cd & 0xF) |
75 | 457 { |
458 case VRAM_WRITE: | |
460
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459 read_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; |
75 | 460 break; |
427
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426
diff
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461 case CRAM_WRITE: |
460
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462 read_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; |
75 | 463 break; |
464 case VSRAM_WRITE: | |
460
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465 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { |
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466 read_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; |
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467 } else { |
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468 read_val = 0; |
75 | 469 } |
470 break; | |
471 } | |
460
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472 ran_source = 1; |
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473 context->flags &= ~FLAG_UNUSED_SLOT; |
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474 } |
460
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475 break; |
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476 case 0x80: |
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477 read_val = (context->cd & 0xF) == VRAM_WRITE ? context->last_write_val >> 8 : context->last_write_val; |
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478 partial = 1; |
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479 ran_source = 1; |
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480 break; |
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481 } |
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482 |
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483 if (ran_source) { |
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484 context->fifo_cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
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485 context->fifo_cur->address = context->address; |
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486 context->fifo_cur->value = read_val; |
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487 context->fifo_cur->cd = context->cd; |
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488 context->fifo_cur->partial = partial; |
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489 context->fifo_cur++; |
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490 context->regs[REG_DMASRC_L] += 1; |
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491 if (!context->regs[REG_DMASRC_L]) { |
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492 context->regs[REG_DMASRC_M] += 1; |
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diff
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493 } |
460
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494 context->address += context->regs[REG_AUTOINC]; |
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495 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
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496 context->regs[REG_DMALEN_H] = dma_len >> 8; |
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497 context->regs[REG_DMALEN_L] = dma_len; |
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498 if (!dma_len) { |
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499 //printf("DMA end at cycle %d\n", context->cycles); |
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500 context->flags &= ~FLAG_DMA_RUN; |
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501 context->cd &= 0xF; |
75 | 502 } |
54
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diff
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503 } |
20
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504 } |
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505 |
40 | 506 #define WINDOW_RIGHT 0x80 |
507 #define WINDOW_DOWN 0x80 | |
508 | |
25
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diff
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509 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
20
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510 { |
417
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511 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
414
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413
diff
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|
512 if (context->double_res) { |
413
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513 line *= 2; |
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514 if (context->framebuf != context->oddbuf) { |
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515 line++; |
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516 } |
417
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517 window_line_shift = 4; |
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518 v_offset_mask = 0xF; |
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|
519 vscroll_shift = 4; |
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520 } else { |
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|
521 window_line_shift = 3; |
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522 v_offset_mask = 0x7; |
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523 vscroll_shift = 3; |
414
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413
diff
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|
524 } |
40 | 525 if (!vsram_off) { |
526 uint16_t left_col, right_col; | |
527 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
41
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diff
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528 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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40
diff
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|
529 right_col = 42; |
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40
diff
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|
530 } else { |
40 | 531 left_col = 0; |
532 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
533 if (right_col) { | |
534 right_col += 2; | |
535 } | |
536 } | |
41
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40
diff
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|
537 uint16_t top_line, bottom_line; |
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40
diff
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|
538 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
417
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diff
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|
539 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
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diff
changeset
|
540 bottom_line = context->double_res ? 481 : 241; |
41
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40
diff
changeset
|
541 } else { |
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40
diff
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|
542 top_line = 0; |
417
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diff
changeset
|
543 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
41
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diff
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|
544 } |
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diff
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|
545 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
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40
diff
changeset
|
546 uint16_t address = context->regs[REG_WINDOW] << 10; |
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40
diff
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|
547 uint16_t line_offset, offset, mask; |
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40
diff
changeset
|
548 if (context->latched_mode & BIT_H40) { |
e591004487bc
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40
diff
changeset
|
549 address &= 0xF000; |
417
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415
diff
changeset
|
550 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
41
e591004487bc
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parents:
40
diff
changeset
|
551 mask = 0x7F; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
552 |
41
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
553 } else { |
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
554 address &= 0xF800; |
417
acdd6c5240fe
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415
diff
changeset
|
555 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
41
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parents:
40
diff
changeset
|
556 mask = 0x3F; |
e591004487bc
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40
diff
changeset
|
557 } |
417
acdd6c5240fe
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Mike Pavone <pavone@retrodev.com>
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415
diff
changeset
|
558 if (context->double_res) { |
acdd6c5240fe
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415
diff
changeset
|
559 mask <<= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
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415
diff
changeset
|
560 mask |= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
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parents:
415
diff
changeset
|
561 } |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
562 offset = address + line_offset + (((column - 2) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
563 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
54
3b79cbcf6846
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parents:
43
diff
changeset
|
564 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
565 offset = address + line_offset + (((column - 1) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
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parents:
40
diff
changeset
|
566 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
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415
diff
changeset
|
567 context->v_offset = (line) & v_offset_mask; |
41
e591004487bc
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parents:
40
diff
changeset
|
568 context->flags |= FLAG_WINDOW; |
e591004487bc
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parents:
40
diff
changeset
|
569 return; |
40 | 570 } |
571 context->flags &= ~FLAG_WINDOW; | |
572 } | |
20
f664eeb55cb4
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parents:
diff
changeset
|
573 uint16_t vscroll; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
574 switch(context->regs[REG_SCROLL] & 0x30) |
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
575 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
576 case 0: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
577 vscroll = 0xFF; |
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578 break; |
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579 case 0x10: |
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580 vscroll = 0x1FF; |
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parents:
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581 break; |
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582 case 0x20: |
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parents:
diff
changeset
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583 //TODO: Verify this behavior |
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parents:
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584 vscroll = 0; |
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585 break; |
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Mike Pavone <pavone@retrodev.com>
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586 case 0x30: |
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587 vscroll = 0x3FF; |
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588 break; |
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589 } |
414
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590 if (context->double_res) { |
413
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591 vscroll <<= 1; |
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Initial work on interlace
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592 vscroll |= 1; |
414
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Fix vscroll calculation in double resultion interlace mode
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593 } |
454
e9b6fe443bf2
Fix per-column scrolling bug
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594 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? (column-2)&63 : 0) + vsram_off] + line); |
414
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parents:
413
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595 context->v_offset = vscroll & v_offset_mask; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
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parents:
25
diff
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596 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
414
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413
diff
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597 vscroll >>= vscroll_shift; |
20
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598 uint16_t hscroll_mask; |
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599 uint16_t v_mul; |
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600 switch(context->regs[REG_SCROLL] & 0x3) |
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diff
changeset
|
601 { |
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diff
changeset
|
602 case 0: |
108
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parents:
87
diff
changeset
|
603 hscroll_mask = 0x1F; |
20
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diff
changeset
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604 v_mul = 64; |
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parents:
diff
changeset
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605 break; |
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diff
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606 case 0x1: |
39
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Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
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diff
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607 hscroll_mask = 0x3F; |
20
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608 v_mul = 128; |
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|
609 break; |
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|
610 case 0x2: |
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611 //TODO: Verify this behavior |
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612 hscroll_mask = 0; |
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613 v_mul = 0; |
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614 break; |
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615 case 0x3: |
108
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diff
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616 hscroll_mask = 0x7F; |
20
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617 v_mul = 256; |
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618 break; |
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619 } |
28 | 620 uint16_t hscroll, offset; |
621 for (int i = 0; i < 2; i++) { | |
39
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Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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38
diff
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622 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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parents:
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diff
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|
623 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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diff
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624 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
28 | 625 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
626 if (i) { | |
627 context->col_2 = col_val; | |
628 } else { | |
629 context->col_1 = col_val; | |
630 } | |
631 } | |
20
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632 } |
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|
633 |
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634 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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diff
changeset
|
635 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
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parents:
24
diff
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|
636 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
20
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|
637 } |
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diff
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|
638 |
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|
639 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
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diff
changeset
|
640 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
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24
diff
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|
641 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
20
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diff
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|
642 } |
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changeset
|
643 |
436
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644 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
20
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645 { |
413
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646 uint16_t address; |
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|
647 uint8_t shift, add; |
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|
648 if (context->double_res) { |
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649 address = ((col & 0x3FF) << 6); |
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|
650 shift = 1; |
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651 add = context->framebuf != context->oddbuf ? 1 : 0; |
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652 } else { |
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|
653 address = ((col & 0x7FF) << 5); |
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654 shift = 0; |
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|
655 add = 0; |
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|
656 } |
20
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diff
changeset
|
657 if (col & MAP_BIT_V_FLIP) { |
414
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Fix vscroll calculation in double resultion interlace mode
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parents:
413
diff
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|
658 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
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diff
changeset
|
659 } else { |
414
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Fix vscroll calculation in double resultion interlace mode
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413
diff
changeset
|
660 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
20
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parents:
diff
changeset
|
661 } |
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parents:
diff
changeset
|
662 uint16_t pal_priority = (col >> 9) & 0x70; |
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parents:
diff
changeset
|
663 int32_t dir; |
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parents:
diff
changeset
|
664 if (col & MAP_BIT_H_FLIP) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
changeset
|
665 offset += 7; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
changeset
|
666 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
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parents:
diff
changeset
|
667 dir = -1; |
f664eeb55cb4
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parents:
diff
changeset
|
668 } else { |
f664eeb55cb4
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parents:
diff
changeset
|
669 dir = 1; |
f664eeb55cb4
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parents:
diff
changeset
|
670 } |
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parents:
diff
changeset
|
671 for (uint32_t i=0; i < 4; i++, address++) |
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
672 { |
436
e341fd5aa996
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427
diff
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|
673 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
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|
674 offset += dir; |
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Implement the scroll ring buffer properly without memcpy
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427
diff
changeset
|
675 offset &= SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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427
diff
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|
676 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
changeset
|
677 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
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parents:
427
diff
changeset
|
678 offset &= SCROLL_BUFFER_MASK; |
20
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parents:
diff
changeset
|
679 } |
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parents:
diff
changeset
|
680 } |
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parents:
diff
changeset
|
681 |
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diff
changeset
|
682 void render_map_1(vdp_context * context) |
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parents:
diff
changeset
|
683 { |
436
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427
diff
changeset
|
684 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
20
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parents:
diff
changeset
|
685 } |
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parents:
diff
changeset
|
686 |
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parents:
diff
changeset
|
687 void render_map_2(vdp_context * context) |
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parents:
diff
changeset
|
688 { |
436
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427
diff
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|
689 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
20
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parents:
diff
changeset
|
690 } |
f664eeb55cb4
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parents:
diff
changeset
|
691 |
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parents:
diff
changeset
|
692 void render_map_3(vdp_context * context) |
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parents:
diff
changeset
|
693 { |
436
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427
diff
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|
694 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
20
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parents:
diff
changeset
|
695 } |
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parents:
diff
changeset
|
696 |
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parents:
diff
changeset
|
697 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
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parents:
diff
changeset
|
698 { |
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parents:
diff
changeset
|
699 if (line >= 240) { |
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parents:
diff
changeset
|
700 return; |
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parents:
diff
changeset
|
701 } |
436
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427
diff
changeset
|
702 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
703 uint16_t *dst; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
704 uint32_t *dst32; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
705 uint8_t *sprite_buf, *plane_a, *plane_b; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
706 int plane_a_off, plane_b_off; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 if (col) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 col-=2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
710 if (context->b32) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
711 dst32 = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
712 dst32 += line * 320 + col * 8; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
713 } else { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
714 dst = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
715 dst += line * 320 + col * 8; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
716 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 sprite_buf = context->linebuf + col * 8; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
718 uint8_t a_src, src; |
40 | 719 if (context->flags & FLAG_WINDOW) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
720 plane_a_off = context->buf_a_off; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
721 a_src = DBG_SRC_W; |
40 | 722 } else { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
723 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
724 a_src = DBG_SRC_A; |
40 | 725 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
726 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
30 | 727 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
728 |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
729 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
730 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
731 uint8_t pixel; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
732 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
733 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
734 uint32_t * colors = context->colors; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
735 src = 0; |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
736 uint8_t sprite_color = *sprite_buf & 0x3F; |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
737 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
232
54873acb982e
Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents:
230
diff
changeset
|
738 if (sprite_color == 0x3F) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
739 colors += CRAM_SIZE; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
740 src = DBG_SHADOW; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
741 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
742 colors += CRAM_SIZE*2; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
743 src = DBG_HILIGHT; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
744 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
745 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
746 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
747 src |= a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
748 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
749 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
750 src |= DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
751 } else if (*plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
752 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
753 src |= a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
754 } else if (*plane_b & 0xF){ |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
755 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
756 src |= DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
757 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
758 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
759 src |= DBG_SRC_BG; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
760 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
761 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
762 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
763 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
764 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
765 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
766 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
767 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
768 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
769 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
770 src = DBG_SRC_B; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
771 } else { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
772 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
773 colors += CRAM_SIZE; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
774 src = DBG_SHADOW; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
775 } |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
776 if (*sprite_buf & 0xF) { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
777 pixel = *sprite_buf; |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
778 if (*sprite_buf & 0xF == 0xE) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
779 colors = context->colors; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
780 src = DBG_SRC_S; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
781 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
782 src |= DBG_SRC_S; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
783 } |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
784 } else if (*plane_a & 0xF) { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
785 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
786 src |= a_src; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
787 } else if (*plane_b & 0xF){ |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
788 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
789 src |= DBG_SRC_B; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
790 } else { |
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
791 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
792 src |= DBG_SRC_BG; |
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
793 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
794 } |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
795 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
796 pixel &= 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
797 uint32_t outpixel; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
798 if (context->debug) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
799 outpixel = context->debugcolors[src]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
800 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
801 outpixel = colors[pixel]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
802 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
803 if (context->b32) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
804 *(dst32++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
805 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
806 *(dst++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
807 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
808 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
810 } else { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
811 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
812 uint8_t pixel; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
813 src = 0; |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
814 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
815 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
816 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
817 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
818 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
819 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
820 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
821 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
822 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
823 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
824 src = DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
825 } else if (*sprite_buf & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
826 pixel = *sprite_buf; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
827 src = DBG_SRC_S; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
828 } else if (*plane_a & 0xF) { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
829 pixel = *plane_a; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
830 src = a_src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
831 } else if (*plane_b & 0xF){ |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
832 pixel = *plane_b; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
833 src = DBG_SRC_B; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
834 } else { |
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
835 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
836 src = DBG_SRC_BG; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
837 } |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
838 uint32_t outpixel; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
839 if (context->debug) { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
840 outpixel = context->debugcolors[src]; |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
841 } else { |
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
842 outpixel = context->colors[pixel & 0x3F]; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
843 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
844 if (context->b32) { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
845 *(dst32++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
846 } else { |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
847 *(dst++) = outpixel; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
848 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
849 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
850 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 //dst = context->framebuf + line * 320; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 //sprite_buf = context->linebuf + col * 8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 //end = dst + 8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
859 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
860 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case startcyc:\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 read_map_scroll_a(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 external_slot(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 render_map_1(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 render_map_2(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 case (startcyc+4):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 read_map_scroll_b(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 case (startcyc+5):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 read_sprite_x(line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 render_map_3(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 case (startcyc+7):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 render_map_output(line, column, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 case startcyc:\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 read_map_scroll_a(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 case (startcyc+1):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 render_map_1(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 render_map_2(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 case (startcyc+4):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 read_map_scroll_b(column, line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 case (startcyc+5):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 read_sprite_x(line, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 render_map_3(context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 break;\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 case (startcyc+7):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 render_map_output(line, column, context);\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 uint16_t address; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 uint32_t mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 switch(linecyc) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 //sprite render to line buffer starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 case 0: |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
922 context->cur_slot = MAX_DRAWS-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 memset(context->linebuf, 0, LINEBUF_SIZE); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 case 1: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 case 2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 case 3: |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
927 if (line == 0xFF) { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
928 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
929 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
930 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
931 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 //sprite attribute table scan starts |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 case 4: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
935 render_sprite_cells( context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 context->sprite_index = 0x80; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 context->slot_counter = MAX_SPRITES_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 case 5: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 case 6: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 case 7: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 case 8: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 case 9: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 case 10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 case 11: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 case 12: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 case 13: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 case 14: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 case 15: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 case 16: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 case 17: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 case 18: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 case 19: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 case 20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 //!HSYNC asserted |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 case 21: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 case 22: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
959 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 case 23: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 external_slot(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 case 24: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case 25: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 case 26: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 case 27: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 case 28: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case 29: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 30: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 case 31: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 case 32: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 case 33: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 case 34: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
976 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 case 35: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 if (context->regs[REG_MODE_3] & 0x2) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 mask |= 0xF8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 if (context->regs[REG_MODE_3] & 0x1) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 mask |= 0x7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 line &= mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 address += line * 4; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
992 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 case 36: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 //!HSYNC high |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 case 37: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 case 38: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 case 39: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
999 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 case 40: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 read_map_scroll_a(0, line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 case 41: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1006 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 case 42: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 render_map_1(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 case 43: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 render_map_2(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 case 44: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 read_map_scroll_b(0, line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 case 45: |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1021 render_sprite_cells(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 scan_sprite_table(line, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 case 46: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 render_map_3(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 case 47: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 render_map_output(line, 0, context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 scan_sprite_table(line, context);//Just a guess |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 //reverse context slot counter so it counts the number of sprite slots |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 //filled rather than the number of available slots |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1033 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1034 context->cur_slot = MAX_SPRITES_LINE-1; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 context->sprite_draws = MAX_DRAWS; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
1036 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 COLUMN_RENDER_BLOCK(2, 48) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 COLUMN_RENDER_BLOCK(4, 56) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 COLUMN_RENDER_BLOCK(6, 64) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 COLUMN_RENDER_BLOCK(10, 80) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 COLUMN_RENDER_BLOCK(12, 88) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 COLUMN_RENDER_BLOCK(14, 96) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 COLUMN_RENDER_BLOCK(18, 112) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 COLUMN_RENDER_BLOCK(20, 120) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 COLUMN_RENDER_BLOCK(22, 128) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 COLUMN_RENDER_BLOCK(26, 144) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 COLUMN_RENDER_BLOCK(28, 152) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 COLUMN_RENDER_BLOCK(30, 160) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 COLUMN_RENDER_BLOCK(34, 176) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 COLUMN_RENDER_BLOCK(36, 184) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 COLUMN_RENDER_BLOCK(38, 192) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 case 208: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 case 209: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 external_slot(context); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 default: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 //leftovers from HSYNC clock change nonsense |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1065 } |
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diff
changeset
|
1066 } |
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diff
changeset
|
1067 |
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diff
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|
1068 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
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Mostly broken VDP core and savestate viewer
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diff
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|
1069 { |
37 | 1070 uint16_t address; |
1071 uint32_t mask; | |
20
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parents:
diff
changeset
|
1072 switch(linecyc) |
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1073 { |
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1074 //sprite render to line buffer starts |
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1075 case 0: |
37 | 1076 context->cur_slot = MAX_DRAWS_H32-1; |
1077 memset(context->linebuf, 0, LINEBUF_SIZE); | |
20
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 case 1: |
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Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1079 case 2: |
37 | 1080 case 3: |
329
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Implement first line/last line weirdness in VDP
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parents:
328
diff
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|
1081 if (line == 0xFF) { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
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parents:
328
diff
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|
1082 external_slot(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
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328
diff
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|
1083 } else { |
fd5f6577db9b
Implement first line/last line weirdness in VDP
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parents:
328
diff
changeset
|
1084 render_sprite_cells(context); |
fd5f6577db9b
Implement first line/last line weirdness in VDP
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328
diff
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|
1085 } |
20
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diff
changeset
|
1086 break; |
37 | 1087 //sprite attribute table scan starts |
20
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1088 case 4: |
37 | 1089 render_sprite_cells( context); |
1090 context->sprite_index = 0x80; | |
1091 context->slot_counter = MAX_SPRITES_LINE_H32; | |
1092 scan_sprite_table(line, context); | |
20
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1093 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 case 5: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 case 6: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 case 7: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 case 8: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 case 9: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1099 case 10: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1100 case 11: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 case 12: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1102 case 13: |
37 | 1103 render_sprite_cells(context); |
1104 scan_sprite_table(line, context); | |
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1105 case 14: |
37 | 1106 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1108 case 15: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1109 case 16: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1110 case 17: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1111 case 18: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1112 case 19: |
37 | 1113 //HSYNC start |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 case 20: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 case 21: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1116 case 22: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1117 case 23: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 case 24: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 case 25: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 case 26: |
37 | 1121 render_sprite_cells(context); |
1122 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1123 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 case 27: |
37 | 1125 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1126 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1127 case 28: |
37 | 1128 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
1129 mask = 0; | |
1130 if (context->regs[REG_MODE_3] & 0x2) { | |
1131 mask |= 0xF8; | |
1132 } | |
1133 if (context->regs[REG_MODE_3] & 0x1) { | |
1134 mask |= 0x7; | |
1135 } | |
1136 line &= mask; | |
1137 address += line * 4; | |
1138 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
1139 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
1140 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 case 29: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 case 30: |
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 case 31: |
37 | 1145 case 32: |
1146 render_sprite_cells(context); | |
1147 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 break; |
37 | 1149 //!HSYNC high |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 case 33: |
37 | 1151 read_map_scroll_a(0, line, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1153 case 34: |
37 | 1154 render_sprite_cells(context); |
1155 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1156 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1157 case 35: |
37 | 1158 render_map_1(context); |
1159 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1160 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 case 36: |
37 | 1162 render_map_2(context); |
1163 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1164 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1165 case 37: |
37 | 1166 read_map_scroll_b(0, line, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1167 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1168 case 38: |
37 | 1169 render_sprite_cells(context); |
1170 scan_sprite_table(line, context); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1171 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1172 case 39: |
37 | 1173 render_map_3(context); |
1174 scan_sprite_table(line, context);//Just a guess | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1175 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1176 case 40: |
37 | 1177 render_map_output(line, 0, context); |
1178 scan_sprite_table(line, context);//Just a guess | |
1179 //reverse context slot counter so it counts the number of sprite slots | |
1180 //filled rather than the number of available slots | |
1181 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
1182 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
1183 context->sprite_draws = MAX_DRAWS_H32; | |
1184 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1185 break; |
37 | 1186 COLUMN_RENDER_BLOCK(2, 41) |
1187 COLUMN_RENDER_BLOCK(4, 49) | |
1188 COLUMN_RENDER_BLOCK(6, 57) | |
1189 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
1190 COLUMN_RENDER_BLOCK(10, 73) | |
1191 COLUMN_RENDER_BLOCK(12, 81) | |
1192 COLUMN_RENDER_BLOCK(14, 89) | |
1193 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
1194 COLUMN_RENDER_BLOCK(18, 105) | |
1195 COLUMN_RENDER_BLOCK(20, 113) | |
1196 COLUMN_RENDER_BLOCK(22, 121) | |
1197 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
1198 COLUMN_RENDER_BLOCK(26, 137) | |
1199 COLUMN_RENDER_BLOCK(28, 145) | |
1200 COLUMN_RENDER_BLOCK(30, 153) | |
1201 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1202 case 169: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 case 170: |
37 | 1204 external_slot(context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1205 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1207 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1208 void latch_mode(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1209 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1210 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1211 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1212 |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1213 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1214 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1215 if (line > 0) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1216 line -= 1; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1217 int starti = -1; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1218 if (context->latched_mode & BIT_H40) { |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1219 if (slot >= 55 && slot < 210) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1220 uint32_t x = (slot-55)*2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1221 starti = line * 320 + x; |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1222 } else if (slot < 5) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1223 uint32_t x = (slot + 155)*2; |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1224 starti = (line-1)*320 + x; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1225 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1226 } else { |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1227 if (slot >= 48 && slot < 171) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1228 uint32_t x = (slot-48)*2; |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1229 starti = line * 320 + x; |
462
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1230 } else if (slot < 5) { |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1231 uint32_t x = (slot + 123)*2; |
5677c053edd6
Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents:
461
diff
changeset
|
1232 starti = (line-1)*320 + x; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1233 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1234 } |
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1235 if (starti >= 0) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1236 if (context->b32) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1237 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1238 uint32_t * start = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1239 start += starti; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1240 for (int i = 0; i < 2; i++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1241 *(start++) = color; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1242 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1243 } else { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1244 uint16_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1245 uint16_t * start = context->framebuf; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1246 start += starti; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1247 for (int i = 0; i < 2; i++) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1248 *(start++) = color; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1249 } |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1250 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1251 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1252 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1253 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1254 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1255 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1257 while(context->cycles < target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1258 { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1259 context->flags &= ~FLAG_UNUSED_SLOT; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 uint32_t line = context->cycles / MCLKS_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1261 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
334
4c91470e1a53
Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents:
333
diff
changeset
|
1262 if (!context->cycles) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1263 latch_mode(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1264 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1265 uint32_t linecyc = context->cycles % MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1266 if (linecyc == 0) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1267 if (line <= 1 || line >= active_lines) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1268 context->hint_counter = context->regs[REG_HINT]; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1269 } else if (context->hint_counter) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1270 context->hint_counter--; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1271 } else { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1272 context->flags2 |= FLAG2_HINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1273 context->hint_counter = context->regs[REG_HINT]; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1274 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1275 } else if(line == active_lines) { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1276 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1277 if (linecyc == intcyc) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1278 context->flags2 |= FLAG2_VINT_PENDING; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1279 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1280 } |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1281 uint32_t inccycles, slot; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1282 if (context->latched_mode & BIT_H40){ |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1283 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1284 slot = linecyc/MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1285 inccycles = MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1286 } else if(linecyc < MCLK_WEIRD_END) { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1287 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1288 { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1289 case 0: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1290 inccycles = 19; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1291 slot = 0; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1292 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1293 case 19: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1294 slot = 1; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1295 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1296 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1297 case 39: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1298 slot = 2; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1299 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1300 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1301 case 59: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1302 slot = 3; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1303 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1304 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1305 case 79: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1306 slot = 4; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1307 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1308 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1309 case 97: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1310 slot = 5; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1311 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1312 break; |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1313 case 117: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1314 slot = 6; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1315 inccycles = 20; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1316 break; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1317 case 137: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1318 slot = 7; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1319 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1320 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1321 case 157: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1322 slot = 8; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1323 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1324 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1325 case 175: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1326 slot = 9; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1327 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1328 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1329 case 195: |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1330 slot = 10; |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1331 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1332 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1333 case 215: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1334 slot = 11; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1335 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1336 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1337 case 235: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1338 slot = 12; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1339 inccycles = 18; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1340 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1341 case 253: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1342 slot = 13; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1343 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1344 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1345 case 273: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1346 slot = 14; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1347 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1348 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1349 case 293: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1350 slot = 15; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1351 inccycles = 20; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1352 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1353 case 313: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1354 slot = 16; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1355 inccycles = 19; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1356 break; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1357 default: |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1358 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1359 exit(1); |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1360 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1361 slot += HSYNC_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1362 } else { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1363 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1364 inccycles = MCLKS_SLOT_H40; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1365 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1366 } else { |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1367 inccycles = MCLKS_SLOT_H32; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1368 slot = linecyc/MCLKS_SLOT_H32; |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1369 } |
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1370 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1371 //first sort-of active line is treated as 255 internally |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1372 //it's used for gathering sprite info for line |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1373 line = (line - 1) & 0xFF; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1374 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1375 //Convert to slot number |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1376 if (context->latched_mode & BIT_H40){ |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1377 vdp_h40(line, slot, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1378 } else { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1379 vdp_h32(line, slot, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1380 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1381 } else { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1382 if (!is_refresh(context, slot)) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1383 external_slot(context); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1384 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1385 if (line < active_lines) { |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1386 check_render_bg(context, line, slot); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1387 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1388 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1389 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, slot)) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1390 run_dma_src(context, slot); |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1391 } |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1392 context->cycles += inccycles; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1393 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1394 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1395 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1396 uint32_t vdp_run_to_vblank(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1397 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1398 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1399 vdp_run_context(context, target_cycles); |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1400 return context->cycles; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1401 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1402 |
75 | 1403 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
1404 { | |
1405 for(;;) { | |
1406 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
1407 if (!dmalen) { | |
1408 dmalen = 0x10000; | |
1409 } | |
1410 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
1411 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
1412 //DMA copies take twice as long to complete since they require a read and a write | |
1413 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
1414 min_dma_complete *= 2; | |
1415 } | |
1416 min_dma_complete += context->cycles; | |
1417 if (target_cycles < min_dma_complete) { | |
1418 vdp_run_context(context, target_cycles); | |
1419 return; | |
1420 } else { | |
1421 vdp_run_context(context, min_dma_complete); | |
1422 if (!(context->flags & FLAG_DMA_RUN)) { | |
1423 return; | |
1424 } | |
1425 } | |
1426 } | |
1427 } | |
1428 | |
1429 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1430 { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1431 //printf("control port write: %X at %d\n", value, context->cycles); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1432 if (context->flags & FLAG_DMA_RUN) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1433 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1434 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1435 if (context->flags & FLAG_PENDING) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1436 context->address = (context->address & 0x3FFF) | (value << 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1437 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
75 | 1438 context->flags &= ~FLAG_PENDING; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1439 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1440 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1441 // |
75 | 1442 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
1443 //DMA copy or 68K -> VDP, transfer starts immediately | |
1444 context->flags |= FLAG_DMA_RUN; | |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1445 context->dma_cd = context->cd; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1446 //printf("DMA start at cycle %d\n", context->cycles); |
75 | 1447 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1448 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
75 | 1449 return 1; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1450 } else { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1451 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
75 | 1452 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1453 } else { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1454 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
75 | 1455 } |
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1456 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1457 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1458 if ((value & 0xC000) == 0x8000) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1459 //Register write |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1460 uint8_t reg = (value >> 8) & 0x1F; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1461 if (reg < VDP_REGS) { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1462 //printf("register %d set to %X\n", reg, value & 0xFF); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1463 context->regs[reg] = value; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1464 if (reg == REG_MODE_2) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1465 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1466 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1467 if (reg == REG_MODE_4) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1468 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1469 if (!context->double_res) { |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1470 context->framebuf = context->oddbuf; |
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1471 } |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1472 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1473 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1474 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1475 context->flags |= FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1476 context->address = (context->address &0xC000) | (value & 0x3FFF); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1477 context->cd = (context->cd &0x3C) | (value >> 14); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1478 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1479 } |
75 | 1480 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1481 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1482 |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1483 int vdp_data_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1484 { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1485 //printf("data port write: %X at %d\n", value, context->cycles); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1486 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1487 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1488 } |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1489 if (!(context->cd & 1)) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1490 //ignore writes when cd is configured for read |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1491 return 0; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1492 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1493 context->flags &= ~FLAG_PENDING; |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1494 /*if (context->fifo_cur == context->fifo_end) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1495 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1496 }*/ |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1497 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1498 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1499 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1500 while (context->fifo_cur == context->fifo_end) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1501 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1502 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1503 context->fifo_cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
138 | 1504 context->fifo_cur->address = context->address; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1505 context->fifo_cur->value = value; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1506 context->last_write_val = value; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1507 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1508 context->flags |= FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1509 } |
138 | 1510 context->fifo_cur->cd = context->cd; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1511 context->fifo_cur->partial = 0; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1512 context->fifo_cur++; |
138 | 1513 context->address += context->regs[REG_AUTOINC]; |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1514 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1515 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1516 |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1517 uint16_t vdp_control_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1518 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1519 context->flags &= ~FLAG_PENDING; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1520 uint16_t value = 0x3400; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1521 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1522 value |= 0x200; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1523 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1524 if (context->fifo_cur == context->fifo_end) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1525 value |= 0x100; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1526 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1527 if (context->flags2 & FLAG2_VINT_PENDING) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1528 value |= 0x80; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1529 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1530 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1531 value |= 0x10; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1532 } |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1533 uint32_t line= context->cycles / MCLKS_LINE; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1534 uint32_t linecyc = context->cycles % MCLKS_LINE; |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1535 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1536 value |= 0x8; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1537 } |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1538 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1539 value |= 0x4; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1540 } |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1541 if (context->flags & FLAG_DMA_RUN) { |
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1542 value |= 0x2; |
75 | 1543 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1544 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1545 value |= 0x1; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1546 } |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1547 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1548 //TODO: Sprite overflow, sprite collision, odd frame flag |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1549 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1550 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1551 |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1552 uint16_t vdp_data_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1553 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1554 context->flags &= ~FLAG_PENDING; |
138 | 1555 if (context->cd & 1) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1556 return 0; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1557 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1558 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1559 context->flags &= ~FLAG_UNUSED_SLOT; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1560 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1561 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1562 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1563 uint16_t value = 0; |
138 | 1564 switch (context->cd & 0xF) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1565 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1566 case VRAM_READ: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1567 value = context->vdpmem[context->address] << 8; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1568 context->flags &= ~FLAG_UNUSED_SLOT; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1569 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1570 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1571 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1572 value |= context->vdpmem[context->address ^ 1]; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1573 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1574 case CRAM_READ: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1575 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1576 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1577 case VSRAM_READ: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1578 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1579 value = context->vsram[context->address & 63]; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1580 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1581 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1582 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1583 context->address += context->regs[REG_AUTOINC]; |
3b79cbcf6846
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parents:
43
diff
changeset
|
1584 return value; |
3b79cbcf6846
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parents:
43
diff
changeset
|
1585 } |
3b79cbcf6846
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parents:
43
diff
changeset
|
1586 |
137 | 1587 uint16_t vdp_hv_counter_read(vdp_context * context) |
1588 { | |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1589 //TODO: deal with clock adjustemnts handled in vdp_run_context |
137 | 1590 uint32_t line= context->cycles / MCLKS_LINE; |
1591 if (!line) { | |
1592 line = 0xFF; | |
1593 } else { | |
1594 line--; | |
1595 if (line > 0xEA) { | |
1596 line = (line + 0xFA) & 0xFF; | |
1597 } | |
1598 } | |
1599 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
1600 if (context->latched_mode & BIT_H40) { | |
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1601 uint32_t slot; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1602 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1603 slot = linecyc/MCLKS_SLOT_H40; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1604 } else if(linecyc < MCLK_WEIRD_END) { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1605 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1606 { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1607 case 0: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1608 slot = 0; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1609 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1610 case 19: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1611 slot = 1; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1612 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1613 case 39: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1614 slot = 2; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1615 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1616 case 59: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1617 slot = 2; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1618 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1619 case 79: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1620 slot = 3; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1621 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1622 case 97: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1623 slot = 4; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1624 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1625 case 117: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1626 slot = 5; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1627 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1628 case 137: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1629 slot = 6; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1630 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1631 case 157: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1632 slot = 7; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1633 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1634 case 175: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1635 slot = 8; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1636 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1637 case 195: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1638 slot = 9; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1639 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1640 case 215: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1641 slot = 11; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1642 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1643 case 235: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1644 slot = 12; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1645 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1646 case 253: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1647 slot = 13; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1648 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1649 case 273: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1650 slot = 14; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1651 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1652 case 293: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1653 slot = 15; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1654 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1655 case 313: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1656 slot = 16; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1657 break; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1658 default: |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1659 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1660 exit(1); |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1661 } |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1662 slot += HSYNC_SLOT_H40; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1663 } else { |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1664 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1665 } |
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1666 linecyc = slot * 2; |
137 | 1667 if (linecyc >= 86) { |
1668 linecyc -= 86; | |
1669 } else { | |
1670 linecyc += 334; | |
1671 } | |
1672 if (linecyc > 0x16C) { | |
1673 linecyc += 92; | |
1674 } | |
1675 } else { | |
1676 linecyc /= 10; | |
1677 if (linecyc >= 74) { | |
1678 linecyc -= 74; | |
1679 } else { | |
1680 linecyc += 268; | |
1681 } | |
1682 if (linecyc > 0x127) { | |
1683 linecyc += 170; | |
1684 } | |
1685 } | |
1686 linecyc &= 0xFF; | |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1687 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1688 line <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1689 if (line & 0x100) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1690 line |= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1691 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1692 } |
137 | 1693 return (line << 8) | linecyc; |
1694 } | |
1695 | |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1696 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1697 { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1698 context->cycles -= deduction; |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1699 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1700 if (start->cycle >= deduction) { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1701 start->cycle -= deduction; |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1702 } else { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1703 start->cycle = 0; |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1704 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1705 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1706 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1707 |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1708 uint32_t vdp_next_hint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1709 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1710 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1711 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1712 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1713 if (context->flags2 & FLAG2_HINT_PENDING) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1714 return context->cycles; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1715 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1716 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1717 uint32_t line = context->cycles / MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1718 if (line >= active_lines) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1719 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1720 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1721 uint32_t linecyc = context->cycles % MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1722 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1723 if (!line) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1724 hcycle += MCLKS_LINE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1725 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1726 return hcycle; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1727 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1728 |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1729 uint32_t vdp_next_vint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1730 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1731 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1732 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1733 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1734 if (context->flags2 & FLAG2_VINT_PENDING) { |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1735 return context->cycles; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1736 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1737 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1738 uint32_t vcycle = MCLKS_LINE * active_lines; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1739 if (context->latched_mode & BIT_H40) { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1740 vcycle += VINT_CYCLE_H40; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1741 } else { |
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1742 vcycle += VINT_CYCLE_H32; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
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1743 } |
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1744 if (vcycle < context->cycles) { |
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1745 return 0xFFFFFFFF; |
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1746 } |
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1747 return vcycle; |
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1748 } |
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1749 |
333 | 1750 uint32_t vdp_next_vint_z80(vdp_context * context) |
1751 { | |
1752 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
1753 uint32_t vcycle = MCLKS_LINE * active_lines; | |
1754 if (context->latched_mode & BIT_H40) { | |
1755 vcycle += VINT_CYCLE_H40; | |
1756 } else { | |
1757 vcycle += VINT_CYCLE_H32; | |
1758 } | |
1759 return vcycle; | |
1760 } | |
1761 | |
317
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1762 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
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1763 { |
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1764 if (int_num == 6) { |
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1765 context->flags2 &= ~FLAG2_VINT_PENDING; |
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1766 } else if(int_num ==4) { |
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1767 context->flags2 &= ~FLAG2_HINT_PENDING; |
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1768 } |
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1769 } |
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1770 |