repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 715:1c2020d3e275

Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly

author	Michael Pavone <pavone@retrodev.com>
date	Sun, 17 May 2015 19:14:41 -0700
parents	382a2b5b70c0
children	b707a8ddc202

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	2 Copyright 2013 Michael Pavone
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	5 */
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	9 #include "mem.h"
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	10 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	11 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	12 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	13 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	14
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MODE_UNUSED (MODE_IMMED-1)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	17 //#define DO_DEBUG_PRINT
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	18
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	19 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	20 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	21 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	22 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	23 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	24
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	25 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst);
715 1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly Michael Pavone <pavone@retrodev.com> parents: 712 diff changeset	26 void z80_handle_deferred(z80_context * context);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	27
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	28 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	31 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	35 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	37
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	38 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	39 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	40 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	47 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	49 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	50 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	51 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	52 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	53 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	54 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	55 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	56 }
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	57 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	58 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	59 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	60 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	61 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	62 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	63 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	64 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	65 ror_ir(code, 8, ea->base, SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	66 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	67 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	68 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	69 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	70 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	71 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	72 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	74 ea->mode = MODE_REG_DISPLACE8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	75 ea->base = opts->gen.context_reg;
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	76 ea->disp = offsetof(z80_context, regs) + inst->reg;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	80
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	81 void z80_save_reg(z80inst * inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	83 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	85 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	86 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	87 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	88 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	89 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	90 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	91 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	92 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	93 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	94 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	95 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	96 //we can't mix an *H reg with a register that requires the REX prefix
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	97 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	98 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	99 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	100 //temp regs require REX prefix too
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	101 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	102 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	105
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	106 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	108 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 uint8_t size, reg, areg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	110 ea->mode = MODE_REG_DIRECT;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	111 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 case Z80_REG:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	116 if (inst->reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	117 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	118 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	119 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	120 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	121 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	122 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	123 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	124 } else if(opts->regs[inst->ea_reg] >= 0) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	126 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	127 uint8_t other_reg = opts->regs[inst->reg];
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	128 #ifdef X86_64
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	129 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	130 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	131 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	132 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	133 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	134 #endif
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	135 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	136 } else {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	137 ea->mode = MODE_REG_DISPLACE8;
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	138 ea->base = opts->gen.context_reg;
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	139 ea->disp = offsetof(z80_context, regs) + inst->ea_reg;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	140 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 case Z80_REG_INDIRECT:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	143 mov_rr(code, opts->regs[inst->ea_reg], areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	145 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	147 //push_r(code, opts->gen.scratch1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	148 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 if (size == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	151 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	153 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	156 //pop_r(code, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	157 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	160 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 case Z80_IMMED_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	167 mov_ir(code, inst->immed, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 if (read) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	170 /*if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	171 push_r(code, opts->gen.scratch1);
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	172 }*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	174 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	176 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	179 //pop_r(code, opts->gen.scratch2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	180 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	183 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	185 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	186 case Z80_IY_DISPLACE:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	187 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY];
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	188 mov_rr(code, reg, areg, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	189 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	193 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	194 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	197 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	199 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	202 //pop_r(code, opts->gen.scratch2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	203 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	206 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	209 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 default:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	212 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	216
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	217 void z80_save_ea(code_info code, z80inst inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	219 if ((inst->addr_mode & 0x1F) == Z80_REG) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	220 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	221 if (inst->reg == Z80_IYL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	222 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	223 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	224 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	225 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	226 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	227 }
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	228 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	229 uint8_t other_reg = opts->regs[inst->reg];
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	230 #ifdef X86_64
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	231 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	232 //we can't mix an *H reg with a register that requires the REX prefix
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	233 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	234 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	235 #endif
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	236 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	239
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	240 void z80_save_result(z80_options opts, z80inst inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	242 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	243 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	244 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	245 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	246 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	247 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	248 if (z80_size(inst) == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	249 call(&opts->gen.code, opts->write_8);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	250 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	251 call(&opts->gen.code, opts->write_16_lowfirst);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	252 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	255
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	260
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	265
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 uint8_t zf_off(uint8_t flag)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 return offsetof(z80_context, flags) + flag;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	270
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	271 uint8_t zaf_off(uint8_t flag)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	272 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	273 return offsetof(z80_context, alt_flags) + flag;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	274 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	275
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	276 uint8_t zar_off(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	277 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	278 return offsetof(z80_context, alt_regs) + reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	279 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	280
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	281 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	282 {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	283 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	284 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	285 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	286 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	287 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	288 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	289 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	290 puts("--Alternate Regs--");
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	291 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	292 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	293 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	294 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	295 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	296 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	297 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	298 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	299
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	300 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	302 uint32_t num_cycles;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	303 host_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	304 uint8_t size;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	305 z80_options *opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	306 uint8_t * start = opts->gen.code.cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	307 code_info *code = &opts->gen.code;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	308 if (!interp) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	309 check_cycles_int(&opts->gen, address);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	310 if (context->breakpoint_flags[address / sizeof(uint8_t)] & (1 << (address % sizeof(uint8_t)))) {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	311 zbreakpoint_patch(context, address, start);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	312 }
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 682 diff changeset	313 //log_address(&opts->gen, address, "Z80: %X @ %d\n");
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	314 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	318 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	319 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	320 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	321 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	322 case Z80_REG_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	323 num_cycles = size == SZ_B ? 4 : 6;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	324 if (inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	325 num_cycles += 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	326 }
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	327 if (inst->reg == Z80_I \|\| inst->ea_reg == Z80_I) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	328 num_cycles += 5;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	329 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	330 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	331 case Z80_IMMED:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	332 num_cycles = size == SZ_B ? 7 : 10;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	333 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	334 case Z80_IMMED_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	335 num_cycles = 10;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	336 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	337 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	338 case Z80_IY_DISPLACE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	339 num_cycles = 16;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	340 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	341 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	342 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) \|\| inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	343 num_cycles += 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	344 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	345 cycles(&opts->gen, num_cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 if (inst->addr_mode & Z80_DIR) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	347 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	348 translate_z80_reg(inst, &src_op, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	349 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	350 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	351 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	353 if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	354 if(dst_op.mode == MODE_REG_DISPLACE8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	355 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	356 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	357 mov_rr(code, src_op.base, dst_op.base, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	358 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	359 } else if(src_op.mode == MODE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	360 mov_ir(code, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	362 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	364 if (inst->ea_reg == Z80_I && inst->addr_mode == Z80_REG) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	365 //ld a, i sets some flags
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	366 //TODO: Implement half-carry flag
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	367 cmp_ir(code, 0, dst_op.base, SZ_B);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	368 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	369 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	370 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);;
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	371 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	372 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	373 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	374 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	375 z80_save_ea(code, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	376 if (inst->addr_mode & Z80_DIR) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	377 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	379 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 case Z80_PUSH:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	381 cycles(&opts->gen, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 9 : 5);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	382 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	383 if (inst->reg == Z80_AF) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	384 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	385 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	386 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	387 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	388 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	389 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	390 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	391 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	392 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	393 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	394 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	395 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	396 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	397 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	398 translate_z80_reg(inst, &src_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	399 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	400 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	401 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	402 call(code, opts->write_16_highfirst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	403 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	404 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 case Z80_POP:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	407 cycles(&opts->gen, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 8 : 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	408 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	409 call(code, opts->read_16);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	410 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	411 if (inst->reg == Z80_AF) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	412
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	413 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	414 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	415 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	416 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	417 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	418 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	419 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	420 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	421 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	422 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	423 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	424 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	425 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	426 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	427 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	428 translate_z80_reg(inst, &src_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	429 mov_rr(code, opts->gen.scratch1, src_op.base, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	430 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	431 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	432 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	433 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	434 case Z80_EX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	435 if (inst->addr_mode == Z80_REG \|\| inst->reg == Z80_HL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	436 num_cycles = 4;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	437 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	438 num_cycles = 8;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	439 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	440 cycles(&opts->gen, num_cycles);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	441 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	442 if(inst->reg == Z80_AF) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	443 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	444 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	445 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	446
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	447 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	448 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	449 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	450 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	451 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	452 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	453 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	454 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	455 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	456 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	457 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	458 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	459 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	460 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	461 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	462 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	463 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	464 cycles(&opts->gen, 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	465 uint8_t high_reg = z80_high_reg(inst->reg);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	466 uint8_t use_reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	467 //even though some of the upper halves can be used directly
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	468 //the limitations on mixing *H regs with the REX prefix
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	469 //prevent us from taking advantage of it
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	470 use_reg = opts->regs[inst->reg];
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	471 ror_ir(code, 8, use_reg, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	472 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	473 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	474 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	475 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	476 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	477 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	478 call(code, opts->write_8);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	479 //restore reg to normal rotation
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	480 ror_ir(code, 8, use_reg, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	481 cycles(&opts->gen, 2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	482 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	483 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 case Z80_EXX:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	485 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	486 mov_rr(code, opts->regs[Z80_BC], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	487 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	488 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	489 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	490 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_C), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	491 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zar_off(Z80_L), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	492 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	493 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	494 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_E), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	495 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	496 case Z80_LDI: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	497 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	498 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	499 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	500 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	501 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	502 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	503 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	504 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	505 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	506 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	507 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	508 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	509 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	510 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	511 case Z80_LDIR: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	512 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	513 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	514 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	515 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	516 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	517 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	518 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	519
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	520 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	521 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	522 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	523 cycles(&opts->gen, 7);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	524 //TODO: Figure out what the flag state should be here
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	525 //TODO: Figure out whether an interrupt can interrupt this
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	526 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	527 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	528 cycles(&opts->gen, 2);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	529 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	530 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	531 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	532 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	533 }
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	534 case Z80_LDD: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	535 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	536 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	537 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	538 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	539 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	540 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	541 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	542 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	543 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	544 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	545 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	546 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	547 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	548 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	549 case Z80_LDDR: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	550 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	551 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	552 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	553 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	554 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	555 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	556 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	557
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	558 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	559 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	560 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	561 cycles(&opts->gen, 7);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	562 //TODO: Figure out what the flag state should be here
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	563 //TODO: Figure out whether an interrupt can interrupt this
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	564 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	565 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	566 cycles(&opts->gen, 2);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	567 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	568 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	569 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	570 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	571 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	572 /*case Z80_CPI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	573 case Z80_CPIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	574 case Z80_CPD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	575 case Z80_CPDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	576 break;*/
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	577 case Z80_ADD:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	578 num_cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	579 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	580 num_cycles += 12;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	581 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	582 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	583 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	584 num_cycles += 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	585 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	586 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	587 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	588 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	589 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	590 add_rr(code, src_op.base, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	591 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	592 add_ir(code, src_op.disp, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	593 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	594 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	595 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	596 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	597 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	598 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	599 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	600 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	601 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	602 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	603 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	604 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	605 case Z80_ADC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	606 num_cycles = 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	607 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	608 num_cycles += 12;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	609 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	610 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	611 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	612 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	613 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	614 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	615 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	616 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	617 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	618 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	619 adc_rr(code, src_op.base, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	620 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	621 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	622 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	623 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	624 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	625 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	626 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	627 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	628 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	629 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	630 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	631 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	632 case Z80_SUB:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	633 num_cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	634 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	635 num_cycles += 12;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	636 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	637 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	638 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	639 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	640 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	641 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	642 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	643 sub_rr(code, src_op.base, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	644 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	645 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	646 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	647 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	648 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	649 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	650 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	651 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	652 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	653 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	654 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	655 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	656 case Z80_SBC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	657 num_cycles = 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	658 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	659 num_cycles += 12;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	660 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	661 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	662 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	663 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	664 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	665 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	666 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	667 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	668 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	669 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	670 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	671 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	672 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	673 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	674 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	675 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	676 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	677 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	678 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	679 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	680 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	681 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	682 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	683 case Z80_AND:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	684 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	685 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	686 num_cycles += 12;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	687 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	688 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	689 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	690 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	691 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	692 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	693 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	694 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	695 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	696 and_rr(code, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	697 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	698 and_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	699 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	700 //TODO: Cleanup flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	701 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	702 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	703 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	704 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	705 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	706 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	707 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	708 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	709 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	710 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	711 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	712 case Z80_OR:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	713 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	714 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	715 num_cycles += 12;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	716 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	717 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	718 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	719 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	720 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	721 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	722 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	723 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	724 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	725 or_rr(code, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	726 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	727 or_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	728 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	729 //TODO: Cleanup flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	730 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	731 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	732 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	733 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	734 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	735 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	736 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	737 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	738 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	739 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	740 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	741 case Z80_XOR:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	742 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	743 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	744 num_cycles += 12;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	745 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	746 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	747 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	748 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	749 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	750 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	751 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	752 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	753 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	754 xor_rr(code, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	755 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	756 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	757 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	758 //TODO: Cleanup flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	759 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	760 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	761 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	762 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	763 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	764 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	765 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	766 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	767 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	768 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	769 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	770 case Z80_CP:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	771 num_cycles = 4;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	772 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	773 num_cycles += 12;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	774 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	775 num_cycles += 3;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	776 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	777 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	778 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	779 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	780 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	781 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	782 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	783 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	784 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	785 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	786 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	787 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	788 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	789 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	790 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	791 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	792 z80_save_ea(code, inst, opts);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	793 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	794 case Z80_INC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	795 num_cycles = 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	796 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	797 num_cycles += 6;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	798 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	799 num_cycles += 2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	800 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	801 num_cycles += 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	802 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	803 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	804 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	805 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	806 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	807 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	808 add_ir(code, 1, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	809 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	810 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	811 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	812 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	813 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	814 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	815 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	816 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	817 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	818 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	819 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	820 case Z80_DEC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	821 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	822 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	823 num_cycles += 6;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	824 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	825 num_cycles += 2;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	826 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	827 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	828 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	829 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	830 translate_z80_reg(inst, &dst_op, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	831 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	832 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	833 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	834 sub_ir(code, 1, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	835 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	836 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	837 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	838 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	839 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	840 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	841 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	842 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	843 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	844 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	845 break;
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	846 //case Z80_DAA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	847 case Z80_CPL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	848 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	849 not_r(code, opts->regs[Z80_A], SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	850 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	851 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	852 break;
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	853 case Z80_NEG:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	854 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	855 neg_r(code, opts->regs[Z80_A], SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	856 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	857 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	858 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	859 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	860 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	861 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	862 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	863 case Z80_CCF:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	864 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	865 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	866 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	867 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	868 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	869 case Z80_SCF:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	870 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	871 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	872 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	873 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	874 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	875 case Z80_NOP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	876 if (inst->immed == 42) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	877 call(code, opts->gen.save_context);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	878 call_args(code, (code_ptr)z80_print_regs_exit, 1, opts->gen.context_reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	879 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	880 cycles(&opts->gen, 4 * inst->immed);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	881 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	882 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	883 case Z80_HALT: {
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	884 code_ptr loop_top = code->cur;
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	885 //this isn't terribly efficient, but it's good enough for now
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	886 cycles(&opts->gen, 4);
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	887 check_cycles_int(&opts->gen, address);
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	888 jmp(code, loop_top);
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	889 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	890 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	891 case Z80_DI:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	892 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	893 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	894 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	895 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	896 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	897 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	898 case Z80_EI:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	899 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	900 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	901 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	902 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335 14a937097c2b Some Z80 interrupt fixes Mike Pavone <pavone@retrodev.com> parents: 315 diff changeset	903 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	904 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	905 call(code, opts->do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	906 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	907 case Z80_IM:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	908 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	909 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	910 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	911 case Z80_RLC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	912 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	913 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	914 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	915 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	916 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	917 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	918 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	919 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	920 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	921 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	922 rol_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	923 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	924 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	925 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	926 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	927 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	928 //TODO: Implement half-carry flag
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	929 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	930 //rlca does not set these flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	931 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	932 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	933 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	934 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	935 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	936 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	937 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	938 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	939 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	940 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	941 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	942 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	943 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	944 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	945 case Z80_RL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	946 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	947 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	948 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	949 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	950 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	951 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	952 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	953 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	954 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	955 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	956 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	957 rcl_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	958 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	959 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	960 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	961 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	962 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	963 //TODO: Implement half-carry flag
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	964 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	965 //rla does not set these flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	966 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	967 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	968 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	969 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	970 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	971 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	972 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	973 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	974 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	975 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	976 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	977 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	978 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	979 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	980 case Z80_RRC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	981 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	982 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	983 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	984 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	985 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	986 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	987 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	988 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	989 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	990 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	991 ror_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	992 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	993 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	994 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	995 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	996 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	997 //TODO: Implement half-carry flag
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	998 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	999 //rrca does not set these flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1000 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1001 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1002 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1003 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1004 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1005 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1006 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1007 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1008 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1009 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1010 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1011 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1012 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1013 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1014 case Z80_RR:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1015 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1016 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1017 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1018 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1019 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1020 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1021 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1022 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1023 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1024 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1025 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1026 rcr_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1027 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1028 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1029 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1030 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1031 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1032 //TODO: Implement half-carry flag
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1033 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1034 //rra does not set these flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1035 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1036 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1037 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1038 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1039 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1040 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1041 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1042 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1043 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1044 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1045 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1046 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1047 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1048 break;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1049 case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1050 case Z80_SLL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1051 num_cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1052 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1053 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1054 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1055 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1056 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1057 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1058 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1059 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1060 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1061 shl_ir(code, 1, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1062 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1063 if (inst->op == Z80_SLL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1064 or_ir(code, 1, dst_op.base, SZ_B);
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1065 }
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1066 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1067 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1068 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1069 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1070 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1071 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1072 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1073 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1074 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1075 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1076 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1077 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1078 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1079 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1080 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1081 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1082 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1083 break;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1084 case Z80_SRA:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1085 num_cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1086 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1087 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1088 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1089 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1090 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1091 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1092 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1093 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1094 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1095 sar_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1096 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1097 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1098 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1099 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1100 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1101 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1102 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1103 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1104 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1105 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1106 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1107 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1108 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1109 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1110 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1111 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1112 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1113 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1114 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1115 case Z80_SRL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1116 num_cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1117 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1118 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1119 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1120 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1121 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1122 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1123 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1124 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1125 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1126 shr_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1127 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1128 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1129 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1130 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1131 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1132 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1133 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1134 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1135 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1136 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1137 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1138 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1139 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1140 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1141 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1142 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1143 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1144 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1145 break;
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1146 case Z80_RLD:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1147 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1148 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1149 call(code, opts->read_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1150 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1151 //After: (HL) = 0x24, A = 0x31
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1152 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1153 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1154 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1155 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1156 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1157 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1158 //opts->gen.scratch1 = 0x0124
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1159 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1160 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1161 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1162 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1163 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1164 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1165 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1166 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1167 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1168
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1169 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1170 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1171 call(code, opts->write_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1172 break;
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1173 case Z80_RRD:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1174 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1175 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1176 call(code, opts->read_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1177 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1178 //After: (HL) = 0x41, A = 0x32
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1179 movzx_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1180 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1181 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1182 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1183 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1184 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1185 //opts->gen.scratch2 = 0x0040
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1186 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1187 //opts->gen.scratch1 = 0x2041
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1188 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1189 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1190 shr_ir(code, 4, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1191 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1192 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1193 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1194 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1195 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1196 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1197 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1198
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1199 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1200 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1201 call(code, opts->write_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1202 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1203 case Z80_BIT: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1204 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1205 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1206 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1207 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1208 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1209 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1210 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1211 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1212 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1213 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1214 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1215 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1216 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1217 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1218 cycles(&opts->gen, 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1219 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1220 bt_ir(code, bit, src_op.base, size);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1221 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1222 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1223 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1224 if (inst->immed == 7) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1225 cmp_ir(code, 0, src_op.base, size);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1226 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1227 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1228 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1229 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1230 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1231 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1232 case Z80_SET: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1233 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1234 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1235 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1236 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1237 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1238 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1239 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1240 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1241 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1242 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1243 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1244 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1245 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1246 translate_z80_reg(inst, &dst_op, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1247 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1248 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1249 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1250 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1251 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1252 bts_ir(code, bit, src_op.base, size);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1253 if (inst->reg != Z80_USE_IMMED) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1254 if (size == SZ_W) {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1255 #ifdef X86_64
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1256 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1257 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1258 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1259 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1260 } else {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1261 #endif
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1262 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1263 #ifdef X86_64
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1264 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1265 #endif
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1266 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1267 mov_rr(code, src_op.base, dst_op.base, SZ_B);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1268 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1269 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1270 if ((inst->addr_mode & 0x1F) != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1271 z80_save_result(opts, inst);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1272 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1273 z80_save_reg(inst, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1274 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1275 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1276 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1277 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1278 case Z80_RES: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1279 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1280 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1281 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1282 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1283 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1284 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1285 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1286 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1287 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1288 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1289 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1290 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1291 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1292 translate_z80_reg(inst, &dst_op, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1293 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1294 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1295 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1296 cycles(&opts->gen, 1);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1297 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1298 btr_ir(code, bit, src_op.base, size);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1299 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1300 if (size == SZ_W) {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1301 #ifdef X86_64
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1302 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1303 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1304 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1305 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1306 } else {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1307 #endif
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1308 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1309 #ifdef X86_64
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1310 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1311 #endif
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1312 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1313 mov_rr(code, src_op.base, dst_op.base, SZ_B);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1314 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1315 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1316 if (inst->addr_mode != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1317 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1318 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1319 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1320 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1321 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1322 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1323 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1324 case Z80_JP: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1325 num_cycles = 4;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	1326 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1327 num_cycles += 6;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1328 } else if(inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1329 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1330 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1331 cycles(&opts->gen, num_cycles);
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1332 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1333 code_ptr call_dst = z80_get_native_address(context, inst->immed);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1334 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1335 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1336 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1337 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1338 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1339 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1340 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1341 if (inst->addr_mode == Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1342 mov_rr(code, opts->regs[inst->ea_reg], opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1343 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1344 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1345 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1346 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1347 jmp_r(code, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1348 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1349 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1350 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1351 case Z80_JPCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1352 cycles(&opts->gen, 7);//T States: 4,3
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1353 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1354 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1355 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1356 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1357 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1358 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1359 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1360 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1361 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1362 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1363 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1364 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1365 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1366 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1367 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1368 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1369 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1370 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1371 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1372 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1373 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1374 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1375 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1376 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1377 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1378 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1379 cycles(&opts->gen, 5);//T States: 5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1380 uint16_t dest_addr = inst->immed;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1381 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1382 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1383 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1384 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1385 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1386 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1387 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1388 *no_jump_off = code->cur - (no_jump_off+1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1389 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1390 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1391 case Z80_JR: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1392 cycles(&opts->gen, 12);//T States: 4,3,5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1393 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1394 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1395 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1396 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1397 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1398 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1399 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1400 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1401 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1402 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1403 case Z80_JRCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1404 cycles(&opts->gen, 7);//T States: 4,3
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1405 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1406 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1407 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1408 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1409 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1410 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1411 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1412 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1413 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1414 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1415 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1416 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1417 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1418 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1419 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1420 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1421 cycles(&opts->gen, 5);//T States: 5
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1422 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1423 code_ptr call_dst = z80_get_native_address(context, dest_addr);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1424 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1425 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1426 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1427 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1428 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1429 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1430 *no_jump_off = code->cur - (no_jump_off+1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1431 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1432 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1433 case Z80_DJNZ: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1434 cycles(&opts->gen, 8);//T States: 5,3
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1435 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1436 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1437 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1438 cycles(&opts->gen, 5);//T States: 5
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1439 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1440 code_ptr call_dst = z80_get_native_address(context, dest_addr);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1441 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1442 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1443 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1444 call_dst = code->cur + 256;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1445 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1446 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1447 *no_jump_off = code->cur - (no_jump_off+1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1448 break;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1449 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1450 case Z80_CALL: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1451 cycles(&opts->gen, 11);//T States: 4,3,4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1452 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1453 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1454 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1455 call(code, opts->write_16_highfirst);//T States: 3, 3
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1456 code_ptr call_dst = z80_get_native_address(context, inst->immed);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1457 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1458 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1459 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1460 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1461 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1462 jmp(code, call_dst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1463 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1464 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1465 case Z80_CALLCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1466 cycles(&opts->gen, 10);//T States: 4,3,3 (false case)
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1467 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1468 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1469 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1470 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1471 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1472 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1473 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1474 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1475 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1476 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1477 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1478 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1479 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1480 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1481 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1482 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1483 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1484 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1485 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1486 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1487 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1488 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1489 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1490 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1491 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1492 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1493 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1494 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1495 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1496 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1497 call(code, opts->write_16_highfirst);//T States: 3, 3
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1498 code_ptr call_dst = z80_get_native_address(context, inst->immed);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1499 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1500 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1501 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1502 call_dst = code->cur + 256;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1503 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1504 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1505 *no_call_off = code->cur - (no_call_off+1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1506 break;
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	1507 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1508 case Z80_RET:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1509 cycles(&opts->gen, 4);//T States: 4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1510 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1511 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1512 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1513 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1514 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1515 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1516 case Z80_RETCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1517 cycles(&opts->gen, 5);//T States: 5
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1518 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1519 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1520 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1521 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1522 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1523 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1524 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1525 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1526 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1527 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1528 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1529 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1530 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1531 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1532 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1533 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1534 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1535 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1536 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1537 cond = CC_NZ;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1538 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1539 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1540 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1541 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1542 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1543 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1544 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1545 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1546 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1547 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1548 jmp_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1549 *no_call_off = code->cur - (no_call_off+1);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1550 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1551 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1552 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1553 //For some systems, this may need a callback for signalling interrupt routine completion
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1554 cycles(&opts->gen, 8);//T States: 4, 4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1555 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1556 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1557 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1558 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1559 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1560 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1561 case Z80_RETN:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1562 cycles(&opts->gen, 8);//T States: 4, 4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1563 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1564 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1565 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1566 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1567 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1568 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1569 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1570 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1571 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1572 //RST is basically CALL to an address in page 0
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1573 cycles(&opts->gen, 5);//T States: 5
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1574 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1575 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1576 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1577 call(code, opts->write_16_highfirst);//T States: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1578 code_ptr call_dst = z80_get_native_address(context, inst->immed);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1579 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1580 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1581 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1582 call_dst = code->cur + 256;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1583 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1584 jmp(code, call_dst);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1585 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1586 }
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1587 case Z80_IN:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1588 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1589 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1590 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1591 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1592 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1593 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1594 call(code, opts->read_io);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1595 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1596 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1597 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1598 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1599 /*case Z80_INI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1600 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1601 case Z80_IND:
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1602 case Z80_INDR:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1603 case Z80_OUT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1604 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1605 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1606 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1607 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1608 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1609 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1610 translate_z80_reg(inst, &src_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1611 mov_rr(code, dst_op.base, opts->gen.scratch1, SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1612 call(code, opts->write_io);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1613 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1614 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1615 /*case Z80_OUTI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1616 case Z80_OTIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1617 case Z80_OUTD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1618 case Z80_OTDR:*/
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1619 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1620 char disbuf[80];
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1621 z80_disasm(inst, disbuf, address);
424 7e8e179116af Add support for loading GST format savestates Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	1622 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1623 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1624 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1625 fclose(f);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1626 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1627 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1628 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1629 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1630
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1631 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context)
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1632 {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1633 if (!context->interp_code[opcode]) {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1634 if (opcode == 0xCB \|\| (opcode >= 0xDD && opcode & 0xF == 0xD)) {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1635 fprintf(stderr, "Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1636 exit(1);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1637 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1638 uint8_t codebuf[8];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1639 memset(codebuf, 0, sizeof(codebuf));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1640 codebuf[0] = opcode;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1641 z80inst inst;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1642 uint8_t * after = z80_decode(codebuf, &inst);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1643 if (after - codebuf > 1) {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1644 fprintf(stderr, "Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1645 exit(1);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1646 }
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1647
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1648 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1649 code_info *code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1650 check_alloc_code(code, ZMAX_NATIVE_SIZE);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1651 context->interp_code[opcode] = code->cur;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1652 translate_z80inst(&inst, context, 0, 1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1653 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1654 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1655 call(code, opts->native_addr);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1656 jmp_r(code, opts->gen.scratch1);
715 1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly Michael Pavone <pavone@retrodev.com> parents: 712 diff changeset	1657 z80_handle_deferred(context);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1658 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1659 return context->interp_code[opcode];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1660 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1661
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1662 code_info z80_make_interp_stub(z80_context * context, uint16_t address)
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1663 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1664 z80_options *opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1665 code_info * code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1666 check_alloc_code(code, 32);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1667 code_info stub = {code->cur, NULL};
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1668 //TODO: make this play well with the breakpoint code
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1669 mov_ir(code, address, opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1670 call(code, opts->read_8);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1671 //normal opcode fetch is already factored into instruction timing
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1672 //back out the base 3 cycles from a read here
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1673 //not quite perfect, but it will have to do for now
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1674 cycles(&opts->gen, -3);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1675 check_cycles_int(&opts->gen, address);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1676 call(code, opts->gen.save_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1677 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1678 push_r(code, opts->gen.context_reg);
712 382a2b5b70c0 Fix crash bug in Z80 interpreter Michael Pavone <pavone@retrodev.com> parents: 702 diff changeset	1679 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	1680 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1681 pop_r(code, opts->gen.context_reg);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1682 call(code, opts->gen.load_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1683 jmp_r(code, opts->gen.scratch1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1684 stub.last = code->cur;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1685 return stub;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1686 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1687
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1688
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1689 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1690 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1691 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1692 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1693 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1694 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1695 } else {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1696 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1697 map = context->banked_code_map;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1698 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1699 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1700 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1701 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1702 }
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1703 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1704 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1705 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1706
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1707 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1708 {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1709 //TODO: Fix for addresses >= 0x4000
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1710 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1711 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1712 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1713 return opts->gen.ram_inst_sizes[0][address & 0x1FFF];
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1714 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1715
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1716 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1717 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1718 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1719 native_map_slot *map;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1720 z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1721 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1722 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1723 map = context->static_code_map;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1724 opts->gen.ram_inst_sizes[0][address] = native_size;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1725 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1726 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1727 } else {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1728 //HERE
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1729 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1730 map = context->banked_code_map;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1731 if (!map->offsets) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1732 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1733 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1734 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1735 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1736 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1737 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1738 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1739 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1740 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1741 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1742 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1743 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1744 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1745 } else {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1746 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1747 map = context->banked_code_map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1748 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1749 if (!map->offsets) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1750 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1751 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1752 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1753 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1754 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1755 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1756
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1757 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1758
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1759 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1760 {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1761 //TODO: Fixme for address >= 0x4000
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1762 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1763 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1764 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1765 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1766 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1767 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1768 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1769 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1770 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1771 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1772 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1773 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1774 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1775
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1776 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1777 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1778 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1779 if (inst_start != INVALID_INSTRUCTION_START) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1780 code_ptr dst = z80_get_native_address(context, inst_start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1781 code_info code = {dst, dst+16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1782 z80_options * opts = context->options;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	1783 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1784 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1785 call(&code, opts->retrans_stub);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1786 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1787 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1788 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1789
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1790 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1791 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1792 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1793 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1794 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1795 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1796 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1797 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1798 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1799 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1800 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1801 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1802
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1803 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1804 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1805 z80_options * opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1806 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1807 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1808 translate_z80_stream(context, opts->gen.deferred->address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1809 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1810 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1811
559 6b248602ab84 blastem builds and almost works on OS X now Mike Pavone <pavone@retrodev.com> parents: 506 diff changeset	1812 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst");
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	1813 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1814 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1815 char disbuf[80];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1816 z80_options * opts = context->options;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1817 uint8_t orig_size = z80_get_native_inst_size(opts, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1818 code_info *code = &opts->gen.code;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1819 uint8_t after, inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1820 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1821 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1822 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1823 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1824 z80_disasm(&instbuf, disbuf, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1825 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1826 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1827 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1828 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	1829 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1830 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1831 if (orig_size != ZMAX_NATIVE_SIZE) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1832 check_alloc_code(code, ZMAX_NATIVE_SIZE);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1833 code_ptr start = code->cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1834 deferred_addr * orig_deferred = opts->gen.deferred;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1835 translate_z80inst(&instbuf, context, address, 0);
644 2d7e84ae818c Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one Michael Pavone <pavone@retrodev.com> parents: 628 diff changeset	1836 /*
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1837 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1838 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1839 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1840 remove_deferred_until(&opts->gen.deferred, orig_deferred);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1841 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1842 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1843 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1844 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1845 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1846 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1847 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1848 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1849 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1850 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1851 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1852 }*/
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1853 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1854 code_info tmp_code = {orig_start, orig_start + 16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1855 jmp(&tmp_code, start);
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1856 tmp_code = *code;
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1857 code->cur = start + ZMAX_NATIVE_SIZE;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1858 if (!z80_is_terminal(&instbuf)) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1859 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst));
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1860 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1861 z80_handle_deferred(context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1862 return start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1863 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1864 code_info tmp_code = *code;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1865 code->cur = orig_start;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1866 code->last = orig_start + ZMAX_NATIVE_SIZE;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1867 translate_z80inst(&instbuf, context, address, 0);
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1868 code_info tmp2 = *code;
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1869 *code = tmp_code;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1870 if (!z80_is_terminal(&instbuf)) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1871
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1872 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1873 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1874 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1875 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1876 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1877 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1878
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1879 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1880 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1881 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1882 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1883 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1884 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1885 z80_options * opts = context->options;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1886 uint32_t start_address = address;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	1887
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1888 do
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1889 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1890 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1891 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1892 do {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1893 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1894 if (existing) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1895 jmp(&opts->gen.code, existing);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1896 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1897 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1898 uint8_t * encoded, *next;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1899 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1900 if (!encoded) {
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1901 code_info stub = z80_make_interp_stub(context, address);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1902 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1903 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1904 }
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1905 //make sure prologue is in a contiguous chunk of code
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1906 check_code_prologue(&opts->gen.code);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1907 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1908 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1909 z80_disasm(&inst, disbuf, address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1910 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1911 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1912 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1913 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1914 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1915 #endif
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1916 code_ptr start = opts->gen.code.cur;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	1917 translate_z80inst(&inst, context, address, 0);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1918 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1919 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1920 address &= 0xFFFF;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1921 } while (!z80_is_terminal(&inst));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1922 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1923 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1924 address = opts->gen.deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1925 dprintf("defferred address: %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1926 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1927 } while (opts->gen.deferred);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1928 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1929
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1930 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, uint32_t clock_divider)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1931 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1932 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1933
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1934 options->gen.memmap = chunks;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1935 options->gen.memmap_chunks = num_chunks;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1936 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1937 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1938 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1939 options->gen.bus_cycles = 3;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1940 options->gen.clock_divider = clock_divider;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1941 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1942 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
620 9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken. Michael Pavone <pavone@retrodev.com> parents: 601 diff changeset	1943 options->gen.ram_flags_shift = 7;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1944
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1945 options->flags = 0;
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1946 #ifdef X86_64
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1947 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1948 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1949 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1950 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1951 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1952 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1953 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1954 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1955 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1956 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1957 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1958 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1959 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1960 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1961 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1962 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1963 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1964 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1965 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1966 options->regs[Z80_IY] = R8;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1967
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1968 options->gen.scratch1 = R13;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1969 options->gen.scratch2 = R14;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1970 #else
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1971 memset(options->regs, -1, sizeof(options->regs));
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1972 options->regs[Z80_A] = RAX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1973 options->regx[Z80_SP] = RBX;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1974
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1975 options->gen.scratch1 = RCX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1976 options->gen.scratch2 = RDX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1977 #endif
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1978
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1979 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1980 options->gen.cycles = RBP;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1981 options->gen.limit = RDI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1982
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1983 options->gen.native_code_map = malloc(sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1984 memset(options->gen.native_code_map, 0, sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1985 options->gen.deferred = NULL;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1986 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1987 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1988 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1989
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1990 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1991 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1992
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1993 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1994 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1995 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1996
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1997 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1998 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1999 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2000 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2001 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2002 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2003 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2004 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2005 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2006 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2007 size = SZ_B;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2008 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2009 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2010 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2011 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2012 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2013 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2014 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2015 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2016 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2017 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2018 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2019 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2020 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2021 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2022
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2023 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2024 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2025 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2026 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2027 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2028 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2029 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2030 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2031 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2032 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2033 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2034 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2035 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2036 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2037 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2038 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2039 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2040 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2041 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2042 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2043 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2044 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2045 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2046 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2047 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2048 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2049 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2050 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2051
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2052 options->native_addr = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2053 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2054 push_r(code, options->gen.context_reg);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2055 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D);
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2056 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2057 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2058 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2059 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2060 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2061
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2062 options->gen.handle_cycle_limit = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2063 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2064 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2065 jcc(code, CC_B, no_sync);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2066 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2067 call(code, options->save_context_scratch);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2068 pop_r(code, RAX); //return address in read/write func
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2069 pop_r(code, RBX); //return address in translated code
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2070 sub_ir(code, 5, RAX, SZ_PTR); //adjust return address to point to the call that got us here
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2071 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2072 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2073 restore_callee_save_regs(code);
598 faad1927d836 Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80 Michael Pavone <pavone@retrodev.com> parents: 597 diff changeset	2074 *no_sync = code->cur - (no_sync + 1);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2075 //return to caller of z80_run
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2076 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2077
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2078 options->gen.handle_code_write = (code_ptr)z80_handle_code_write;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2079
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2080 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2081 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2082
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2083 options->gen.handle_cycle_limit_int = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2084 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2085 code_ptr skip_int = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2086 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2087 //set limit to the cycle limit
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2088 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2089 //disable interrupts
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2090 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2091 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2092 cycles(&options->gen, 7);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2093 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2094 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2095 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2096 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2097 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2098 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2099 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2100 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2101 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2102 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2103 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2104 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2105 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2106 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2107 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2108 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2109 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2110 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2111 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2112 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2113 //dispose of return address as we'll be jumping somewhere else
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2114 pop_r(code, options->gen.scratch2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2115 //TODO: Support interrupt mode 0 and 2
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2116 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2117 call(code, options->native_addr);
663 7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	2118 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR);
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2119 restore_callee_save_regs(code);
663 7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	2120 //return to caller of z80_run to sync
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	2121 retn(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2122 *skip_int = code->cur - (skip_int+1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2123 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2124 code_ptr skip_sync = code->cur + 1;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2125 jcc(code, CC_B, skip_sync);
702 144df1a6d3b9 Save PC to context struct when syncing Z80 at instruction start. This fixes saving savestates and probably the Z80 debugger as well Michael Pavone <pavone@retrodev.com> parents: 701 diff changeset	2126 //save PC
144df1a6d3b9 Save PC to context struct when syncing Z80 at instruction start. This fixes saving savestates and probably the Z80 debugger as well Michael Pavone <pavone@retrodev.com> parents: 701 diff changeset	2127 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2128 options->do_sync = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2129 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2130 pop_rind(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2131 //restore callee saved registers
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2132 restore_callee_save_regs(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2133 //return to caller of z80_run
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2134 *skip_sync = code->cur - (skip_sync+1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2135 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2136
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2137 options->read_io = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2138 check_cycles(&options->gen);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2139 cycles(&options->gen, 4);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2140 //Genesis has no IO hardware and always returns FF
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2141 //eventually this should use a second memory map array
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2142 mov_ir(code, 0xFF, options->gen.scratch1, SZ_B);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2143 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2144
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2145 options->write_io = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2146 check_cycles(&options->gen);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2147 cycles(&options->gen, 4);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2148 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2149
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2150 options->read_16 = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2151 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2152 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2153 //TODO: figure out how to handle the extra wait state for word reads to bank area
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2154 //may also need special handling to avoid too much stack depth when access is blocked
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2155 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2156 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2157 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2158 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2159 add_ir(code, 1, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2160 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2161 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2162 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2163 shl_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2164 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2165 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2166
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2167 options->write_16_highfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2168 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2169 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2170 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2171 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2172 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2173 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2174 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2175 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2176 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2177 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2178 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2179 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2180 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2181 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2182
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2183 options->write_16_lowfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2184 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2185 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2186 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2187 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2188 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2189 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2190 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2191 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2192 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2193 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2194 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2195 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2196 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2197 retn(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2198
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2199 options->retrans_stub = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2200 //pop return address
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2201 pop_r(code, options->gen.scratch2);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2202 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2203 //adjust pointer before move and call instructions that got us here
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2204 sub_ir(code, 11, options->gen.scratch2, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2205 push_r(code, options->gen.context_reg);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2206 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2207 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2208 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2209 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2210 jmp_r(code, options->gen.scratch1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2211
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2212 options->run = (z80_run_fun)code->cur;
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2213 save_callee_save_regs(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2214 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR);
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2215 call(code, options->load_context_scratch);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2216 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2217 code_ptr no_extra = code->cur+1;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2218 jcc(code, CC_Z, no_extra);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2219 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc));
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2220 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2221 *no_extra = code->cur - (no_extra + 1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2222 jmp_rind(code, options->gen.context_reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2223 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2224
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2225 void init_z80_context(z80_context * context, z80_options * options)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2226 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2227 memset(context, 0, sizeof(*context));
360 c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error Mike Pavone <pavone@retrodev.com> parents: 335 diff changeset	2228 context->static_code_map = malloc(sizeof(*context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2229 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2230 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2231 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2232 context->banked_code_map = malloc(sizeof(native_map_slot));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2233 memset(context->banked_code_map, 0, sizeof(native_map_slot));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2234 context->options = options;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2235 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2236 context->int_pulse_start = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2237 context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2238 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2239
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2240 void z80_run(z80_context * context, uint32_t target_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2241 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2242 if (context->reset \|\| context->busack) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2243 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2244 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2245 if (context->current_cycle < target_cycle) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2246 //busreq is sampled at the end of an m-cycle
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2247 //we can approximate that by running for a single m-cycle after a bus request
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2248 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2249 if (!context->native_pc) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2250 context->native_pc = z80_get_native_address_trans(context, context->pc);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2251 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2252 while (context->current_cycle < context->sync_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2253 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2254 if (context->int_pulse_end < context->current_cycle \|\| context->int_pulse_end == CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2255 z80_next_int_pulse(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2256 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2257 if (context->iff1) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2258 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2259 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2260 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2261 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2262 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
670 f4f3e74b0ce6 Restore Z80 interrupt pulse duration and make a small improvement to debug print output Michael Pavone <pavone@retrodev.com> parents: 668 diff changeset	2263 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end);
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2264 context->options->run(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2265 dprintf("Z80 ran to cycle %d\n", context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2266 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2267 if (context->busreq) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2268 context->busack = 1;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2269 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2270 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2271 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2272 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2273 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2274
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2275 void z80_assert_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2276 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2277 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2278 context->reset = 1;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2279 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2280
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2281 void z80_clear_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2282 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2283 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2284 if (context->reset) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2285 //TODO: Handle case where reset is not asserted long enough
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2286 context->im = 0;
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2287 context->iff1 = context->iff2 = 0;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2288 context->native_pc = NULL;
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2289 context->extra_pc = NULL;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2290 context->pc = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2291 context->reset = 0;
676 41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	2292 if (context->busreq) {
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	2293 //TODO: Figure out appropriate delay
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	2294 context->busack = 1;
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	2295 }
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2296 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2297 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2298
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2299 void z80_assert_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2300 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2301 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2302 context->busreq = 1;
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	2303 }
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2304
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2305 void z80_clear_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2306 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2307 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2308 context->busreq = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2309 context->busack = 0;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2310 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2311
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2312 uint8_t z80_get_busack(z80_context * context, uint32_t cycle)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2313 {
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2314 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2315 return context->busack;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2316 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2317
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2318 void z80_adjust_cycles(z80_context * context, uint32_t deduction)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2319 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2320 if (context->current_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2321 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2322 context->current_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2323 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2324 context->current_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2325 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2326 if (context->int_enable_cycle != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2327 if (context->int_enable_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2328 context->int_enable_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2329 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2330 context->int_enable_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2331 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2332 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2333 if (context->int_pulse_start != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2334 if (context->int_pulse_end < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2335 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2336 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2337 context->int_pulse_end -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2338 if (context->int_pulse_start < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2339 context->int_pulse_start = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2340 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2341 context->int_pulse_start -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2342 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2343 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2344 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2345 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2346
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2347 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2348 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2349 code_info code = {dst, dst+16};
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	2350 mov_ir(&code, address, context->options->gen.scratch1, SZ_W);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2351 call(&code, context->bp_stub);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2352 return code.cur-dst;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2353 }
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2354
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2355 void zcreate_stub(z80_context * context)
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2356 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2357 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2358 code_info *code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2359 check_code_prologue(code);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2360 context->bp_stub = code->cur;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2361
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2362 //Calculate length of prologue
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2363 check_cycles_int(&opts->gen, 0);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2364 int check_int_size = code->cur-context->bp_stub;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2365 code->cur = context->bp_stub;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2366
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2367 //Calculate length of patch
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2368 int patch_size = zbreakpoint_patch(context, 0, code->cur);
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2369
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2370 //Save context and call breakpoint handler
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2371 call(code, opts->gen.save_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2372 push_r(code, opts->gen.scratch1);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2373 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	2374 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2375 //Restore context
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2376 call(code, opts->gen.load_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2377 pop_r(code, opts->gen.scratch1);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2378 //do prologue stuff
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2379 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2380 uint8_t * jmp_off = code->cur+1;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2381 jcc(code, CC_NC, code->cur + 7);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2382 pop_r(code, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	2383 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2384 push_r(code, opts->gen.scratch1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2385 jmp(code, opts->gen.handle_cycle_limit_int);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2386 *jmp_off = code->cur - (jmp_off+1);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2387 //jump back to body of translated instruction
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2388 pop_r(code, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	2389 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2390 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2391 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2392
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2393 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2394 {
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2395 context->bp_handler = bp_handler;
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2396 uint8_t bit = 1 << (address % sizeof(uint8_t));
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2397 if (!(bit & context->breakpoint_flags[address / sizeof(uint8_t)])) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2398 context->breakpoint_flags[address / sizeof(uint8_t)] \|= bit;
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2399 if (!context->bp_stub) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2400 zcreate_stub(context);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2401 }
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2402 uint8_t * native = z80_get_native_address(context, address);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2403 if (native) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2404 zbreakpoint_patch(context, address, native);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2405 }
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2406 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2407 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2408
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2409 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2410 {
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	2411 context->breakpoint_flags[address / sizeof(uint8_t)] &= ~(1 << (address % sizeof(uint8_t)));
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2412 uint8_t * native = z80_get_native_address(context, address);
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	2413 if (native) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2414 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2415 code_info tmp_code = opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2416 opts->gen.code.cur = native;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2417 opts->gen.code.last = native + 16;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2418 check_cycles_int(&opts->gen, address);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2419 opts->gen.code = tmp_code;
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2420 }
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2421 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2422

Mercurial > repos > blastem

annotate z80_to_x86.c @ 715:1c2020d3e275