Mercurial > repos > blastem
annotate m68k_to_x86.c @ 544:8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 16 Feb 2014 19:21:39 -0800 |
parents | 915a1cb98bac |
children | 67cf0ce57d8d |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_x86.h" |
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7 #include "m68k_to_x86.h" |
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8 #include "68kinst.h" |
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9 #include "mem.h" |
211 | 10 #include "x86_backend.h" |
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11 #include <stdio.h> |
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12 #include <stddef.h> |
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13 #include <stdlib.h> |
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14 #include <string.h> |
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15 |
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16 #define BUS 4 |
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17 #define PREDEC_PENALTY 2 |
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18 #define CYCLES RAX |
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19 #define LIMIT RBP |
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20 #define SCRATCH1 RCX |
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21 #define SCRATCH2 RDI |
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22 #define CONTEXT RSI |
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23 |
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24 #define FLAG_N RBX |
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25 #define FLAG_V BH |
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26 #define FLAG_Z RDX |
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27 #define FLAG_C DH |
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28 |
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29 char disasm_buf[1024]; |
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30 |
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31 m68k_context * sync_components(m68k_context * context, uint32_t address); |
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32 |
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33 void handle_cycle_limit(); |
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34 void m68k_invalid(); |
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35 void set_sr(); |
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36 void set_ccr(); |
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37 void get_sr(); |
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38 void do_sync(); |
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39 void bcd_add(); |
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40 void bcd_sub(); |
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41 |
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42 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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43 { |
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44 dst = add_ir(dst, num, CYCLES, SZ_D); |
118 | 45 return dst; |
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46 } |
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47 |
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48 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address, x86_68k_options * opts) |
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49 { |
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50 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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51 uint8_t * jmp_off = dst+1; |
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52 dst = jcc(dst, CC_NC, dst + 7); |
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53 dst = mov_ir(dst, address, SCRATCH1, SZ_D); |
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54 dst = call(dst, opts->handle_cycle_limit_int); |
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55 *jmp_off = dst - (jmp_off+1); |
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56 return dst; |
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57 } |
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58 |
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59 uint8_t * check_cycles(uint8_t * dst) |
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60 { |
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61 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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62 uint8_t * jmp_off = dst+1; |
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63 dst = jcc(dst, CC_NC, dst + 7); |
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64 dst = call(dst, (uint8_t *)handle_cycle_limit); |
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65 *jmp_off = dst - (jmp_off+1); |
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66 return dst; |
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67 } |
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68 |
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69 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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70 { |
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71 if (op->addr_mode == MODE_REG) { |
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72 return opts->dregs[op->params.regs.pri]; |
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73 } |
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74 if (op->addr_mode == MODE_AREG) { |
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75 return opts->aregs[op->params.regs.pri]; |
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76 } |
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77 return -1; |
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78 } |
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79 |
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80 //must be called with an m68k_op_info that uses a register |
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81 size_t reg_offset(m68k_op_info *op) |
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82 { |
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83 if (op->addr_mode == MODE_REG) { |
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84 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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85 } |
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86 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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87 } |
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88 |
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89 void print_regs_exit(m68k_context * context) |
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90 { |
207 | 91 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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92 for (int i = 0; i < 8; i++) { |
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93 printf("d%d: %X\n", i, context->dregs[i]); |
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94 } |
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95 for (int i = 0; i < 8; i++) { |
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96 printf("a%d: %X\n", i, context->aregs[i]); |
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97 } |
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98 exit(0); |
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99 } |
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100 |
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101 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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102 { |
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103 int8_t reg = native_reg(&(inst->src), opts); |
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104 uint8_t sec_reg; |
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105 int32_t dec_amount,inc_amount; |
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106 if (reg >= 0) { |
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107 ea->mode = MODE_REG_DIRECT; |
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108 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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109 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D); |
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110 ea->base = SCRATCH1; |
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111 } else { |
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112 ea->base = reg; |
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113 } |
18
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|
114 return out; |
14
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|
115 } |
18
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116 switch (inst->src.addr_mode) |
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117 { |
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118 case MODE_REG: |
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119 case MODE_AREG: |
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120 //We only get one memory parameter, so if the dst operand is a register in memory, |
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121 //we need to copy this to a temp register first |
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122 reg = native_reg(&(inst->dst), opts); |
447
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|
123 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) |
18
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124 || inst->op == M68K_EXG) { |
447
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|
125 |
18
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126 ea->mode = MODE_REG_DISPLACE8; |
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127 ea->base = CONTEXT; |
52
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128 ea->disp = reg_offset(&(inst->src)); |
18
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129 } else { |
181
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130 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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131 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D); |
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132 } else { |
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133 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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134 } |
18
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135 ea->mode = MODE_REG_DIRECT; |
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136 ea->base = SCRATCH1; |
181
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137 //we're explicitly handling the areg dest here, so we exit immediately |
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138 return out; |
18
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139 } |
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140 break; |
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141 case MODE_AREG_PREDEC: |
216
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Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
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213
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|
142 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 :1)); |
18
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143 out = cycles(out, PREDEC_PENALTY); |
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144 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
158
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|
145 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
18
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146 } else { |
158
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|
147 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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148 } |
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149 case MODE_AREG_INDIRECT: |
447
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150 case MODE_AREG_POSTINC: |
18
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151 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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152 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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153 } else { |
52
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|
154 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
18
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155 } |
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156 switch (inst->extra.size) |
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157 { |
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158 case OPSIZE_BYTE: |
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|
159 out = call(out, opts->read_8); |
18
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160 break; |
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161 case OPSIZE_WORD: |
343
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162 out = call(out, opts->read_16); |
18
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163 break; |
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164 case OPSIZE_LONG: |
343
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165 out = call(out, opts->read_32); |
18
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166 break; |
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167 } |
447
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|
168 |
18
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169 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
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182
diff
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|
170 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1)); |
18
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171 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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172 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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|
173 } else { |
52
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51
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|
174 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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|
175 } |
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176 } |
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|
177 ea->mode = MODE_REG_DIRECT; |
184
ebcbdd1c4cc8
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183
diff
changeset
|
178 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1; |
18
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|
179 break; |
71
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|
180 case MODE_AREG_DISPLACE: |
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diff
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|
181 out = cycles(out, BUS); |
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182 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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183 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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184 } else { |
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|
185 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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|
186 } |
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187 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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188 switch (inst->extra.size) |
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189 { |
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|
190 case OPSIZE_BYTE: |
343
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|
191 out = call(out, opts->read_8); |
71
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|
192 break; |
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193 case OPSIZE_WORD: |
343
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|
194 out = call(out, opts->read_16); |
71
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195 break; |
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|
196 case OPSIZE_LONG: |
343
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197 out = call(out, opts->read_32); |
71
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|
198 break; |
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|
199 } |
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|
200 ea->mode = MODE_REG_DIRECT; |
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|
201 ea->base = SCRATCH1; |
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|
202 break; |
81
6d231dbe75ab
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78
diff
changeset
|
203 case MODE_AREG_INDEX_DISP8: |
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78
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|
204 out = cycles(out, 6); |
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78
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|
205 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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changeset
|
206 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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|
207 } else { |
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|
208 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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|
209 } |
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changeset
|
210 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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|
211 if (inst->src.params.regs.sec & 1) { |
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78
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changeset
|
212 if (inst->src.params.regs.sec & 0x10) { |
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78
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changeset
|
213 if (opts->aregs[sec_reg] >= 0) { |
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78
diff
changeset
|
214 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
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78
diff
changeset
|
215 } else { |
6d231dbe75ab
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parents:
78
diff
changeset
|
216 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
217 } |
6d231dbe75ab
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parents:
78
diff
changeset
|
218 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
219 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
220 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
221 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
222 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
223 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
224 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
225 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
226 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
227 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
228 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
229 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
230 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
231 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
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|
232 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
233 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
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|
234 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
235 } else { |
6d231dbe75ab
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78
diff
changeset
|
236 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
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|
237 } |
6d231dbe75ab
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78
diff
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|
238 } |
6d231dbe75ab
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78
diff
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|
239 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
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78
diff
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|
240 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
241 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
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78
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|
242 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
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diff
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|
243 } |
97
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
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|
244 switch (inst->extra.size) |
c7185fd840fc
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96
diff
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|
245 { |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
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|
246 case OPSIZE_BYTE: |
343
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Mostly working runtime generation of memory map read/write functions
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324
diff
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|
247 out = call(out, opts->read_8); |
97
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
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|
248 break; |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
changeset
|
249 case OPSIZE_WORD: |
343
467bfa17004a
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324
diff
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|
250 out = call(out, opts->read_16); |
97
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
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|
251 break; |
c7185fd840fc
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96
diff
changeset
|
252 case OPSIZE_LONG: |
343
467bfa17004a
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324
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|
253 out = call(out, opts->read_32); |
97
c7185fd840fc
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96
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|
254 break; |
c7185fd840fc
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96
diff
changeset
|
255 } |
c7185fd840fc
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96
diff
changeset
|
256 ea->mode = MODE_REG_DIRECT; |
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96
diff
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|
257 ea->base = SCRATCH1; |
81
6d231dbe75ab
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78
diff
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|
258 break; |
71
f80fa1776507
Implement more instructions and address modes
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70
diff
changeset
|
259 case MODE_PC_DISPLACE: |
f80fa1776507
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70
diff
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|
260 out = cycles(out, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
261 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
f80fa1776507
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70
diff
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|
262 switch (inst->extra.size) |
f80fa1776507
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70
diff
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|
263 { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
264 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
265 out = call(out, opts->read_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
266 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
267 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
268 out = call(out, opts->read_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
269 break; |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
270 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
271 out = call(out, opts->read_32); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
272 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
273 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
274 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
275 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
276 break; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
277 case MODE_PC_INDEX_DISP8: |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
278 out = cycles(out, 6); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
279 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
280 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
281 if (inst->src.params.regs.sec & 1) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
282 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
283 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
284 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
285 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
286 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
287 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
288 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
289 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
290 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
291 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
292 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
293 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
294 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
295 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
296 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
297 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
298 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
299 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
300 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
301 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
302 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
303 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
304 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
305 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
306 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
307 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
308 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
309 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
310 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
311 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
312 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
313 } |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
314 switch (inst->extra.size) |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
315 { |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
316 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
317 out = call(out, opts->read_8); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
318 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
319 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
320 out = call(out, opts->read_16); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
321 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
322 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
323 out = call(out, opts->read_32); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
324 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
325 } |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
326 ea->mode = MODE_REG_DIRECT; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
327 ea->base = SCRATCH1; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
328 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
329 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
330 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
331 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
332 out = cycles(out, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
333 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
334 out = cycles(out, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
335 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
336 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
337 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
338 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
339 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
340 out = call(out, opts->read_8); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
341 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
342 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
343 out = call(out, opts->read_16); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
344 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
345 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
346 out = call(out, opts->read_32); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
347 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
348 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
349 ea->mode = MODE_REG_DIRECT; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
350 ea->base = SCRATCH1; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
351 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
352 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
353 case MODE_IMMEDIATE_WORD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
354 if (inst->variant != VAR_QUICK) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
355 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
356 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
357 ea->mode = MODE_IMMED; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
358 ea->disp = inst->src.params.immed; |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
359 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
360 ea->disp |= 0xFFFF0000; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
361 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
362 return out; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
363 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
364 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
365 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
366 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
367 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
368 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
369 if (ea->mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
370 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
371 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
372 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
373 ea->mode = MODE_REG_DIRECT; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
374 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
375 ea->base = SCRATCH1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
376 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
377 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
378 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
379 |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
380 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
381 { |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
382 int8_t reg = native_reg(&(inst->dst), opts), sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
383 int32_t dec_amount, inc_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
384 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
385 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
386 ea->base = reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
387 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
388 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
389 switch (inst->dst.addr_mode) |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 { |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 case MODE_REG: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 case MODE_AREG: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
393 ea->mode = MODE_REG_DISPLACE8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
394 ea->base = CONTEXT; |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
395 ea->disp = reg_offset(&(inst->dst)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
396 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
397 case MODE_AREG_PREDEC: |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
398 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
399 out = push_r(out, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
400 } |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
401 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
402 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
403 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
404 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
405 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
406 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
407 case MODE_AREG_INDIRECT: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
408 case MODE_AREG_POSTINC: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
409 if (fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
410 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
411 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
412 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
413 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
414 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
415 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
416 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
417 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
418 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
419 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
420 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
421 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
422 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
423 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
424 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
425 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
426 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
427 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
428 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
429 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
430 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
431 //restore src operand to SCRATCH2 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
432 out =pop_r(out, SCRATCH2); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
433 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
434 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
435 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
436 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
437 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
438 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
439 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
440 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
441 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
442 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
443 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
444 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
445 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
446 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
447 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
448 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
449 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
450 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
451 ea->base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
452 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
453 case MODE_AREG_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
454 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
455 reg = fake_read ? SCRATCH2 : SCRATCH1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
456 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
457 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
458 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
459 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
460 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
461 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
462 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
463 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
464 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
465 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
466 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
467 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
468 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
469 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
470 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
471 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
472 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
473 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
474 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
475 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
476 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
477 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
478 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
479 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
480 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
481 case MODE_AREG_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
482 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
483 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
484 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
485 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
486 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
487 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
488 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
489 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
490 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
491 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
492 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
493 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
494 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
495 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
496 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
497 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
498 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
499 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
500 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
501 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
502 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
503 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
504 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
505 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
506 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
507 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
508 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
509 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
510 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
511 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
512 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
513 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
514 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
515 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
516 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
517 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
518 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
519 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
520 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
521 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
522 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
523 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
524 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
525 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
526 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
527 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
528 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
529 out = call(out, opts->read_8); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
530 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
531 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
532 out = call(out, opts->read_16); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
533 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
534 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
535 out = call(out, opts->read_32); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
536 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
537 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
538 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
539 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
540 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
541 ea->base = SCRATCH1; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
542 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
543 case MODE_PC_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
544 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
545 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
546 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
547 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
548 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
549 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
550 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
551 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
552 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
553 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
554 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
555 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
556 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
557 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
558 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
559 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
560 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
561 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
562 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
563 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
564 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
565 case MODE_PC_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
566 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
567 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
568 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
569 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
570 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
571 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
572 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
573 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
574 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
575 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
576 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
577 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
578 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
579 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
580 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
581 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
582 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
583 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
584 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
585 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
586 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
587 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
588 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
589 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
590 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
591 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
592 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
593 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
594 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
595 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
596 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
597 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
598 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
599 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
600 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
601 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
602 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
603 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
604 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
605 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
606 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
607 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
608 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
609 out = call(out, opts->read_8); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
610 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
611 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
612 out = call(out, opts->read_16); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
613 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
614 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
615 out = call(out, opts->read_32); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
616 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
617 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
618 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
619 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
620 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
621 ea->base = SCRATCH1; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
622 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
623 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
624 case MODE_ABSOLUTE_SHORT: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
625 //Add cycles for reading address from instruction stream |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
626 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0)); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
627 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
628 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
629 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
630 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
631 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
632 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
633 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
634 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
635 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
636 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
637 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
638 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
639 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
640 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
641 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
642 out = pop_r(out, SCRATCH2); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
643 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
644 ea->mode = MODE_REG_DIRECT; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
645 ea->base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
646 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
647 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
648 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
649 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
650 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
651 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
652 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
653 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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654 |
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655 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
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656 { |
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657 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
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658 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) { |
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659 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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660 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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661 } else { |
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662 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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663 } |
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664 } |
18
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665 switch (inst->extra.size) |
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666 { |
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667 case OPSIZE_BYTE: |
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668 out = call(out, opts->write_8); |
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669 break; |
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670 case OPSIZE_WORD: |
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671 out = call(out, opts->write_16); |
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672 break; |
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673 case OPSIZE_LONG: |
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674 out = call(out, opts->write_32_lowfirst); |
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675 break; |
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676 } |
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677 } |
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678 return out; |
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679 } |
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680 |
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681 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
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682 { |
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683 address &= 0xFFFFFF; |
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684 address /= 2; |
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685 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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686 if (!native_code_map[chunk].base) { |
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687 return NULL; |
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688 } |
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689 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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690 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
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691 return NULL; |
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692 } |
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693 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
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694 } |
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695 |
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696 uint8_t * get_native_from_context(m68k_context * context, uint32_t address) |
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697 { |
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698 return get_native_address(context->native_code_map, address); |
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699 } |
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700 |
193
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701 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address) |
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702 { |
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703 address &= 0xFFFFFF; |
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704 address /= 2; |
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705 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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706 if (!native_code_map[chunk].base) { |
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707 return 0; |
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708 } |
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709 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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710 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
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711 return 0; |
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712 } |
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713 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
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|
714 --address; |
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715 chunk = address / NATIVE_CHUNK_SIZE; |
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716 offset = address % NATIVE_CHUNK_SIZE; |
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|
717 } |
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|
718 return address*2; |
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|
719 } |
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|
720 |
192
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|
721 void map_native_address(m68k_context * context, uint32_t address, uint8_t * native_addr, uint8_t size, uint8_t native_size) |
18
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|
722 { |
192
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|
723 native_map_slot * native_code_map = context->native_code_map; |
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|
724 x86_68k_options * opts = context->options; |
18
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diff
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|
725 address &= 0xFFFFFF; |
192
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|
726 if (address > 0xE00000) { |
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|
727 context->ram_code_flags[(address & 0xC000) >> 14] |= 1 << ((address & 0x3800) >> 11); |
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|
728 if (((address & 0x3FFF) + size) & 0xC000) { |
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|
729 context->ram_code_flags[((address+size) & 0xC000) >> 14] |= 1 << (((address+size) & 0x3800) >> 11); |
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|
730 } |
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|
731 uint32_t slot = (address & 0xFFFF)/1024; |
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732 if (!opts->ram_inst_sizes[slot]) { |
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|
733 opts->ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512); |
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|
734 } |
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|
735 opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size; |
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|
736 } |
95
dd3c680c618c
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Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
737 address/= 2; |
18
3e7bfde7606e
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diff
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|
738 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
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diff
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|
739 if (!native_code_map[chunk].base) { |
3e7bfde7606e
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|
740 native_code_map[chunk].base = native_addr; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
741 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
6331ddec228f
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parents:
81
diff
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|
742 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
18
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diff
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|
743 } |
3e7bfde7606e
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diff
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|
744 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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diff
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|
745 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
193
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746 for(address++,size-=2; size; address++,size-=2) { |
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|
747 chunk = address / NATIVE_CHUNK_SIZE; |
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748 offset = address % NATIVE_CHUNK_SIZE; |
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|
749 if (!native_code_map[chunk].base) { |
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|
750 native_code_map[chunk].base = native_addr; |
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|
751 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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752 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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|
753 } |
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|
754 native_code_map[chunk].offsets[offset] = EXTENSION_WORD; |
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|
755 } |
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|
756 } |
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|
757 |
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758 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address) |
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|
759 { |
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|
760 if (address < 0xE00000) { |
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|
761 return 0; |
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|
762 } |
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|
763 uint32_t slot = (address & 0xFFFF)/1024; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
764 return opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512]; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
765 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
766 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
767 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
768 { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
769 int8_t reg, flags_reg, sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
770 uint8_t dir = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
771 int32_t offset; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
772 int32_t inc_amount, dec_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
773 x86_ea src; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
774 dst = translate_m68k_src(inst, &src, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
775 reg = native_reg(&(inst->dst), opts); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
776 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
777 //update statically set flags |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
778 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
779 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
780 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
781 |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
782 if (inst->dst.addr_mode != MODE_AREG) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
783 if (src.mode == MODE_REG_DIRECT) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
784 flags_reg = src.base; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
785 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
786 if (reg >= 0) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
787 flags_reg = reg; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
788 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
789 if(src.mode == MODE_REG_DISPLACE8) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
790 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
791 } else { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
792 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
793 } |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
794 src.mode = MODE_REG_DIRECT; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
795 flags_reg = src.base = SCRATCH1; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
796 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
797 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
798 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
799 uint8_t size = inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
800 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
801 { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
802 case MODE_AREG: |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
803 size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
804 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
805 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
806 if (src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
807 dst = mov_rr(dst, src.base, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
808 } else if (src.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
809 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
810 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
811 dst = mov_ir(dst, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
812 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
813 } else if(src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
814 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
815 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
816 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
817 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
818 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
819 dst = cmp_ir(dst, 0, flags_reg, size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
820 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
821 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
822 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
824 case MODE_AREG_PREDEC: |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
825 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
826 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
827 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
828 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
829 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
830 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
832 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
833 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
834 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
835 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
836 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
837 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
838 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
839 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
840 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
841 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
842 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
843 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
844 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
845 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
846 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
847 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
848 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
849 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
850 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
851 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
852 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
853 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
854 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
855 dst = call(dst, opts->write_8); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
856 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
857 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
858 dst = call(dst, opts->write_16); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
859 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
860 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
861 dst = call(dst, opts->write_32_highfirst); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
862 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
863 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
864 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
865 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
866 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
867 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
868 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
869 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
870 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
871 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
873 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
874 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
875 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
876 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
877 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
878 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
879 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
880 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
881 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
882 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
883 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
884 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
885 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
886 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
887 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
888 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
889 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
890 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
891 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
892 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
893 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
894 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
895 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
896 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
897 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
898 dst = call(dst, opts->write_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
899 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
900 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
901 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
902 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
903 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
904 dst = call(dst, opts->write_32_highfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
905 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
906 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
907 break; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
908 case MODE_AREG_INDEX_DISP8: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
909 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
910 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
911 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
912 } else { |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
913 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
914 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
915 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
916 if (inst->dst.params.regs.sec & 1) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
917 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
918 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
919 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
920 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
921 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
922 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
923 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
924 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
925 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
926 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
927 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
928 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
929 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
930 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
931 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
932 dst = push_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
933 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
934 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
935 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
936 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
937 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
938 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
939 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
940 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
941 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
942 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
943 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
944 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
945 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
946 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
947 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
948 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
949 dst = pop_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
950 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
951 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
952 if (inst->dst.params.regs.displacement) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
953 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
954 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
955 if (src.mode == MODE_REG_DIRECT) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
956 if (src.base != SCRATCH1) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
957 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
958 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
959 } else if (src.mode == MODE_REG_DISPLACE8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
960 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
961 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
962 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
963 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
964 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
965 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
966 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
967 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
968 } |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
969 switch (inst->extra.size) |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
970 { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
971 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
972 dst = call(dst, opts->write_8); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
973 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
974 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
975 dst = call(dst, opts->write_16); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
976 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
977 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
978 dst = call(dst, opts->write_32_highfirst); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
979 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
980 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
981 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
982 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
983 dst = cycles(dst, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
984 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
985 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
986 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
987 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
988 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
989 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
990 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
991 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
992 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
993 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
994 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
995 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
996 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
997 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
998 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
999 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1000 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1001 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1002 dst = call(dst, opts->write_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1003 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1004 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1005 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1006 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1007 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1008 dst = call(dst, opts->write_32_highfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1009 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1010 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1011 break; |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1012 case MODE_PC_INDEX_DISP8: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1013 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1014 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1015 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1016 if (inst->dst.params.regs.sec & 1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1017 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1018 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1019 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1020 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1021 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1022 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1023 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1024 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1025 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1026 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1027 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1028 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1029 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1030 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1031 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1032 dst = push_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1033 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1034 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1035 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1036 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1037 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1038 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1039 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1040 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1041 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1042 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1043 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1044 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1045 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1046 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1047 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1048 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1049 dst = pop_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1050 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1051 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1052 if (inst->dst.params.regs.displacement) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1053 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1054 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1055 if (src.mode == MODE_REG_DIRECT) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1056 if (src.base != SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1057 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1058 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1059 } else if (src.mode == MODE_REG_DISPLACE8) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1060 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1061 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1062 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1063 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1064 if (inst->dst.addr_mode != MODE_AREG) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1065 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1066 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1067 dst = setcc_r(dst, CC_S, FLAG_N); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1068 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1069 switch (inst->extra.size) |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1070 { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1071 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1072 dst = call(dst, opts->write_8); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1073 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1074 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1075 dst = call(dst, opts->write_16); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1076 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1077 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1078 dst = call(dst, opts->write_32_highfirst); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1079 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1080 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1081 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1082 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1083 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1084 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1085 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1086 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1087 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1088 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1089 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1090 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1091 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1092 } |
3b79cbcf6846
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parents:
53
diff
changeset
|
1093 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1094 dst = cycles(dst, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1095 } else { |
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parents:
53
diff
changeset
|
1096 dst = cycles(dst, BUS); |
3b79cbcf6846
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parents:
53
diff
changeset
|
1097 } |
3b79cbcf6846
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parents:
53
diff
changeset
|
1098 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1099 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
changeset
|
1100 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
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|
1101 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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parents:
183
diff
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|
1102 dst = setcc_r(dst, CC_S, FLAG_N); |
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parents:
183
diff
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|
1103 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1104 switch (inst->extra.size) |
3b79cbcf6846
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parents:
53
diff
changeset
|
1105 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
53
diff
changeset
|
1106 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1107 dst = call(dst, opts->write_8); |
54
3b79cbcf6846
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parents:
53
diff
changeset
|
1108 break; |
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parents:
53
diff
changeset
|
1109 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1110 dst = call(dst, opts->write_16); |
54
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parents:
53
diff
changeset
|
1111 break; |
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parents:
53
diff
changeset
|
1112 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
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|
1113 dst = call(dst, opts->write_32_highfirst); |
54
3b79cbcf6846
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parents:
53
diff
changeset
|
1114 break; |
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parents:
53
diff
changeset
|
1115 } |
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parents:
53
diff
changeset
|
1116 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1117 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1118 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1119 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1120 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1122 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1123 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1124 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1125 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1126 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1127 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1128 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1129 { |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1130 int8_t bit,reg,sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1131 uint8_t early_cycles; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1132 if(inst->src.addr_mode == MODE_REG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1133 //reg to mem |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1134 early_cycles = 8; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1135 int8_t dir; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1136 switch (inst->dst.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1137 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1138 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1139 case MODE_AREG_PREDEC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1140 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1141 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1142 } else { |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1143 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1144 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1145 break; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1146 case MODE_AREG_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1147 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1148 reg = SCRATCH2; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1149 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1150 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1151 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1152 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1153 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1154 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1155 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1156 case MODE_AREG_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1157 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1158 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1159 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1160 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1161 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1162 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1163 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1164 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1165 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1166 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1167 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1168 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1169 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1170 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1171 } else { |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1172 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1173 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1174 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1175 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1176 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1177 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1178 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1179 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1180 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1181 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1182 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1183 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1184 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1185 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1186 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1187 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1188 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1189 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
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Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1190 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1191 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1192 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1193 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1194 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1195 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1196 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1197 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1198 case MODE_PC_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1199 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1200 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1201 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1202 case MODE_PC_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1203 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1204 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1205 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1206 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1207 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1208 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1209 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1210 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1211 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1212 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1213 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1214 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1215 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1216 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1217 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1218 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1219 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1220 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1221 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1222 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1223 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1224 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1225 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1226 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1227 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1228 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1229 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1230 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1231 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1232 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1233 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1234 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1235 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1236 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1237 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1238 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1239 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1240 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1241 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1242 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1243 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1244 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1245 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1246 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1247 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1248 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1249 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1250 } |
210
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1251 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1252 reg = 15; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1253 dir = -1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1254 } else { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1255 reg = 0; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1256 dir = 1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1257 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1258 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1259 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1260 if (inst->src.params.immed & (1 << bit)) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1261 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1262 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1263 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1264 dst = push_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1265 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1266 if (opts->aregs[reg-8] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1267 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1268 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1269 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1270 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1271 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1272 if (opts->dregs[reg] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1273 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1274 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1275 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1276 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1277 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1278 if (inst->extra.size == OPSIZE_LONG) { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1279 dst = call(dst, opts->write_32_lowfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1280 } else { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1281 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1282 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1283 dst = pop_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1284 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1285 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1286 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1287 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1288 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1289 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1290 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1291 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1292 } else { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1293 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1294 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1295 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1296 } else { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1297 //mem to reg |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1298 early_cycles = 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1299 switch (inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1300 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1301 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1302 case MODE_AREG_POSTINC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1303 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1304 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1305 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1306 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1307 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1308 break; |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1309 case MODE_AREG_DISPLACE: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1310 early_cycles += BUS; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1311 reg = SCRATCH2; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1312 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1313 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1314 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1315 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1316 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1317 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1318 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1319 case MODE_AREG_INDEX_DISP8: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1320 early_cycles += 6; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1321 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1322 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1323 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1324 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1325 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1326 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1327 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1328 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1329 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1330 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1331 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1332 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1333 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1334 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1335 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1336 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1337 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1338 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1339 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1340 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1341 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1342 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1343 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1344 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1345 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1346 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1347 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1348 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1349 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1350 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1351 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1352 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1353 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1354 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1355 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1356 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1357 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1358 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1359 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1360 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1361 case MODE_PC_DISPLACE: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1362 early_cycles += BUS; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1363 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1364 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1365 case MODE_PC_INDEX_DISP8: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1366 early_cycles += 6; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1367 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1368 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1369 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1370 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1371 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1372 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1373 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1374 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1375 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1376 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1377 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1378 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1379 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1380 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1381 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1382 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1383 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1384 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1385 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1386 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1387 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1388 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1389 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1390 } else { |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1391 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1392 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1393 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1394 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1395 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1396 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1397 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1398 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1399 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1400 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1401 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1402 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1403 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1404 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1405 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1406 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1407 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1408 break; |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1409 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1410 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1411 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1412 exit(1); |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1413 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1414 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1415 for(reg = 0; reg < 16; reg ++) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1416 if (inst->dst.params.immed & (1 << reg)) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1417 dst = push_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1418 if (inst->extra.size == OPSIZE_LONG) { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1419 dst = call(dst, opts->read_32); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1420 } else { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1421 dst = call(dst, opts->read_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1422 } |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1423 if (inst->extra.size == OPSIZE_WORD) { |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1424 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1425 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1426 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1427 if (opts->aregs[reg-8] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1428 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1429 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1430 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1431 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1432 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1433 if (opts->dregs[reg] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1434 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1435 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1436 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1437 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1438 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1439 dst = pop_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1440 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1441 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1442 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1443 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1444 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1445 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1446 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1447 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1448 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1449 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1450 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1451 //prefetch |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1452 dst = cycles(dst, 4); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1453 return dst; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1454 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1455 |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1456 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1457 { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1458 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1459 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1460 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1461 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1462 int8_t reg = native_reg(&(inst->dst), opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1463 if (reg >= 0) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1464 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1465 return xor_rr(dst, reg, reg, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1466 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1467 x86_ea dst_op; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1468 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1469 if (dst_op.mode == MODE_REG_DIRECT) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1470 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1471 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1472 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1473 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1474 dst = m68k_save_result(inst, dst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1475 return dst; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1476 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1477 |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1478 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1479 { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1480 x86_ea dst_op; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1481 uint8_t dst_size = inst->extra.size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1482 inst->extra.size--; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1483 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1484 if (dst_op.mode == MODE_REG_DIRECT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1485 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1486 dst = cmp_ir(dst, 0, dst_op.base, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1487 } else { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1488 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1489 dst = cmp_ir(dst, 0, SCRATCH1, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1490 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1491 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1492 inst->extra.size = dst_size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1493 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1494 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1495 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1496 dst = setcc_r(dst, CC_S, FLAG_N); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1497 //M68K EXT only operates on registers so no need for a call to save result here |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1498 return dst; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1499 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1500 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1501 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1502 { |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1503 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1504 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1505 { |
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Implement more instructions and address modes
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parents:
70
diff
changeset
|
1506 case MODE_AREG_INDIRECT: |
f80fa1776507
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parents:
70
diff
changeset
|
1507 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1508 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1509 if (dst_reg >= 0) { |
f80fa1776507
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parents:
70
diff
changeset
|
1510 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1511 } else { |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1512 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1513 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1514 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1515 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1516 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1517 } else { |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1518 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1519 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1520 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1521 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1522 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1523 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1524 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1525 if (dst_reg >= 0) { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1526 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1527 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1528 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1529 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1530 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1531 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1532 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1533 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1534 } else { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1535 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1536 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1537 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1538 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1539 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1540 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1541 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1542 } |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1543 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1544 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1545 break; |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1546 case MODE_AREG_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1547 dst = cycles(dst, 12); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1548 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1549 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1550 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1551 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1552 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1553 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1554 if (inst->src.params.regs.sec & 1) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1555 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1556 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1557 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1558 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1559 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1560 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1561 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1562 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1563 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1564 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1565 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1566 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1567 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1568 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1569 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1570 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1571 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1572 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1573 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1574 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1575 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1576 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1577 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1578 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1579 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1580 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1581 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1582 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1583 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1584 if (inst->src.params.regs.displacement) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1585 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1586 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1587 if (dst_reg >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1588 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1589 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1590 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1591 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1592 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1593 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1594 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1595 if (dst_reg >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1596 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1597 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1598 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1599 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1600 break; |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1601 case MODE_PC_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1602 dst = cycles(dst, BUS*3); |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1603 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1604 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1605 if (inst->src.params.regs.sec & 1) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1606 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1607 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1608 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1609 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1610 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1611 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1612 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1613 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1614 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1615 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1616 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1617 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1618 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1619 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1620 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1621 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1622 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1623 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1624 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1625 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1626 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1627 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1628 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1629 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1630 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1631 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1632 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1633 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1634 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1635 if (inst->src.params.regs.displacement) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1636 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1637 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1638 if (dst_reg >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1639 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1640 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1641 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1642 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1643 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1644 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1645 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1646 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1647 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1648 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1649 } else { |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1650 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1651 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1652 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1653 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1654 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1655 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1656 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1657 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1658 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1659 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1660 |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1661 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1662 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1663 uint8_t sec_reg; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1664 switch(inst->src.addr_mode) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1665 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1666 case MODE_AREG_INDIRECT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1667 dst = cycles(dst, BUS); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1668 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1669 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1670 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1671 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1672 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1673 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1674 case MODE_AREG_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1675 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1676 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1677 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1678 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1679 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1680 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1681 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1682 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1683 case MODE_AREG_INDEX_DISP8: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1684 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1685 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1686 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1687 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1688 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1689 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1690 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1691 if (inst->src.params.regs.sec & 1) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1692 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1693 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1694 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1695 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1696 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1697 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1698 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1699 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1700 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1701 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1702 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1703 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1704 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1705 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1706 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1707 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1708 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1709 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1710 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1711 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1712 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1713 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1714 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1715 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1716 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1717 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1718 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1719 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1720 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1721 if (inst->src.params.regs.displacement) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1722 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1723 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1724 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1725 case MODE_PC_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1726 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1727 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1728 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1729 case MODE_ABSOLUTE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1730 case MODE_ABSOLUTE_SHORT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1731 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1732 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1733 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1734 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1735 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1736 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1737 exit(1); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1738 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1739 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1740 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1741 dst = call(dst, opts->write_32_lowfirst); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1742 return dst; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1743 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1744 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1745 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1746 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1747 int32_t disp = inst->src.params.immed; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1748 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1749 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1750 dst = cycles(dst, 10); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1751 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1752 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1753 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1754 dst = call(dst, opts->write_32_highfirst); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1755 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1756 if (!dest_addr) { |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1757 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1758 //dummy address to be replaced later |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1759 dest_addr = dst + 256; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1760 } |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
1761 dst = jmp(dst, (char *)dest_addr); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1762 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1763 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1764 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1765 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1766 { |
156
3900cfde9dbb
Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Mike Pavone <pavone@retrodev.com>
parents:
155
diff
changeset
|
1767 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1768 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1769 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1770 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1771 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1772 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1773 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1774 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1775 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1776 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1777 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1778 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1779 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1780 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1781 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1782 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1783 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1784 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1785 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1786 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1787 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1788 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1789 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1790 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1791 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1792 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1793 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1794 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1795 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1796 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1797 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1798 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1799 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1800 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1801 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1802 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1803 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1804 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1805 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1806 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1807 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1808 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1809 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1810 case COND_LESS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1811 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1812 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1813 case COND_GREATER: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1814 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1815 case COND_LESS_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1816 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1817 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1818 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1819 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1820 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1821 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1822 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1823 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1824 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1825 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1826 dst = jcc(dst, cond, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1827 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1828 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1829 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1830 |
112 | 1831 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
1832 { | |
1833 uint8_t cond = inst->extra.cond; | |
1834 x86_ea dst_op; | |
1835 inst->extra.size = OPSIZE_BYTE; | |
1836 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); | |
1837 if (cond == COND_TRUE || cond == COND_FALSE) { | |
1838 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) { | |
1839 dst = cycles(dst, 6); | |
1840 } else { | |
1841 dst = cycles(dst, BUS); | |
1842 } | |
1843 if (dst_op.mode == MODE_REG_DIRECT) { | |
179
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1844 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B); |
112 | 1845 } else { |
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1846 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1847 } |
1848 } else { | |
1849 uint8_t cc = CC_NZ; | |
1850 switch (cond) | |
1851 { | |
1852 case COND_HIGH: | |
1853 cc = CC_Z; | |
1854 case COND_LOW_SAME: | |
1855 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1856 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); | |
1857 break; | |
1858 case COND_CARRY_CLR: | |
1859 cc = CC_Z; | |
1860 case COND_CARRY_SET: | |
1861 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); | |
1862 break; | |
1863 case COND_NOT_EQ: | |
1864 cc = CC_Z; | |
1865 case COND_EQ: | |
1866 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); | |
1867 break; | |
1868 case COND_OVERF_CLR: | |
1869 cc = CC_Z; | |
1870 case COND_OVERF_SET: | |
1871 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); | |
1872 break; | |
1873 case COND_PLUS: | |
1874 cc = CC_Z; | |
1875 case COND_MINUS: | |
1876 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); | |
1877 break; | |
1878 case COND_GREATER_EQ: | |
1879 cc = CC_Z; | |
1880 case COND_LESS: | |
1881 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); | |
1882 break; | |
1883 case COND_GREATER: | |
1884 cc = CC_Z; | |
1885 case COND_LESS_EQ: | |
1886 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); | |
1887 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); | |
1888 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1889 break; | |
1890 } | |
179
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1891 uint8_t *true_off = dst + 1; |
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1892 dst = jcc(dst, cc, dst+2); |
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1893 dst = cycles(dst, BUS); |
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1894 if (dst_op.mode == MODE_REG_DIRECT) { |
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
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1895 dst = mov_ir(dst, 0, dst_op.base, SZ_B); |
112 | 1896 } else { |
179
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1897 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1898 } |
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1899 uint8_t *end_off = dst+1; |
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1900 dst = jmp(dst, dst+2); |
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1901 *true_off = dst - (true_off+1); |
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1902 dst = cycles(dst, 6); |
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1903 if (dst_op.mode == MODE_REG_DIRECT) { |
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1904 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B); |
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1905 } else { |
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1906 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B); |
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1907 } |
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1908 *end_off = dst - (end_off+1); |
112 | 1909 } |
1910 dst = m68k_save_result(inst, dst, opts); | |
1911 return dst; | |
1912 } | |
1913 | |
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1914 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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1915 { |
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1916 uint8_t * dest_addr, sec_reg; |
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1917 uint32_t m68k_addr; |
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1918 switch(inst->src.addr_mode) |
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1919 { |
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1920 case MODE_AREG_INDIRECT: |
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1921 dst = cycles(dst, BUS*2); |
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1922 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1923 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1924 } else { |
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1925 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
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1926 } |
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1927 dst = call(dst, opts->native_addr); |
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1928 dst = jmp_r(dst, SCRATCH1); |
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1929 break; |
132
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1930 case MODE_AREG_INDEX_DISP8: |
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1931 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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1932 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1933 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1934 } else { |
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1935 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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1936 } |
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1937 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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1938 if (inst->src.params.regs.sec & 1) { |
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1939 //32-bit index register |
132
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1940 if (inst->src.params.regs.sec & 0x10) { |
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1941 if (opts->aregs[sec_reg] >= 0) { |
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1942 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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1943 } else { |
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1944 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1945 } |
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1946 } else { |
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1947 if (opts->dregs[sec_reg] >= 0) { |
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1948 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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1949 } else { |
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1950 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1951 } |
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1952 } |
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1953 } else { |
516
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1954 //16-bit index register |
132
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1955 if (inst->src.params.regs.sec & 0x10) { |
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1956 if (opts->aregs[sec_reg] >= 0) { |
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1957 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1958 } else { |
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1959 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1960 } |
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1961 } else { |
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1962 if (opts->dregs[sec_reg] >= 0) { |
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1963 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1964 } else { |
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1965 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1966 } |
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1967 } |
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1968 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
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1969 } |
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1970 if (inst->src.params.regs.displacement) { |
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1971 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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1972 } |
544
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1973 dst = call(dst, opts->native_addr); |
132
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1974 dst = jmp_r(dst, SCRATCH1); |
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1975 break; |
76
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1976 case MODE_PC_DISPLACE: |
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1977 dst = cycles(dst, 10); |
124
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1978 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
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1979 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
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1980 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
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1981 if (!dest_addr) { |
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1982 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
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1983 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
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1984 dest_addr = dst + 256; |
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1985 } |
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1986 dst = jmp(dst, dest_addr); |
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1987 } else { |
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1988 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
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1989 dst = call(dst, opts->native_addr); |
124
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1990 dst = jmp_r(dst, SCRATCH1); |
76
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1991 } |
71
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1992 break; |
132
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1993 case MODE_PC_INDEX_DISP8: |
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1994 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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1995 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
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1996 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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1997 if (inst->src.params.regs.sec & 1) { |
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1998 if (inst->src.params.regs.sec & 0x10) { |
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1999 if (opts->aregs[sec_reg] >= 0) { |
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2000 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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2001 } else { |
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2002 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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2003 } |
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2004 } else { |
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2005 if (opts->dregs[sec_reg] >= 0) { |
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2006 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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2007 } else { |
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2008 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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2009 } |
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2010 } |
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2011 } else { |
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2012 if (inst->src.params.regs.sec & 0x10) { |
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|
2013 if (opts->aregs[sec_reg] >= 0) { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2014 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2015 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2016 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2017 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2018 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2019 if (opts->dregs[sec_reg] >= 0) { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2020 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2021 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2022 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2023 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2024 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2025 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2026 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2027 if (inst->src.params.regs.displacement) { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2028 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2029 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2030 dst = call(dst, opts->native_addr); |
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2031 dst = jmp_r(dst, SCRATCH1); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2032 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2033 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2034 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2035 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2036 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2037 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2038 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2039 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2040 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2041 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2042 dest_addr = dst + 256; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2043 } |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2044 dst = jmp(dst, dest_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2045 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2046 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2047 dst = call(dst, opts->native_addr); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2048 dst = jmp_r(dst, SCRATCH1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2049 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2050 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2051 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2052 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2053 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode); |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
102
diff
changeset
|
2054 exit(1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2055 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2056 return dst; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2057 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2058 |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2059 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2060 { |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2061 uint8_t * dest_addr, sec_reg; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2062 uint32_t after; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2063 uint32_t m68k_addr; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2064 switch(inst->src.addr_mode) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2065 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2066 case MODE_AREG_INDIRECT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2067 dst = cycles(dst, BUS*2); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2068 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2069 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2070 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2071 dst = call(dst, opts->write_32_highfirst); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2072 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2073 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2074 } else { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2075 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2076 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2077 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2078 dst = jmp_r(dst, SCRATCH1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2079 break; |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2080 case MODE_AREG_DISPLACE: |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2081 dst = cycles(dst, BUS*2); |
187
8e138da572ab
Fix return address for areg displacement mode JSR
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
2082 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2083 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2084 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2085 dst = call(dst, opts->write_32_highfirst); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2086 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2087 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2088 } else { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2089 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2090 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2091 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2092 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2093 dst = jmp_r(dst, SCRATCH1); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2094 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2095 case MODE_AREG_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2096 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2097 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2098 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2099 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2100 dst = call(dst, opts->write_32_highfirst); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2101 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2102 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2103 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2104 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2105 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2106 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2107 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2108 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2109 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2110 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2111 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2112 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2113 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2114 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2115 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2116 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2117 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2118 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2119 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2120 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2121 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2122 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2123 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2124 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2125 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2126 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2127 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2128 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2129 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2130 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2131 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2132 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2133 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2134 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2135 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2136 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2137 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2138 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2139 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2140 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2141 dst = jmp_r(dst, SCRATCH1); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2142 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2143 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2144 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2145 dst = cycles(dst, 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2146 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2147 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2148 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2149 dst = call(dst, opts->write_32_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2150 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2151 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2152 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2153 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2154 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2155 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2156 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2157 } |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2158 dst = jmp(dst, dest_addr); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2159 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2160 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2161 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2162 dst = jmp_r(dst, SCRATCH1); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2163 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2164 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2165 case MODE_PC_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2166 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2167 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2168 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2169 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2170 dst = call(dst, opts->write_32_highfirst); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2171 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2172 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2173 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2174 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2175 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2176 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2177 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2178 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2179 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2180 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2181 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2182 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2183 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2184 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2185 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2186 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2187 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2188 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2189 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2190 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2191 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2192 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2193 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2194 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2195 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2196 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2197 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2198 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2199 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2200 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2201 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2202 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2203 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2204 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2205 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2206 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2207 dst = jmp_r(dst, SCRATCH1); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2208 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2209 case MODE_ABSOLUTE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2210 case MODE_ABSOLUTE_SHORT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2211 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2212 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2213 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2214 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2215 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2216 dst = call(dst, opts->write_32_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2217 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2218 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2219 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2220 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2221 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2222 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2223 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2224 } |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2225 dst = jmp(dst, dest_addr); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2226 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2227 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2228 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2229 dst = jmp_r(dst, SCRATCH1); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2230 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2231 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2232 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2233 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2234 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode); |
105 | 2235 exit(1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2236 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2237 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2238 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2239 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2240 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2241 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2242 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2243 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2244 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2245 dst = call(dst, opts->read_32); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2246 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2247 dst = jmp_r(dst, SCRATCH1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2248 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2249 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2250 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2251 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2252 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2253 //best case duration |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2254 dst = cycles(dst, 10); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2255 uint8_t * skip_loc = NULL; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2256 //TODO: Check if COND_TRUE technically valid here even though |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2257 //it's basically a slow NOP |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2258 if (inst->extra.cond != COND_FALSE) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2259 uint8_t cond = CC_NZ; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2260 switch (inst->extra.cond) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2261 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2262 case COND_HIGH: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2263 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2264 case COND_LOW_SAME: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2265 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2266 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2267 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2268 case COND_CARRY_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2269 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2270 case COND_CARRY_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2271 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2272 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2273 case COND_NOT_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2274 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2275 case COND_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2276 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2277 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2278 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2279 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2280 case COND_OVERF_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2281 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2282 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2283 case COND_PLUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2284 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2285 case COND_MINUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2286 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2287 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2288 case COND_GREATER_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2289 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2290 case COND_LESS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2291 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2292 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2293 case COND_GREATER: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2294 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2295 case COND_LESS_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2296 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2297 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2298 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2299 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2300 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2301 skip_loc = dst + 1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2302 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2303 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2304 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2305 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2306 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2307 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2308 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2309 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2310 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2311 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2312 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2313 uint32_t after = inst->address + 2; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2314 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2315 if (!dest_addr) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2316 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2317 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2318 dest_addr = dst + 256; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2319 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2320 dst = jmp(dst, dest_addr); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2321 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2322 if (skip_loc) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2323 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2324 *skip_loc = dst - (skip_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2325 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2326 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2327 dst = cycles(dst, 4); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2328 } |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2329 return dst; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2330 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2331 |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2332 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2333 { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2334 int8_t reg = native_reg(&(inst->src), opts); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2335 //compensate for displacement word |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2336 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2337 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2338 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2339 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2340 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2341 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2342 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2343 } |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2344 dst = call(dst, opts->write_32_highfirst); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2345 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2346 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2347 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2348 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2349 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2350 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2351 //prefetch |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2352 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2353 return dst; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2354 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2355 |
172 | 2356 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2357 { | |
2358 int8_t reg; | |
2359 dst = cycles(dst, BUS*2); | |
2360 if (inst->src.addr_mode == MODE_REG) { | |
2361 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { | |
2362 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); | |
2363 } else { | |
2364 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); | |
2365 } | |
2366 if (inst->dst.params.regs.displacement) { | |
2367 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); | |
2368 } | |
2369 reg = native_reg(&(inst->src), opts); | |
2370 if (inst->extra.size == OPSIZE_LONG) { | |
2371 if (reg >= 0) { | |
2372 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2373 dst = shr_ir(dst, 24, SCRATCH1, SZ_D); | |
2374 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2375 dst = call(dst, opts->write_8); |
172 | 2376 dst = pop_r(dst, SCRATCH2); |
2377 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2378 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2379 |
172 | 2380 } else { |
2381 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B); | |
2382 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2383 dst = call(dst, opts->write_8); |
172 | 2384 dst = pop_r(dst, SCRATCH2); |
2385 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B); | |
2386 } | |
2387 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2388 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2389 dst = call(dst, opts->write_8); |
172 | 2390 dst = pop_r(dst, SCRATCH2); |
2391 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2392 } | |
2393 if (reg >= 0) { | |
2394 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2395 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); | |
2396 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2397 dst = call(dst, opts->write_8); |
172 | 2398 dst = pop_r(dst, SCRATCH2); |
2399 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2400 } else { | |
2401 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B); | |
2402 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2403 dst = call(dst, opts->write_8); |
172 | 2404 dst = pop_r(dst, SCRATCH2); |
2405 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B); | |
2406 } | |
2407 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2408 dst = call(dst, opts->write_8); |
172 | 2409 } else { |
2410 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | |
2411 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); | |
2412 } else { | |
2413 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); | |
2414 } | |
2415 if (inst->src.params.regs.displacement) { | |
2416 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); | |
2417 } | |
2418 reg = native_reg(&(inst->dst), opts); | |
2419 if (inst->extra.size == OPSIZE_LONG) { | |
2420 if (reg >= 0) { | |
2421 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2422 dst = call(dst, opts->read_8); |
172 | 2423 dst = shl_ir(dst, 24, SCRATCH1, SZ_D); |
2424 dst = mov_rr(dst, SCRATCH1, reg, SZ_D); | |
2425 dst = pop_r(dst, SCRATCH1); | |
2426 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2427 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2428 dst = call(dst, opts->read_8); |
172 | 2429 dst = shl_ir(dst, 16, SCRATCH1, SZ_D); |
2430 dst = or_rr(dst, SCRATCH1, reg, SZ_D); | |
2431 } else { | |
2432 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2433 dst = call(dst, opts->read_8); |
172 | 2434 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B); |
2435 dst = pop_r(dst, SCRATCH1); | |
2436 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2437 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
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Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2438 dst = call(dst, opts->read_8); |
172 | 2439 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B); |
2440 } | |
2441 dst = pop_r(dst, SCRATCH1); | |
2442 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2443 } | |
2444 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2445 dst = call(dst, opts->read_8); |
172 | 2446 if (reg >= 0) { |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2447 |
172 | 2448 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
2449 dst = mov_rr(dst, SCRATCH1, reg, SZ_W); | |
2450 dst = pop_r(dst, SCRATCH1); | |
2451 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2452 dst = call(dst, opts->read_8); |
172 | 2453 dst = mov_rr(dst, SCRATCH1, reg, SZ_B); |
2454 } else { | |
2455 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B); | |
2456 dst = pop_r(dst, SCRATCH1); | |
2457 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2458 dst = call(dst, opts->read_8); |
172 | 2459 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B); |
2460 } | |
2461 } | |
2462 return dst; | |
2463 } | |
2464 | |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2465 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2466 { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2467 uint8_t size = inst->extra.size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2468 x86_ea src_op, dst_op; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2469 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2470 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2471 dst = push_r(dst, SCRATCH1); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2472 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2473 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2474 src_op.base = SCRATCH2; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2475 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2476 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2477 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2478 size = OPSIZE_LONG; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2479 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2480 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2481 dst = cycles(dst, BUS); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2482 if (src_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2483 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2484 dst = cmp_rr(dst, src_op.base, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2485 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2486 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2487 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2488 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2489 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2490 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2491 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2492 dst = cmp_ir(dst, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2493 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2494 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
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parents:
179
diff
changeset
|
2495 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2496 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2497 dst = setcc_r(dst, CC_C, FLAG_C); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2498 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2499 dst = setcc_r(dst, CC_S, FLAG_N); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2500 dst = setcc_r(dst, CC_O, FLAG_V); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2501 return dst; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2502 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2503 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2504 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2505 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2506 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2507 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2508 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2509 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2510 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2511 uint8_t * end_off = NULL; |
207 | 2512 uint8_t * nz_off = NULL; |
2513 uint8_t * z_off = NULL; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2514 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2515 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2516 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2517 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2518 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2519 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2520 if (src_op->mode == MODE_IMMED) { |
207 | 2521 if (src_op->disp != 1 && inst->op == M68K_ASL) { |
2522 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2523 for (int i = 0; i < src_op->disp; i++) { | |
2524 if (dst_op->mode == MODE_REG_DIRECT) { | |
2525 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2526 } else { | |
2527 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2528 } | |
2529 //dst = setcc_r(dst, CC_O, FLAG_V); | |
2530 dst = jcc(dst, CC_NO, dst+4); | |
2531 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2532 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2533 } else { |
207 | 2534 if (dst_op->mode == MODE_REG_DIRECT) { |
2535 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); | |
2536 } else { | |
2537 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); | |
2538 } | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
2539 dst = setcc_r(dst, CC_O, FLAG_V); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2540 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2541 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2542 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2543 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2544 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2545 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2546 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2547 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2548 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2549 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2550 dst = and_ir(dst, 63, RCX, SZ_D); |
207 | 2551 nz_off = dst+1; |
2552 dst = jcc(dst, CC_NZ, dst+2); | |
2553 //Flag behavior for shift count of 0 is different for x86 than 68K | |
2554 if (dst_op->mode == MODE_REG_DIRECT) { | |
2555 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size); | |
2556 } else { | |
2557 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2558 } | |
2559 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
2560 dst = setcc_r(dst, CC_S, FLAG_N); | |
2561 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2562 //For other instructions, this flag will be set below | |
2563 if (inst->op == M68K_ASL) { | |
2564 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2565 } | |
2566 z_off = dst+1; | |
2567 dst = jmp(dst, dst+2); | |
2568 *nz_off = dst - (nz_off + 1); | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2569 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2570 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2571 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
207 | 2572 if (inst->op == M68K_ASL) { |
2573 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB | |
2574 //Easiest way to deal with this is to shift one bit at a time | |
2575 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2576 uint8_t * loop_start = dst; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2577 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2578 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2579 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2580 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2581 } |
207 | 2582 //dst = setcc_r(dst, CC_O, FLAG_V); |
2583 dst = jcc(dst, CC_NO, dst+4); | |
2584 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2585 dst = loop(dst, loop_start); | |
2586 } else { | |
2587 //x86 shifts modulo 32 for operand sizes less than 64-bits | |
2588 //but M68K shifts modulo 64, so we need to check for large shifts here | |
2589 dst = cmp_ir(dst, 32, RCX, SZ_B); | |
2590 uint8_t * norm_shift_off = dst + 1; | |
2591 dst = jcc(dst, CC_L, dst+2); | |
2592 if (special) { | |
2593 if (inst->extra.size == OPSIZE_LONG) { | |
2594 uint8_t * neq_32_off = dst + 1; | |
2595 dst = jcc(dst, CC_NZ, dst+2); | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2596 |
207 | 2597 //set the carry bit to the lsb |
2598 if (dst_op->mode == MODE_REG_DIRECT) { | |
2599 dst = special(dst, 1, dst_op->base, SZ_D); | |
2600 } else { | |
2601 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); | |
2602 } | |
2603 dst = setcc_r(dst, CC_C, FLAG_C); | |
2604 dst = jmp(dst, dst+4); | |
2605 *neq_32_off = dst - (neq_32_off+1); | |
2606 } | |
2607 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2608 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
2609 dst = mov_ir(dst, 0, FLAG_N, SZ_B); | |
2610 if (dst_op->mode == MODE_REG_DIRECT) { | |
2611 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); | |
2612 } else { | |
2613 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2614 } | |
2615 } else { | |
2616 if (dst_op->mode == MODE_REG_DIRECT) { | |
2617 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); | |
2618 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2619 } else { | |
2620 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); | |
2621 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2622 } | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2623 |
207 | 2624 } |
2625 end_off = dst+1; | |
2626 dst = jmp(dst, dst+2); | |
2627 *norm_shift_off = dst - (norm_shift_off+1); | |
2628 if (dst_op->mode == MODE_REG_DIRECT) { | |
2629 dst = shift_clr(dst, dst_op->base, inst->extra.size); | |
2630 } else { | |
2631 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); | |
2632 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2633 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2634 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2635 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2636 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2637 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2638 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2639 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2640 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2641 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2642 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2643 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2644 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2645 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2646 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2647 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
207 | 2648 if (z_off) { |
2649 *z_off = dst - (z_off + 1); | |
2650 } | |
219
8d3c16071559
Fix overflow flag behavior for lsl/lsr/asr
Mike Pavone <pavone@retrodev.com>
parents:
218
diff
changeset
|
2651 if (inst->op != M68K_ASL) { |
207 | 2652 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
2653 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2654 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2655 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2656 } |
66 | 2657 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2658 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2659 |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2660 #define BIT_SUPERVISOR 5 |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2661 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2662 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2663 { |
122 | 2664 uint8_t * end_off, *zero_off, *norm_off; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2665 uint8_t dst_reg; |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
2666 dst = check_cycles_int(dst, inst->address, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2667 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2668 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2669 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2670 return translate_m68k_lea(dst, inst, opts); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2671 } else if(inst->op == M68K_PEA) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2672 return translate_m68k_pea(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2673 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2674 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2675 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2676 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2677 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2678 return translate_m68k_jmp(dst, inst, opts); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2679 } else if(inst->op == M68K_JSR) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2680 return translate_m68k_jsr(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2681 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2682 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2683 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2684 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2685 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2686 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2687 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2688 return translate_m68k_movem(dst, inst, opts); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2689 } else if(inst->op == M68K_LINK) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2690 return translate_m68k_link(dst, inst, opts); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2691 } else if(inst->op == M68K_EXT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2692 return translate_m68k_ext(dst, inst, opts); |
112 | 2693 } else if(inst->op == M68K_SCC) { |
2694 return translate_m68k_scc(dst, inst, opts); | |
172 | 2695 } else if(inst->op == M68K_MOVEP) { |
2696 return translate_m68k_movep(dst, inst, opts); | |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2697 } else if(inst->op == M68K_INVALID) { |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2698 if (inst->src.params.immed == 0x7100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2699 return retn(dst); |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2700 } |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2701 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D); |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2702 return call(dst, (uint8_t *)m68k_invalid); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2703 } else if(inst->op == M68K_CMP) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2704 return translate_m68k_cmp(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2705 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2706 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2707 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2708 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2709 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2710 if (inst->dst.addr_mode != MODE_UNUSED) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
2711 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2712 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2713 uint8_t size; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2714 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2715 { |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2716 case M68K_ABCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2717 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2718 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2719 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2720 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2721 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2722 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2723 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2724 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2725 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2726 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2727 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2728 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2729 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2730 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2731 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2732 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2733 dst = add_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2734 dst = call(dst, (uint8_t *)bcd_add); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2735 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2736 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2737 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2738 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2739 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2740 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2741 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2742 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2743 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2744 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2745 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2746 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2747 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2748 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2749 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2750 dst = cycles(dst, BUS); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2751 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2752 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2753 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2754 dst = add_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2755 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2756 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2757 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2758 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2759 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2760 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2761 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2762 dst = add_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2763 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2764 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2765 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2766 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2767 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2768 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2769 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2770 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2771 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2772 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2773 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2774 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2775 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2776 case M68K_ADDX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2777 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2778 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2779 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2780 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2781 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2782 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2783 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2784 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2785 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2786 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2787 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2788 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2789 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2790 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2791 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2792 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2793 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2794 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2795 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2796 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2797 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2798 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2799 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2800 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2801 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2802 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2803 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2804 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2805 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2806 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2807 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2808 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2809 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2810 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2811 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2812 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2813 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2814 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2815 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2816 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2817 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2818 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2819 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2820 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2821 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2822 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2823 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2824 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2825 case M68K_ANDI_CCR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2826 case M68K_ANDI_SR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2827 dst = cycles(dst, 20); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2828 //TODO: If ANDI to SR, trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2829 if (!(inst->src.params.immed & 0x1)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2830 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2831 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2832 if (!(inst->src.params.immed & 0x2)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2833 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2834 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2835 if (!(inst->src.params.immed & 0x4)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2836 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2837 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2838 if (!(inst->src.params.immed & 0x8)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2839 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2840 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2841 if (!(inst->src.params.immed & 0x10)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2842 dst = mov_irind(dst, 0, CONTEXT, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2843 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2844 if (inst->op == M68K_ANDI_SR) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2845 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2846 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2847 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2848 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2849 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2850 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2851 } |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2852 if (inst->src.params.immed & 0x700) { |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2853 dst = call(dst, (uint8_t *)do_sync); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2854 } |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2855 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2856 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2857 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2858 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2859 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2860 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2861 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2862 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2863 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2864 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2865 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2866 break; |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2867 case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2868 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2869 case M68K_BSET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2870 case M68K_BTST: |
457
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2871 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : ( |
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2872 inst->op == M68K_BTST ? 6 : (inst->op == M68K_BCLR ? 10 : 8)) |
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2873 ); |
67 | 2874 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2875 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2876 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2877 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2878 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2879 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2880 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2881 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2882 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2883 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2884 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2885 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2886 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2887 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2888 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2889 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2890 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2891 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2892 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2893 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2894 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2895 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2896 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2897 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2898 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2899 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2900 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2901 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2902 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2903 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2904 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != SCRATCH1 && src_op.base != SCRATCH2)) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2905 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2906 dst = push_r(dst, SCRATCH2); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2907 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2908 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2909 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2910 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2911 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2912 src_op.base = SCRATCH2; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2913 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2914 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2915 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2916 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2917 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2918 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2919 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2920 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2921 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2922 uint8_t size = inst->extra.size; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2923 if (dst_op.mode == MODE_REG_DISPLACE8) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2924 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2925 if (src_op.mode == MODE_REG_DIRECT) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2926 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2927 } else { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2928 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2929 src_op.mode = MODE_REG_DIRECT; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2930 } |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2931 src_op.base = SCRATCH1; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2932 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2933 //b### with register destination is modulo 32 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2934 //x86 with a memory destination isn't modulo anything |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2935 //so use an and here to force the value to be modulo 32 |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2936 dst = and_ir(dst, 31, SCRATCH1, SZ_D); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2937 } else if(inst->dst.addr_mode != MODE_REG) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2938 //b### with memory destination is modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2939 //x86-64 doesn't support 8-bit bit operations |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2940 //so we fake it by forcing the bit number to be modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2941 dst = and_ir(dst, 7, src_op.base, SZ_D); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2942 size = SZ_D; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2943 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2944 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2945 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2946 dst = bt_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2947 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2948 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2949 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2950 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2951 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2952 dst = bts_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2953 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2954 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2955 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2956 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2957 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2958 dst = btr_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2959 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2960 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2961 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2962 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2963 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2964 dst = btc_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2965 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2966 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2967 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2968 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2969 if (src_op.base == SCRATCH2) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2970 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2971 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2972 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2973 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2974 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2975 dst = setcc_r(dst, CC_NC, FLAG_Z); |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2976 if (inst->op != M68K_BTST) { |
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2977 dst = m68k_save_result(inst, dst, opts); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2978 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2979 break; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2980 case M68K_CHK: |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2981 { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2982 dst = cycles(dst, 6); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2983 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2984 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2985 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2986 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2987 } |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2988 uint32_t isize; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2989 switch(inst->src.addr_mode) |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2990 { |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2991 case MODE_AREG_DISPLACE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2992 case MODE_AREG_INDEX_DISP8: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2993 case MODE_ABSOLUTE_SHORT: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2994 case MODE_PC_INDEX_DISP8: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2995 case MODE_PC_DISPLACE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2996 case MODE_IMMEDIATE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2997 isize = 4; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2998 break; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2999 case MODE_ABSOLUTE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3000 isize = 6; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3001 break; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3002 default: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3003 isize = 2; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3004 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3005 uint8_t * passed = dst+1; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3006 dst = jcc(dst, CC_GE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3007 dst = mov_ir(dst, 1, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3008 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3009 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3010 dst = jmp(dst, opts->trap); |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3011 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3012 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3013 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3014 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3015 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3016 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3017 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3018 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3019 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3020 } else if(dst_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3021 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3022 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3023 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3024 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3025 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3026 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3027 passed = dst+1; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3028 dst = jcc(dst, CC_LE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3029 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3030 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3031 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3032 dst = jmp(dst, opts->trap); |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3033 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3034 dst = cycles(dst, 4); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3035 break; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3036 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3037 case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3038 case M68K_DIVU: |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3039 { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3040 //TODO: cycle exact division |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3041 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3042 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3043 dst = push_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3044 dst = push_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3045 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3046 dst = mov_rr(dst, dst_op.base, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3047 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3048 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3049 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3050 if (src_op.mode == MODE_IMMED) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3051 dst = mov_ir(dst, (src_op.disp & 0x8000) && inst->op == M68K_DIVS ? src_op.disp | 0xFFFF0000 : src_op.disp, SCRATCH2, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3052 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3053 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3054 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3055 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3056 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3057 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3058 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3059 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3060 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3061 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3062 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3063 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3064 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3065 dst = cmp_ir(dst, 0, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3066 uint8_t * not_zero = dst+1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3067 dst = jcc(dst, CC_NZ, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3068 dst = pop_r(dst, RAX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3069 dst = pop_r(dst, RDX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3070 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3071 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3072 dst = jmp(dst, opts->trap); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3073 *not_zero = dst - (not_zero+1); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3074 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3075 dst = cdq(dst); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3076 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3077 dst = xor_rr(dst, RDX, RDX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3078 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3079 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3080 dst = idiv_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3081 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3082 dst = div_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3083 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3084 uint8_t * skip_sec_check; |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3085 if (inst->op == M68K_DIVS) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3086 dst = cmp_ir(dst, 0x8000, RAX, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3087 skip_sec_check = dst + 1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3088 dst = jcc(dst, CC_GE, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3089 dst = cmp_ir(dst, -0x8000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3090 norm_off = dst+1; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3091 dst = jcc(dst, CC_L, dst+2); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3092 } else { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3093 dst = cmp_ir(dst, 0x10000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3094 norm_off = dst+1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3095 dst = jcc(dst, CC_NC, dst+2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3096 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3097 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3098 dst = mov_rr(dst, RDX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3099 dst = shl_ir(dst, 16, dst_op.base, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3100 dst = mov_rr(dst, RAX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3101 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3102 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3103 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3104 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3105 } |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3106 dst = cmp_ir(dst, 0, RAX, SZ_W); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3107 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3108 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3109 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3110 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3111 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3112 end_off = dst+1; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3113 dst = jmp(dst, dst+2); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3114 *norm_off = dst - (norm_off + 1); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3115 if (inst->op == M68K_DIVS) { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3116 *skip_sec_check = dst - (skip_sec_check+1); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3117 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3118 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3119 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3120 dst = mov_ir(dst, 1, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3121 *end_off = dst - (end_off + 1); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3122 break; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3123 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3124 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3125 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3126 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3127 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3128 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3129 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3130 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3131 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3132 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3133 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3134 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3135 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3136 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3137 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3138 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3139 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3140 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3141 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3142 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3143 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3144 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3145 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3146 break; |
171 | 3147 case M68K_EORI_CCR: |
3148 case M68K_EORI_SR: | |
3149 dst = cycles(dst, 20); | |
3150 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3151 if (inst->src.params.immed & 0x1) { | |
3152 dst = xor_ir(dst, 1, FLAG_C, SZ_B); | |
3153 } | |
3154 if (inst->src.params.immed & 0x2) { | |
3155 dst = xor_ir(dst, 1, FLAG_V, SZ_B); | |
3156 } | |
3157 if (inst->src.params.immed & 0x4) { | |
3158 dst = xor_ir(dst, 1, FLAG_Z, SZ_B); | |
3159 } | |
3160 if (inst->src.params.immed & 0x8) { | |
3161 dst = xor_ir(dst, 1, FLAG_N, SZ_B); | |
3162 } | |
3163 if (inst->src.params.immed & 0x10) { | |
3164 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B); | |
3165 } | |
3166 if (inst->op == M68K_ORI_SR) { | |
3167 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); | |
3168 if (inst->src.params.immed & 0x700) { | |
3169 dst = call(dst, (uint8_t *)do_sync); | |
3170 } | |
3171 } | |
3172 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3173 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3174 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3175 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3176 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3177 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3178 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3179 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3180 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3181 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3182 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3183 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3184 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3185 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3186 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3187 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3188 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3189 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3190 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3191 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3192 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3193 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3194 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3195 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3196 case M68K_ILLEGAL: |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
3197 dst = call(dst, opts->save_context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3198 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3199 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3200 break; |
105 | 3201 case M68K_MOVE_FROM_SR: |
3202 //TODO: Trap if not in system mode | |
3203 dst = call(dst, (uint8_t *)get_sr); | |
3204 if (dst_op.mode == MODE_REG_DIRECT) { | |
3205 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W); | |
3206 } else { | |
3207 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W); | |
3208 } | |
3209 dst = m68k_save_result(inst, dst, opts); | |
3210 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3211 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3212 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3213 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3214 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3215 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3216 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3217 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3218 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3219 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3220 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3221 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3222 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3223 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3224 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3225 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3226 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3227 } |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3228 dst = call(dst, (uint8_t *)do_sync); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3229 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3230 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3231 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3232 if (src_op.base != SCRATCH1) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3233 if (src_op.mode == MODE_REG_DIRECT) { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3234 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3235 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3236 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3237 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3238 } |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3239 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr)); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3240 dst = cycles(dst, 12); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3241 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3242 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3243 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3244 case M68K_MOVE_USP: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3245 dst = cycles(dst, BUS); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3246 //TODO: Trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3247 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3248 if (inst->src.addr_mode == MODE_UNUSED) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3249 if (dst_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3250 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3251 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3252 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3253 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3254 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3255 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3256 if (src_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3257 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3258 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3259 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3260 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3261 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3262 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3263 break; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3264 //case M68K_MOVEP: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3265 case M68K_MULS: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3266 case M68K_MULU: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3267 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3268 if (src_op.mode == MODE_IMMED) { |
223
17534fb7c4f5
Fix muls with a negative immediate source.
Mike Pavone <pavone@retrodev.com>
parents:
221
diff
changeset
|
3269 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : ((src_op.disp & 0x8000) ? src_op.disp | 0xFFFF0000 : src_op.disp), SCRATCH1, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3270 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3271 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3272 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3273 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3274 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3275 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3276 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3277 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3278 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3279 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3280 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3281 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3282 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3283 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3284 dst_reg = dst_op.base; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3285 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3286 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3287 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3288 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3289 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3290 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3291 dst_reg = SCRATCH2; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3292 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3293 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3294 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3295 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3296 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3297 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3298 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3299 if (dst_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3300 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3301 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3302 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3303 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3304 dst = cmp_ir(dst, 0, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3305 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3306 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3307 break; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3308 //case M68K_NBCD: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3309 case M68K_NEG: |
173 | 3310 dst = cycles(dst, BUS); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3311 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3312 dst = neg_r(dst, dst_op.base, inst->extra.size); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3313 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
3314 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3315 } |
173 | 3316 dst = setcc_r(dst, CC_C, FLAG_C); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3317 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3318 dst = setcc_r(dst, CC_S, FLAG_N); |
173 | 3319 dst = setcc_r(dst, CC_O, FLAG_V); |
3320 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3321 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3322 break; |
173 | 3323 case M68K_NEGX: |
3324 dst = cycles(dst, BUS); | |
3325 if (dst_op.mode == MODE_REG_DIRECT) { | |
3326 if (dst_op.base == SCRATCH1) { | |
3327 dst = push_r(dst, SCRATCH2); | |
3328 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size); | |
3329 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3330 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size); | |
3331 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size); | |
3332 dst = pop_r(dst, SCRATCH2); | |
3333 } else { | |
3334 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3335 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3336 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size); | |
3337 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size); | |
3338 } | |
3339 } else { | |
3340 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3341 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3342 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size); | |
3343 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size); | |
3344 } | |
3345 dst = setcc_r(dst, CC_C, FLAG_C); | |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3346 dst = jcc(dst, CC_Z, dst+4); |
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3347 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
173 | 3348 dst = setcc_r(dst, CC_S, FLAG_N); |
3349 dst = setcc_r(dst, CC_O, FLAG_V); | |
3350 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
3351 dst = m68k_save_result(inst, dst, opts); | |
3352 break; | |
3353 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3354 case M68K_NOP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3355 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3356 break; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3357 case M68K_NOT: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3358 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3359 dst = not_r(dst, dst_op.base, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3360 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3361 } else { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3362 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3363 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3364 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3365 |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3366 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3367 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3368 dst = setcc_r(dst, CC_S, FLAG_N); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3369 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3370 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3371 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3372 case M68K_OR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3373 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3374 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3375 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3376 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3377 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3378 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3379 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3380 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3381 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3382 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3383 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3384 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3385 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3386 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3387 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3388 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3389 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3390 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3391 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3392 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3393 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3394 break; |
106 | 3395 case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3396 case M68K_ORI_SR: |
106 | 3397 dst = cycles(dst, 20); |
3398 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3399 if (inst->src.params.immed & 0x1) { | |
3400 dst = mov_ir(dst, 1, FLAG_C, SZ_B); | |
3401 } | |
3402 if (inst->src.params.immed & 0x2) { | |
3403 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
3404 } | |
3405 if (inst->src.params.immed & 0x4) { | |
3406 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
3407 } | |
3408 if (inst->src.params.immed & 0x8) { | |
3409 dst = mov_ir(dst, 1, FLAG_N, SZ_B); | |
3410 } | |
3411 if (inst->src.params.immed & 0x10) { | |
3412 dst = mov_irind(dst, 1, CONTEXT, SZ_B); | |
3413 } | |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3414 if (inst->op == M68K_ORI_SR) { |
106 | 3415 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3416 if (inst->src.params.immed & 0x700) { |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3417 dst = call(dst, (uint8_t *)do_sync); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3418 } |
106 | 3419 } |
3420 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3421 case M68K_RESET: |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
3422 dst = call(dst, opts->save_context); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3423 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3424 dst = call(dst, (uint8_t *)print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3425 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3426 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3427 case M68K_ROR: |
122 | 3428 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
3429 if (inst->src.addr_mode == MODE_UNUSED) { | |
3430 dst = cycles(dst, BUS); | |
3431 //Memory rotate | |
3432 if (inst->op == M68K_ROL) { | |
3433 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3434 } else { | |
3435 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3436 } | |
3437 dst = setcc_r(dst, CC_C, FLAG_C); | |
3438 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3439 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3440 dst = setcc_r(dst, CC_S, FLAG_N); | |
3441 dst = m68k_save_result(inst, dst, opts); | |
3442 } else { | |
3443 if (src_op.mode == MODE_IMMED) { | |
3444 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); | |
3445 if (dst_op.mode == MODE_REG_DIRECT) { | |
3446 if (inst->op == M68K_ROL) { | |
3447 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3448 } else { | |
3449 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3450 } | |
3451 } else { | |
3452 if (inst->op == M68K_ROL) { | |
3453 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3454 } else { | |
3455 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3456 } | |
3457 } | |
3458 dst = setcc_r(dst, CC_C, FLAG_C); | |
3459 } else { | |
3460 if (src_op.mode == MODE_REG_DIRECT) { | |
3461 if (src_op.base != SCRATCH1) { | |
3462 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); | |
3463 } | |
3464 } else { | |
3465 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | |
3466 } | |
3467 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | |
3468 zero_off = dst+1; | |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3469 dst = jcc(dst, CC_Z, dst+2); |
122 | 3470 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
3471 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | |
3472 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | |
3473 norm_off = dst+1; | |
3474 dst = jcc(dst, CC_L, dst+2); | |
442
1a48b31f5316
Fix carry flag on rotate when the register provided rotate bit count is exactly 32
Mike Pavone <pavone@retrodev.com>
parents:
440
diff
changeset
|
3475 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
122 | 3476 if (dst_op.mode == MODE_REG_DIRECT) { |
3477 if (inst->op == M68K_ROL) { | |
3478 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size); | |
3479 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3480 } else { | |
3481 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size); | |
3482 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3483 } | |
3484 } else { | |
3485 if (inst->op == M68K_ROL) { | |
3486 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3487 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3488 } else { | |
3489 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3490 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3491 } | |
3492 } | |
3493 *norm_off = dst - (norm_off+1); | |
3494 if (dst_op.mode == MODE_REG_DIRECT) { | |
3495 if (inst->op == M68K_ROL) { | |
3496 dst = rol_clr(dst, dst_op.base, inst->extra.size); | |
3497 } else { | |
3498 dst = ror_clr(dst, dst_op.base, inst->extra.size); | |
3499 } | |
3500 } else { | |
3501 if (inst->op == M68K_ROL) { | |
3502 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3503 } else { | |
3504 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3505 } | |
3506 } | |
3507 dst = setcc_r(dst, CC_C, FLAG_C); | |
3508 end_off = dst + 1; | |
3509 dst = jmp(dst, dst+2); | |
3510 *zero_off = dst - (zero_off+1); | |
3511 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
3512 *end_off = dst - (end_off+1); | |
3513 } | |
3514 if (dst_op.mode == MODE_REG_DIRECT) { | |
3515 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3516 } else { | |
3517 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); | |
3518 } | |
3519 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3520 dst = setcc_r(dst, CC_S, FLAG_N); | |
3521 } | |
3522 break; | |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3523 case M68K_ROXL: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3524 case M68K_ROXR: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3525 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3526 if (inst->src.addr_mode == MODE_UNUSED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3527 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3528 //Memory rotate |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3529 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3530 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3531 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3532 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3533 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3534 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3535 dst = setcc_r(dst, CC_C, FLAG_C); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3536 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3537 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3538 dst = setcc_r(dst, CC_S, FLAG_N); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3539 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3540 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3541 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3542 if (src_op.mode == MODE_IMMED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3543 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3544 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3545 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3546 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3547 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3548 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3549 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3550 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3551 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3552 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3553 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3554 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3555 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3556 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3557 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3558 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3559 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3560 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3561 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3562 if (src_op.base != SCRATCH1) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3563 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3564 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3565 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3566 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3567 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3568 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3569 zero_off = dst+1; |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3570 dst = jcc(dst, CC_Z, dst+2); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3571 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3572 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3573 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3574 norm_off = dst+1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3575 dst = jcc(dst, CC_L, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3576 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3577 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3578 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3579 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3580 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3581 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3582 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3583 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3584 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3585 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3586 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3587 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3588 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3589 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3590 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3591 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3592 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3593 } |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3594 dst = setcc_rind(dst, CC_C, CONTEXT); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3595 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3596 *norm_off = dst - (norm_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3597 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3598 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3599 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3600 dst = rcl_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3601 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3602 dst = rcr_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3603 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3604 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3605 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3606 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3607 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3608 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3609 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3610 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3611 dst = setcc_r(dst, CC_C, FLAG_C); |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3612 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3613 end_off = dst + 1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3614 dst = jmp(dst, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3615 *zero_off = dst - (zero_off+1); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3616 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3617 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3618 *end_off = dst - (end_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3619 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3620 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3621 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3622 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3623 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3624 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3625 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3626 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3627 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3628 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3629 case M68K_RTE: |
170 | 3630 //TODO: Trap if not in system mode |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3631 //Read saved SR |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3632 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3633 dst = call(dst, opts->read_16); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3634 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3635 dst = call(dst, (uint8_t *)set_sr); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3636 //Read saved PC |
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3637 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3638 dst = call(dst, opts->read_32); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3639 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3640 //Check if we've switched to user mode and swap stack pointers if needed |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3641 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3642 end_off = dst+1; |
121
f848aad2abef
Fix logic for switching between USP and SSP
Mike Pavone <pavone@retrodev.com>
parents:
119
diff
changeset
|
3643 dst = jcc(dst, CC_C, dst+2); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3644 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3645 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3646 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3647 *end_off = dst - (end_off+1); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3648 //Get native address, sync components, recalculate integer points and jump to returned address |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
3649 dst = call(dst, opts->native_addr_and_sync); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3650 dst = jmp_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3651 break; |
170 | 3652 case M68K_RTR: |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3653 //Read saved CCR |
170 | 3654 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3655 dst = call(dst, opts->read_16); |
170 | 3656 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
3657 dst = call(dst, (uint8_t *)set_ccr); | |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3658 //Read saved PC |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3659 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3660 dst = call(dst, opts->read_32); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3661 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3662 //Get native address and jump to it |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
3663 dst = call(dst, opts->native_addr); |
170 | 3664 dst = jmp_r(dst, SCRATCH1); |
3665 break; | |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3666 case M68K_SBCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3667 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3668 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3669 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3670 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3671 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3672 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3673 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3674 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3675 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3676 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3677 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3678 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3679 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3680 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3681 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3682 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3683 dst = sub_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3684 dst = call(dst, (uint8_t *)bcd_sub); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3685 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3686 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3687 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3688 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3689 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3690 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3691 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3692 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3693 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3694 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3695 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3696 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3697 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3698 break; |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3699 case M68K_STOP: { |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3700 //TODO: Trap if not in system mode |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3701 //manual says 4 cycles, but it has to be at least 8 since it's a 2-word instruction |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3702 //possibly even 12 since that's how long MOVE to SR takes |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3703 dst = cycles(dst, BUS*2); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3704 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3705 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3706 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3707 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3708 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3709 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3710 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3711 //leave supervisor mode |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3712 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3713 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3714 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3715 } |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3716 uint8_t * loop_top = dst; |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3717 dst = call(dst, (uint8_t *)do_sync); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3718 dst = cmp_rr(dst, LIMIT, CYCLES, SZ_D); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3719 uint8_t * normal_cycle_up = dst + 1; |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3720 dst = jcc(dst, CC_A, dst+2); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3721 dst = cycles(dst, BUS); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3722 uint8_t * after_cycle_up = dst + 1; |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3723 dst = jmp(dst, dst+2); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3724 *normal_cycle_up = dst - (normal_cycle_up + 1); |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3725 dst = mov_rr(dst, LIMIT, CYCLES, SZ_D); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3726 *after_cycle_up = dst - (after_cycle_up+1); |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3727 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3728 dst = jcc(dst, CC_C, loop_top); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3729 break; |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3730 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3731 case M68K_SUB: |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3732 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3733 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3734 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3735 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3736 dst = sub_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3737 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3738 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3739 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3740 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3741 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3742 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3743 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3744 dst = sub_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3745 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3746 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3747 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3748 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3749 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3750 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3751 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3752 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3753 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3754 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3755 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3756 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3757 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3758 case M68K_SUBX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3759 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3760 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3761 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3762 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3763 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3764 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3765 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3766 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3767 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3768 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3769 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3770 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3771 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3772 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3773 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3774 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3775 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3776 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3777 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3778 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3779 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3780 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3781 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3782 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3783 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3784 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3785 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3786 if (src_op.mode == MODE_REG_DIRECT) { |
129 | 3787 dst = rol_ir(dst, 16, src_op.base, SZ_D); |
443 | 3788 dst = cmp_ir(dst, 0, src_op.base, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3789 } else{ |
129 | 3790 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D); |
443 | 3791 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3792 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3793 |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3794 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3795 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3796 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3797 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3798 break; |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3799 //case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3800 case M68K_TRAP: |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3801 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
182
diff
changeset
|
3802 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3803 dst = jmp(dst, opts->trap); |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3804 break; |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3805 //case M68K_TRAPV: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3806 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3807 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3808 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3809 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3810 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3811 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3812 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3813 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3814 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3815 dst = setcc_r(dst, CC_S, FLAG_N); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3816 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3817 break; |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3818 case M68K_UNLK: |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3819 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3820 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3821 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3822 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3823 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3824 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3825 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3826 dst = call(dst, opts->read_32); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3827 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3828 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3829 } else { |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3830 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3831 } |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3832 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3833 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3834 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3835 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3836 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op); |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3837 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3838 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3839 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3840 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3841 |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3842 uint8_t m68k_is_terminal(m68kinst * inst) |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3843 { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3844 return inst->op == M68K_RTS || inst->op == M68K_RTE || inst->op == M68K_RTR || inst->op == M68K_JMP |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3845 || inst->op == M68K_TRAP || inst->op == M68K_ILLEGAL || inst->op == M68K_INVALID || inst->op == M68K_RESET |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3846 || (inst->op == M68K_BCC && inst->extra.cond == COND_TRUE); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3847 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3848 |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3849 void m68k_handle_deferred(m68k_context * context) |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3850 { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3851 x86_68k_options * opts = context->options; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3852 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3853 if (opts->deferred) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3854 translate_m68k_stream(opts->deferred->address, context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3855 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3856 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3857 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3858 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3859 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3860 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3861 x86_68k_options * opts = context->options; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3862 uint8_t * dst = opts->cur_code; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3863 uint8_t * dst_end = opts->code_end; |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
3864 address &= 0xFFFFFF; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3865 if(get_native_address(opts->native_code_map, address)) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3866 return dst; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3867 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3868 char disbuf[1024]; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3869 uint16_t *encoded, *next; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3870 if ((address & 0xFFFFFF) < 0x400000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3871 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3872 } else if ((address & 0xFFFFFF) > 0xE00000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3873 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3874 } else { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3875 printf("attempt to translate non-memory address: %X\n", address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3876 exit(1); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3877 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3878 do { |
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3879 if (opts->address_log) { |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3880 fprintf(opts->address_log, "%X\n", address); |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3881 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3882 do { |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3883 if (dst_end-dst < MAX_NATIVE_SIZE) { |
102
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3884 if (dst_end-dst < 5) { |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3885 puts("out of code memory, not enough space for jmp to next chunk"); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3886 exit(1); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3887 } |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3888 size_t size = 1024*1024; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3889 opts->cur_code = alloc_code(&size); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3890 opts->code_end = opts->cur_code + size; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3891 jmp(dst, opts->cur_code); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3892 dst = opts->cur_code; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3893 dst_end = opts->code_end; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3894 } |
159
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3895 if (address >= 0x400000 && address < 0xE00000) { |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3896 dst = xor_rr(dst, RDI, RDI, SZ_D); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3897 dst = call(dst, (uint8_t *)exit); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3898 break; |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3899 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3900 uint8_t * existing = get_native_address(opts->native_code_map, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3901 if (existing) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3902 dst = jmp(dst, existing); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3903 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3904 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3905 next = m68k_decode(encoded, &instbuf, address); |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3906 if (instbuf.op == M68K_INVALID) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3907 instbuf.src.params.immed = *encoded; |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3908 } |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3909 uint16_t m68k_size = (next-encoded)*2; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3910 address += m68k_size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3911 encoded = next; |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3912 //m68k_disasm(&instbuf, disbuf); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3913 //printf("%X: %s\n", instbuf.address, disbuf); |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3914 uint8_t * after = translate_m68k(dst, &instbuf, opts); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3915 map_native_address(context, instbuf.address, dst, m68k_size, after-dst); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3916 dst = after; |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3917 } while(!m68k_is_terminal(&instbuf)); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
3918 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3919 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3920 address = opts->deferred->address; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3921 if ((address & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3922 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3923 } else if ((address & 0xFFFFFF) > 0xE00000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3924 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3925 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3926 printf("attempt to translate non-memory address: %X\n", address); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3927 exit(1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3928 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3929 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3930 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3931 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3932 } while(encoded != NULL); |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3933 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3934 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3935 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3936 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3937 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address) |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3938 { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3939 address &= 0xFFFFFF; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3940 uint8_t * ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3941 if (!ret) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3942 translate_m68k_stream(address, context); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3943 ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3944 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3945 return ret; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3946 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3947 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3948 void * m68k_retranslate_inst(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3949 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3950 x86_68k_options * opts = context->options; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3951 uint8_t orig_size = get_native_inst_size(opts, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3952 uint8_t * orig_start = get_native_address(context->native_code_map, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3953 uint32_t orig = address; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3954 address &= 0xFFFF; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3955 uint8_t * dst = opts->cur_code; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3956 uint8_t * dst_end = opts->code_end; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3957 uint16_t *after, *inst = context->mem_pointers[1] + address/2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3958 m68kinst instbuf; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3959 after = m68k_decode(inst, &instbuf, orig); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3960 if (orig_size != MAX_NATIVE_SIZE) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3961 if (dst_end - dst < 128) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3962 size_t size = 1024*1024; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3963 dst = alloc_code(&size); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3964 opts->code_end = dst_end = dst + size; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3965 opts->cur_code = dst; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3966 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3967 deferred_addr * orig_deferred = opts->deferred; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3968 uint8_t * native_end = translate_m68k(dst, &instbuf, opts); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3969 uint8_t is_terminal = m68k_is_terminal(&instbuf); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3970 if ((native_end - dst) <= orig_size) { |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3971 uint8_t * native_next; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3972 if (!is_terminal) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3973 native_next = get_native_address(context->native_code_map, orig + (after-inst)*2); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3974 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3975 if (is_terminal || (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5))) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3976 remove_deferred_until(&opts->deferred, orig_deferred); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3977 native_end = translate_m68k(orig_start, &instbuf, opts); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3978 if (!is_terminal) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3979 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3980 while (native_end < orig_start + orig_size) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3981 *(native_end++) = 0x90; //NOP |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3982 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3983 } else { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3984 jmp(native_end, native_next); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3985 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3986 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3987 m68k_handle_deferred(context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3988 return orig_start; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3989 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3990 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3991 |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3992 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3993 opts->cur_code = dst+MAX_NATIVE_SIZE; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3994 jmp(orig_start, dst); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3995 if (!m68k_is_terminal(&instbuf)) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3996 jmp(native_end, get_native_address_trans(context, orig + (after-inst)*2)); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3997 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3998 m68k_handle_deferred(context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3999 return dst; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4000 } else { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4001 dst = translate_m68k(orig_start, &instbuf, opts); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4002 if (!m68k_is_terminal(&instbuf)) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4003 dst = jmp(dst, get_native_address_trans(context, orig + (after-inst)*2)); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4004 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4005 m68k_handle_deferred(context); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4006 return orig_start; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4007 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4008 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4009 |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4010 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4011 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4012 uint32_t inst_start = get_instruction_start(context->native_code_map, address | 0xFF0000); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4013 if (inst_start) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4014 uint8_t * dst = get_native_address(context->native_code_map, inst_start); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4015 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D); |
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4016 x86_68k_options * options = context->options; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4017 if (!options->retrans_stub) { |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4018 if (options->code_end - options->cur_code < 32) { |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4019 size_t size = 1024*1024; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4020 options->cur_code = alloc_code(&size); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4021 options->code_end = options->cur_code + size; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4022 } |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4023 uint8_t * rdst = options->retrans_stub = options->cur_code; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4024 rdst = call(rdst, options->save_context); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4025 rdst = push_r(rdst, CONTEXT); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4026 rdst = call(rdst, (uint8_t *)m68k_retranslate_inst); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4027 rdst = pop_r(rdst, CONTEXT); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4028 rdst = mov_rr(rdst, RAX, SCRATCH1, SZ_Q); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4029 rdst = call(rdst, options->load_context); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4030 rdst = jmp_r(rdst, SCRATCH1); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4031 options->cur_code = rdst; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4032 } |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4033 dst = jmp(dst, options->retrans_stub); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4034 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4035 return context; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4036 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4037 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4038 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4039 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4040 static uint8_t * bp_stub = NULL; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4041 uint8_t * native = get_native_address_trans(context, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4042 uint8_t * start_native = native; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4043 native = mov_ir(native, address, SCRATCH1, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4044 if (!bp_stub) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4045 x86_68k_options * opts = context->options; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4046 uint8_t * dst = opts->cur_code; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4047 uint8_t * dst_end = opts->code_end; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4048 if (dst_end - dst < 128) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4049 size_t size = 1024*1024; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4050 dst = alloc_code(&size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4051 opts->code_end = dst_end = dst + size; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4052 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4053 bp_stub = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4054 native = call(native, bp_stub); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4055 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4056 //Calculate length of prologue |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4057 dst = check_cycles_int(dst, address, opts); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4058 int check_int_size = dst-bp_stub; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4059 dst = bp_stub; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4060 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4061 //Save context and call breakpoint handler |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4062 dst = call(dst, opts->save_context); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4063 dst = push_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4064 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4065 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4066 dst = call(dst, bp_handler); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4067 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4068 //Restore context |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4069 dst = call(dst, opts->load_context); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4070 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4071 //do prologue stuff |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4072 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4073 uint8_t * jmp_off = dst+1; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4074 dst = jcc(dst, CC_NC, dst + 7); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4075 dst = call(dst, opts->handle_cycle_limit_int); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4076 *jmp_off = dst - (jmp_off+1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4077 //jump back to body of translated instruction |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4078 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4079 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4080 dst = jmp_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4081 opts->cur_code = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4082 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4083 native = call(native, bp_stub); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4084 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4085 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4086 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4087 void remove_breakpoint(m68k_context * context, uint32_t address) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4088 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4089 uint8_t * native = get_native_address(context->native_code_map, address); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4090 check_cycles_int(native, address, context->options); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4091 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4092 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4093 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4094 { |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
423
diff
changeset
|
4095 uint8_t * addr = get_native_address_trans(context, address); |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4096 x86_68k_options * options = context->options; |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4097 options->start_context(addr, context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4098 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4099 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4100 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4101 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4102 //TODO: Make this actually use the normal read functions |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4103 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4104 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4105 start_68k_context(context, address); |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4106 } |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4107 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4108 typedef enum { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4109 READ_16, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4110 READ_8, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4111 WRITE_16, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4112 WRITE_8 |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4113 } ftype; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4114 |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4115 uint8_t * gen_mem_fun(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4116 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4117 uint8_t * dst = opts->cur_code; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4118 uint8_t * start = dst; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4119 dst = check_cycles(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4120 dst = cycles(dst, BUS); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4121 dst = and_ir(dst, 0xFFFFFF, SCRATCH1, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4122 uint8_t *lb_jcc = NULL, *ub_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4123 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4124 uint8_t adr_reg = is_write ? SCRATCH2 : SCRATCH1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4125 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4126 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4127 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4128 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4129 if (memmap[chunk].start > 0) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4130 dst = cmp_ir(dst, memmap[chunk].start, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4131 lb_jcc = dst + 1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4132 dst = jcc(dst, CC_C, dst+2); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4133 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4134 if (memmap[chunk].end < 0x1000000) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4135 dst = cmp_ir(dst, memmap[chunk].end, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4136 ub_jcc = dst + 1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4137 dst = jcc(dst, CC_NC, dst+2); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4138 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4139 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4140 if (memmap[chunk].mask != 0xFFFFFF) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4141 dst = and_ir(dst, memmap[chunk].mask, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4142 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4143 void * cfun; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4144 switch (fun_type) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4145 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4146 case READ_16: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4147 cfun = memmap[chunk].read_16; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4148 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4149 case READ_8: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4150 cfun = memmap[chunk].read_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4151 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4152 case WRITE_16: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4153 cfun = memmap[chunk].write_16; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4154 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4155 case WRITE_8: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4156 cfun = memmap[chunk].write_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4157 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4158 default: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4159 cfun = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4160 } |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4161 if(memmap[chunk].buffer && memmap[chunk].flags & access_flag) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4162 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4163 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4164 dst = cmp_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4165 uint8_t * not_null = dst+1; |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4166 dst = jcc(dst, CC_NZ, dst+2); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4167 dst = call(dst, opts->save_context); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4168 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4169 //SCRATCH2 is RDI, so no need to move it there |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4170 dst = mov_rr(dst, SCRATCH1, RDX, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4171 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4172 dst = push_r(dst, CONTEXT); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4173 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4174 } |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4175 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4176 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4177 dst = jcc(dst, CC_NZ, dst+2); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4178 dst = call(dst, cfun); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4179 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4180 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4181 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4182 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4183 dst = call(dst, cfun); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4184 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4185 *no_adjust = dst - (no_adjust + 1); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4186 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4187 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4188 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4189 dst = pop_r(dst, CONTEXT); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4190 dst = mov_rr(dst, RAX, SCRATCH1, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4191 } |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4192 dst = jmp(dst, opts->load_context); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4193 |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4194 *not_null = dst - (not_null + 1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4195 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4196 if (size == SZ_B) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4197 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4198 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4199 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4200 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4201 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, size); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4202 |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4203 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4204 dst = mov_rindr(dst, SCRATCH1, SCRATCH1, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4205 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4206 } else { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4207 uint8_t tmp_size = size; |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4208 if (size == SZ_B) { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4209 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4210 dst = bt_ir(dst, 0, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4211 uint8_t * good_addr = dst + 1; |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4212 dst = jcc(dst, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, dst+2); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4213 if (!is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4214 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4215 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4216 dst = retn(dst); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4217 *good_addr = dst - (good_addr + 1); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4218 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4219 } else { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4220 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4221 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4222 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4223 tmp_size = SZ_B; |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4224 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4225 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4226 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4227 } |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4228 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4229 if ((int64_t)memmap[chunk].buffer <= 0x7FFFFFFF && (int64_t)memmap[chunk].buffer >= -2147483648) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4230 if (is_write) { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4231 dst = mov_rrdisp32(dst, SCRATCH1, SCRATCH2, (int64_t)memmap[chunk].buffer, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4232 } else { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4233 dst = mov_rdisp32r(dst, SCRATCH1, (int64_t)memmap[chunk].buffer, SCRATCH1, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4234 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4235 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4236 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4237 dst = push_r(dst, SCRATCH1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4238 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH1, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4239 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4240 dst = pop_r(dst, SCRATCH1); |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4241 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4242 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4243 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH2, SZ_Q); |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4244 dst = mov_rindexr(dst, SCRATCH2, SCRATCH1, 1, SCRATCH1, tmp_size); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4245 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4246 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4247 if (size != tmp_size && !is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4248 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4249 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4250 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4251 } else { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4252 dst = or_ir(dst, 0xFF00, SCRATCH1, SZ_W); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4253 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4254 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4255 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4256 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4257 dst = mov_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4258 dst = shr_ir(dst, 11, SCRATCH1, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4259 dst = bt_rrdisp32(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, ram_code_flags), SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4260 uint8_t * not_code = dst+1; |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4261 dst = jcc(dst, CC_NC, dst+2); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4262 dst = call(dst, opts->save_context); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4263 dst = call(dst, (uint8_t *)m68k_handle_code_write); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4264 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4265 dst = call(dst, opts->load_context); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4266 *not_code = dst - (not_code+1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4267 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4268 dst = retn(dst); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4269 } else if (cfun) { |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4270 dst = call(dst, opts->save_context); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4271 if (is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4272 //SCRATCH2 is RDI, so no need to move it there |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4273 dst = mov_rr(dst, SCRATCH1, RDX, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4274 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4275 dst = push_r(dst, CONTEXT); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4276 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4277 } |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4278 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4279 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4280 dst = jcc(dst, CC_NZ, dst+2); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4281 dst = call(dst, cfun); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4282 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4283 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4284 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4285 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4286 dst = call(dst, cfun); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4287 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4288 *no_adjust = dst - (no_adjust+1); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4289 if (is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4290 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4291 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4292 dst = pop_r(dst, CONTEXT); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4293 dst = mov_rr(dst, RAX, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4294 } |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4295 dst = jmp(dst, opts->load_context); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4296 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4297 //Not sure the best course of action here |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4298 if (!is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4299 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4300 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4301 dst = retn(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4302 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4303 if (lb_jcc) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4304 *lb_jcc = dst - (lb_jcc+1); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4305 lb_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4306 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4307 if (ub_jcc) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4308 *ub_jcc = dst - (ub_jcc+1); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4309 ub_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4310 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4311 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4312 if (!is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4313 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4314 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4315 dst = retn(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4316 opts->cur_code = dst; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4317 return start; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4318 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4319 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4320 void init_x86_68k_opts(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4321 { |
440 | 4322 memset(opts, 0, sizeof(*opts)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4323 for (int i = 0; i < 8; i++) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4324 opts->dregs[i] = opts->aregs[i] = -1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4325 opts->dregs[0] = R10; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4326 opts->dregs[1] = R11; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4327 opts->dregs[2] = R12; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4328 opts->dregs[3] = R8; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4329 opts->aregs[0] = R13; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4330 opts->aregs[1] = R14; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4331 opts->aregs[2] = R9; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4332 opts->aregs[7] = R15; |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4333 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4334 opts->flag_regs[0] = -1; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4335 opts->flag_regs[1] = RBX; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4336 opts->flag_regs[2] = RDX; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4337 opts->flag_regs[3] = BH; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4338 opts->flag_regs[4] = DH; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4339 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4340 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4341 opts->deferred = NULL; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4342 size_t size = 1024 * 1024; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4343 opts->cur_code = alloc_code(&size); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4344 opts->code_end = opts->cur_code + size; |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4345 opts->ram_inst_sizes = malloc(sizeof(uint8_t *) * 64); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4346 memset(opts->ram_inst_sizes, 0, sizeof(uint8_t *) * 64); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4347 |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4348 uint8_t * dst = opts->cur_code; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4349 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4350 opts->save_context = dst; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4351 for (int i = 0; i < 5; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4352 if (opts->flag_regs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4353 dst = mov_rrdisp8(dst, opts->flag_regs[i], CONTEXT, offsetof(m68k_context, flags) + i, SZ_B); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4354 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4355 for (int i = 0; i < 8; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4356 { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4357 if (opts->dregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4358 dst = mov_rrdisp8(dst, opts->dregs[i], CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4359 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4360 if (opts->aregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4361 dst = mov_rrdisp8(dst, opts->aregs[i], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4362 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4363 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4364 dst = mov_rrdisp8(dst, CYCLES, CONTEXT, offsetof(m68k_context, current_cycle), SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4365 dst = retn(dst); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4366 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4367 opts->load_context = dst; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4368 for (int i = 0; i < 5; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4369 if (opts->flag_regs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4370 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + i, opts->flag_regs[i], SZ_B); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4371 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4372 for (int i = 0; i < 8; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4373 { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4374 if (opts->dregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4375 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, opts->dregs[i], SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4376 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4377 if (opts->aregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4378 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, opts->aregs[i], SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4379 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4380 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4381 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, current_cycle), CYCLES, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4382 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, target_cycle), LIMIT, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4383 dst = retn(dst); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4384 |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4385 opts->start_context = (start_fun)dst; |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4386 //save callee save registers |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4387 dst = push_r(dst, RBP); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4388 dst = push_r(dst, R12); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4389 dst = push_r(dst, R13); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4390 dst = push_r(dst, R14); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4391 dst = push_r(dst, R15); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4392 dst = call(dst, opts->load_context); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4393 dst = call_r(dst, RDI); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4394 dst = call(dst, opts->save_context); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4395 //restore callee save registers |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4396 dst = pop_r(dst, R15); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4397 dst = pop_r(dst, R14); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4398 dst = pop_r(dst, R13); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4399 dst = pop_r(dst, R12); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4400 dst = pop_r(dst, RBP); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4401 dst = retn(dst); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4402 |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4403 opts->native_addr = dst; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4404 dst = call(dst, opts->save_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4405 dst = push_r(dst, CONTEXT); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4406 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); //move context to 1st arg reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4407 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); //move address to 2nd arg reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4408 dst = call(dst, (uint8_t *)get_native_address_trans); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4409 dst = mov_rr(dst, RAX, SCRATCH1, SZ_Q); //move result to scratch reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4410 dst = pop_r(dst, CONTEXT); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4411 dst = call(dst, opts->load_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4412 dst = retn(dst); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4413 |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4414 opts->native_addr_and_sync = dst; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4415 dst = call(dst, opts->save_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4416 dst = push_r(dst, SCRATCH1); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4417 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4418 dst = xor_rr(dst, RSI, RSI, SZ_D); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4419 dst = test_ir(dst, 8, RSP, SZ_Q); //check stack alignment |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4420 uint8_t * do_adjust_rsp = dst+1; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4421 dst = jcc(dst, CC_NZ, dst+2); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4422 dst = call(dst, (uint8_t *)sync_components); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4423 uint8_t * no_adjust_rsp = dst+1; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4424 dst = jmp(dst, dst+2); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4425 *do_adjust_rsp = dst - (do_adjust_rsp+1); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4426 dst = sub_ir(dst, 8, RSP, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4427 dst = call(dst, (uint8_t *)sync_components); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4428 dst = add_ir(dst, 8, RSP, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4429 *no_adjust_rsp = dst - (no_adjust_rsp+1); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4430 dst = pop_r(dst, RSI); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4431 dst = push_r(dst, RAX); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4432 dst = mov_rr(dst, RAX, RDI, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4433 dst = call(dst, (uint8_t *)get_native_address_trans); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4434 dst = mov_rr(dst, RAX, SCRATCH1, SZ_Q); //move result to scratch reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4435 dst = pop_r(dst, CONTEXT); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4436 dst = call(dst, opts->load_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4437 dst = retn(dst); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4438 |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4439 opts->cur_code = dst; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4440 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4441 opts->read_16 = gen_mem_fun(opts, memmap, num_chunks, READ_16); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4442 opts->read_8 = gen_mem_fun(opts, memmap, num_chunks, READ_8); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4443 opts->write_16 = gen_mem_fun(opts, memmap, num_chunks, WRITE_16); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4444 opts->write_8 = gen_mem_fun(opts, memmap, num_chunks, WRITE_8); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4445 |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4446 dst = opts->cur_code; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4447 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4448 opts->read_32 = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4449 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4450 dst = call(dst, opts->read_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4451 dst = mov_rr(dst, SCRATCH1, SCRATCH2, SZ_W); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4452 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4453 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4454 dst = add_ir(dst, 2, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4455 dst = call(dst, opts->read_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4456 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4457 dst = movzx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4458 dst = shl_ir(dst, 16, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4459 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4460 dst = retn(dst); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4461 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4462 opts->write_32_lowfirst = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4463 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4464 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4465 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4466 dst = call(dst, opts->write_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4467 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4468 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4469 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4470 dst = jmp(dst, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4471 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4472 opts->write_32_highfirst = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4473 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4474 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4475 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4476 dst = call(dst, opts->write_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4477 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4478 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4479 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4480 dst = jmp(dst, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4481 |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4482 opts->handle_cycle_limit_int = dst; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4483 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4484 uint8_t * do_int = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4485 dst = jcc(dst, CC_NC, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4486 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4487 uint8_t * skip_sync = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4488 dst = jcc(dst, CC_C, dst+2); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4489 dst = call(dst, opts->save_context); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4490 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4491 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4492 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4493 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4494 dst = jcc(dst, CC_NZ, dst+2); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4495 dst = call(dst, (uint8_t *)sync_components); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4496 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4497 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4498 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4499 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4500 dst = call(dst, (uint8_t *)sync_components); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4501 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4502 *no_adjust = dst - (no_adjust+1); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4503 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4504 dst = jmp(dst, opts->load_context); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4505 *skip_sync = dst - (skip_sync+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4506 dst = retn(dst); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4507 *do_int = dst - (do_int+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4508 //set target cycle to sync cycle |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4509 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), LIMIT, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4510 //swap USP and SSP if not already in supervisor mode |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4511 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4512 uint8_t *already_supervisor = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4513 dst = jcc(dst, CC_C, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4514 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4515 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4516 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4517 *already_supervisor = dst - (already_supervisor+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4518 //save PC |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4519 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4520 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4521 dst = call(dst, opts->write_32_lowfirst); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4522 //save status register |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4523 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4524 dst = call(dst, (uint8_t *)get_sr); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4525 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4526 dst = call(dst, opts->write_16); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4527 //update status register |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4528 dst = and_irdisp8(dst, 0xF8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4529 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4530 dst = or_ir(dst, 0x20, SCRATCH1, SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4531 dst = or_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4532 //calculate interrupt vector address |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4533 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4534 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, int_ack), SZ_W); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4535 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4536 dst = add_ir(dst, 0x60, SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4537 dst = call(dst, opts->read_32); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4538 dst = call(dst, opts->native_addr_and_sync); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4539 dst = cycles(dst, 24); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4540 //discard function return address |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4541 dst = pop_r(dst, SCRATCH2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4542 dst = jmp_r(dst, SCRATCH1); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4543 |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4544 opts->trap = dst; |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4545 dst = push_r(dst, SCRATCH2); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4546 //swap USP and SSP if not already in supervisor mode |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4547 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4548 already_supervisor = dst+1; |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4549 dst = jcc(dst, CC_C, dst+2); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4550 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4551 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4552 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4553 *already_supervisor = dst - (already_supervisor+1); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4554 //save PC |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4555 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4556 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4557 dst = call(dst, opts->write_32_lowfirst); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4558 //save status register |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4559 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4560 dst = call(dst, (uint8_t *)get_sr); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4561 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4562 dst = call(dst, opts->write_16); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4563 //set supervisor bit |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
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347
diff
changeset
|
4564 dst = or_irdisp8(dst, 0x20, CONTEXT, offsetof(m68k_context, status), SZ_B); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
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347
diff
changeset
|
4565 //calculate vector address |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4566 dst = pop_r(dst, SCRATCH1); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4567 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4568 dst = call(dst, opts->read_32); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4569 dst = call(dst, opts->native_addr_and_sync); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
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347
diff
changeset
|
4570 dst = cycles(dst, 18); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4571 dst = jmp_r(dst, SCRATCH1); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4572 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4573 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4574 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4575 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4576 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4577 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4578 memset(context, 0, sizeof(m68k_context)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4579 context->native_code_map = native_code_map; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4580 context->options = opts; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
4581 context->int_cycle = 0xFFFFFFFF; |
167
f6c7fea1ecf7
Initialize status register to proper value on startup
Mike Pavone <pavone@retrodev.com>
parents:
165
diff
changeset
|
4582 context->status = 0x27; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4583 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4584 |