repos/blastem: cpu_dsl.py annotate

annotate cpu_dsl.py @ 2585:c730067d5f77

Fix jsr in new CPU core

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 08 Feb 2025 16:37:15 -0800
parents	9e10149c9e10
children	e04c7e753bf6

rev	line source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	3 assignmentOps = {
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	4 '=': 'mov',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	5 '+=': 'add',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	6 '-=': 'sub',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	7 '<<=': 'lsl',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	8 '>>=': 'lsr',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	9 '&=': 'and',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	10 '\|=': 'or',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	11 '^=': 'xor'
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	12 }
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	13 binaryOps = {
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	14 '+': 'add',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	15 '-': 'sub',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	16 '<<': 'lsl',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	17 '>>': 'lsr',
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	18 '*': 'mulu',
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	19 '*S': 'muls',
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	20 '&': 'and',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	21 '\|': 'or',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	22 '^': 'xor'
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	23 }
2443 461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	24 unaryOps = {
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	25 '~': 'not',
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	26 '!': 'lnot',
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	27 '-': 'neg'
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	28 }
2442 52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	29 compareOps = {'>=U', '=', '!='}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	30 class Block:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 if parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 o = Switch(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39 elif parts[0] == 'if':
2442 52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	40 if len(parts) == 4 and parts[2] in compareOps:
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	41 self.addOp(NormalOp(['cmp', parts[3], parts[1]]))
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	42 cond = parts[2]
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	43 else:
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	44 cond = parts[1]
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	45 o = If(self, cond)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	48 elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	49 raise Exception('end is only allowed inside a switch or if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	50 else:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	51 if len(parts) > 1 and parts[1] in assignmentOps:
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	52 dst = parts[0]
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	53 dst,_,size = dst.partition(':')
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	54 op = parts[1]
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	55 parts = [assignmentOps[op]] + parts[2:]
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	56 if op == '=':
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	57 if len(parts) > 2 and parts[2] in binaryOps:
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	58 op = parts[2]
2478 ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	59 if op == '-':
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	60 tmp = parts[1]
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	61 parts[1] = parts[3]
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	62 parts[3] = tmp
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	63 parts[0] = binaryOps[op]
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	64 del parts[2]
2443 461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	65 elif len(parts) > 1 and parts[1][0] in unaryOps:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	66 rest = parts[1][1:]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	67 op = parts[1][0]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	68 if rest:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	69 parts[1] = rest
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	70 else:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	71 del parts[1]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	72 parts[0] = unaryOps[op]
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	73 else:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	74 if op == '<<=' or op == '>>=':
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	75 parts.insert(1, dst)
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	76 else:
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	77 parts.append(dst)
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	78 parts.append(dst)
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	79 if size:
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	80 parts.append(size)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	81 self.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	82 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	83
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	84 def processOps(self, prog, fieldVals, output, otype, oplist):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	85 for i in range(0, len(oplist)):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	86 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	87 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0])
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	88 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	89 flagUpdates = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	90 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	91
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	92 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	93 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	94
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	95 class ChildBlock(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	96 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	97 if parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	98 return self.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	99 return super().processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	101 #Represents an instruction of the emulated CPU
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	102 class Instruction(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	103 def __init__(self, value, fields, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	104 self.value = value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105 self.fields = fields
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109 self.regValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	110 self.varyingBits = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	111 self.invalidFieldValues = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	112 self.invalidCombos = []
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	113 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	114 for field in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	115 self.varyingBits += fields[field][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	116
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	117 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	118 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	119 name = op.params[0]
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	120 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	121 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	122 elif op.op == 'invalid':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	123 if len(op.params) < 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	124 name = op.params[0]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	125 value = int(op.params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	126 self.invalidFieldValues.setdefault(name, set()).add(value)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	127 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	128 vmap = {}
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	129 for i in range(0, len(op.params), 2):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	130 name = op.params[i]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	131 value = int(op.params[i+1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	132 vmap[name] = value
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	133 self.invalidCombos.append(vmap)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	134 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	135 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	136
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	137 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	138 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	139 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	140 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	141
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	142 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	143 self.locals[name] = size
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	144 self.newLocals.append(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	145
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 return self.locals.get(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149 def __lt__(self, other):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150 if isinstance(other, Instruction):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 if self.varyingBits != other.varyingBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	152 return self.varyingBits < other.varyingBits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	153 return self.value < other.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 return NotImplemented
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	156
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157 def allValues(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	158 values = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	159 for i in range(0, 1 << self.varyingBits):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	160 iword = self.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	161 doIt = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	162 combos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	163 for combo in self.invalidCombos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	164 combos.append(dict(combo))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	165 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	166 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	167 val = i & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	168 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	169 doIt = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	170 break
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	171 nextcombos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	172 for combo in combos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	173 if field in combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	174 if combo[field] == val:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	175 del combo[field]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	176 if not combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	177 doIt = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	178 break
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	179 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	180 continue
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	181 nextcombos.append(combo)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	182 combos = nextcombos
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	183 if not doIt:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	184 break
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	185 i >>= bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	186 iword \|= val << shift
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	187 if doIt:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	188 values.append(iword)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	189 return values
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	190
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	191 def getFieldVals(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	192 fieldVals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	193 fieldBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	194 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	195 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	196 val = (value >> shift) & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	197 fieldVals[field] = val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 fieldBits[field] = bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	199 return (fieldVals, fieldBits)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	200
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	201 def generateName(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202 fieldVals,fieldBits = self.getFieldVals(value)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	203 names = list(fieldVals.keys())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 names.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 funName = self.name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	206 for name in names:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208 return funName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210 def generateBody(self, value, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	211 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	212 prog.meta = {}
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	213 prog.pushScope(self)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	214 self.regValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	215 for var in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	216 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	217 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	218 fieldVals,_ = self.getFieldVals(value)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	219 self.processOps(prog, fieldVals, output, otype, self.implementation)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	220
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	221 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	222 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context, uint32_t target_cycle)\n{'
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	223 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	224 begin = '\n' + self.generateName(value) + ': {'
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	225 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	226 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	227 if prog.needFlagCoalesce:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	228 begin += prog.flags.coalesceFlags(prog, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	229 if prog.needFlagDisperse:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	230 output.append(prog.flags.disperseFlags(prog, otype))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	231 for var in self.newLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	232 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	233 for size in prog.temp:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	234 begin += '\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	235 prog.popScope()
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	236 if prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	237 output += prog.nextInstruction(otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	238 return begin + ''.join(output) + '\n}'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	239
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	240 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	241 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	242 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	243 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	244 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	245 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	246 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	247
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	248 #Represents the definition of a helper function
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	249 class SubRoutine(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	250 def __init__(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	251 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	252 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	253 self.args = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	254 self.arg_map = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	255 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	256 self.regValues = {}
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	257 self.argValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	258
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	259 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	260 if op.op == 'arg':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	261 name = op.params[0]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	262 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	263 self.arg_map[name] = len(self.args)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	264 self.args.append((name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	265 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 name = op.params[0]
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	267 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	270 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	271
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	274 return self.name + '_' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	275 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	276
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	278 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	279
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	280 def localSize(self, name):
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	281 if name in self.locals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	282 return self.locals[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	283 if name in self.arg_map:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	284 argIndex = self.arg_map[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	285 return self.args[argIndex][1]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	286 return None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	287
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	288 def inline(self, prog, params, output, otype, parent):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	289 if len(params) != len(self.args):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	290 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	291 argValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	292 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	293 self.regValues = parent.regValues
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	294 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	295 i = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	296 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	297 argValues[name] = params[i]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	298 i += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	299 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	300 size = self.locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	301 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name))
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	302 self.argValues = argValues
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	303 self.processOps(prog, argValues, output, otype, self.implementation)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	304 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	305
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	306 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	307 pieces = [self.name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	308 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	309 pieces.append('\n\targ {0} {1}'.format(name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	310 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	311 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	312 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	313 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	314 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	315
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	316 class Op:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	317 def __init__(self, evalFun = None):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	318 self.evalFun = evalFun
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	319 self.impls = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	320 self.outOp = ()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	321 def cBinaryOperator(self, op):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	322 def _impl(prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	323 if op == '-':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 a = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 b = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	326 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	327 a = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	328 b = params[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	329 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	330 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	331 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	332 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	333 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	334 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	335 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	336 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	337 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	338 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	339 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	340 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	341 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	342 prog.sizeAdjust = size
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	343 needsCarry = needsOflow = needsHalf = False
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	344 if flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	345 for flag in flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	346 calc = prog.flags.flagCalc[flag]
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	347 if calc == 'carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	348 needsCarry = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	349 elif calc == 'half-carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	350 needsHalf = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	351 elif calc == 'overflow':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	352 needsOflow = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	353 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	354 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	355 if len(params) <= 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	356 size = prog.paramSize(rawParams[2])
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	357 if needsCarry and op != '>>':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	358 size *= 2
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	359 decl,name = prog.getTemp(size)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	360 dst = prog.carryFlowDst = name
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	361 prog.lastA = a
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	362 prog.lastB = b
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	363 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	364 a = '((uint64_t){a})'.format(a=a)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	365 b = '((uint64_t){b})'.format(b=b)
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	366 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	367 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	368 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	369 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	370 return '{decl}\n\t{tmp} = ({a} & {mask}) {op} ({b} & {mask});\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	371 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	372 )
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	373 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	374 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	375 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	376 return decl + '\n\t{dst} = ({a} & {mask}) {op} ({b} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	377 dst = dst, a = a, b = b, op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	378 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	379 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	380 return decl + '\n\t{dst} = {a} {op} {b};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	381 dst = dst, a = a, b = b, op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	382 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	383 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	384 self.outOp = (2,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	385 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	386 def cUnaryOperator(self, op):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	387 def _impl(prog, params, rawParams, flagUpdates):
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	388 dst = params[1]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	389 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	390 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	391 if len(params) > 2:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	392 size = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	393 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	394 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	395 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	396 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	397 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	398 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	399 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	400 destSize = prog.paramSize(rawParams[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	401 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	402 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	403 prog.sizeAdjust = size
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	404 needsCarry = needsOflow = needsHalf = False
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	405 if op == '-':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	406 if flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	407 for flag in flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	408 calc = prog.flags.flagCalc[flag]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	409 if calc == 'carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	410 needsCarry = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	411 elif calc == 'half-carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	412 needsHalf = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	413 elif calc == 'overflow':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	414 needsOflow = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	415 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	416 size = prog.paramSize(rawParams[1])
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	417 decl,name = prog.getTemp(size)
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	418 dst = prog.carryFlowDst = name
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	419 prog.lastA = 0
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	420 prog.lastB = params[0]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	421 prog.lastBFlow = params[0]
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	422 if needsSizeAdjust:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	423 return decl + '\n\t{dst} = {op}({a} & {mask});'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	424 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	425 )
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	426 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	427 return decl + '\n\t{dst} = ({dst} & ~{mask}) \| (({op}{a}) & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	428 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	429 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	430 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	431 return decl + '\n\t{dst} = {op}{a};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	432 dst = dst, a = params[0], op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	433 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	434 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	435 self.outOp = (1,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	436 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	437 def addImplementation(self, lang, outOp, impl):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	438 self.impls[lang] = impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	439 if not outOp is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	440 if type(outOp) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	441 self.outOp = outOp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	442 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	443 self.outOp = (outOp,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	444 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	445 def evaluate(self, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	446 return self.evalFun(*params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	447 def canEval(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	448 return not self.evalFun is None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	449 def numArgs(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	450 return self.evalFun.__code__.co_argcount
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	451 def numParams(self):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	452 if self.outOp:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	453 params = max(self.outOp) + 1
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	454 else:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	455 params = 0
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	456 if self.evalFun:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	457 params = max(params, self.numArgs())
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	458 return params
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	459 def generate(self, otype, prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 if self.impls[otype].__code__.co_argcount == 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	461 return self.impls[otype](prog, params)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	462 elif self.impls[otype].__code__.co_argcount == 3:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	463 return self.impls[otype](prog, params, rawParams)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	464 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	465 return self.impls[otype](prog, params, rawParams, flagUpdates)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	466
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	467
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	468 def _xchgCImpl(prog, params, rawParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	469 size = prog.paramSize(rawParams[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	470 decl,name = prog.getTemp(size)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	471 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	472
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	473 def _dispatchCImpl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	474 if len(params) == 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	475 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	476 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	477 table = params[1]
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	478 if table == 'main':
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	479 prog.mainDispatch.add(params[0])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	480 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	481 return '\n\timpl_{tbl}[{op}](context, target_cycle);'.format(tbl = table, op = params[0])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	482 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	483 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	484 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	485 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	486
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	487 def _addExplicitFlagSet(prog, output, flag, flagval):
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	488 location = prog.flags.getStorage(flag)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	489 if type(location) is tuple:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	490 reg,bit = location
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	491 reg = prog.resolveReg(reg, None, {})
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	492 value = str(1 << bit)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	493 if flagval:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	494 operator = '\|='
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	495 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	496 operator = '&='
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	497 value = '~' + value
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	498 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value))
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	499 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	500 reg = prog.resolveReg(location, None, {})
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	501 output.append('\n\t{reg} = {val};'.format(reg=reg, val=flagval))
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	502
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	503 def _updateFlagsCImpl(prog, params, rawParams):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	504 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	505 output = []
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	506 parity = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	507 directFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	508 for flag in autoUpdate:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	509 calc = prog.flags.flagCalc[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	510 calc,_,resultBit = calc.partition('-')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	511 if prog.carryFlowDst:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	512 lastDst = prog.carryFlowDst
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	513 else:
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	514 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	515 storage = prog.flags.getStorage(flag)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	516 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	517 myRes = lastDst
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	518 after = ''
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	519 if calc == 'sign':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	520 resultBit = prog.getLastSize() - 1
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	521 elif calc == 'carry':
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	522 if prog.lastOp.op in ('asr', 'lsr', 'rrc'):
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	523 if type(prog.lastB) is int:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	524 if prog.lastB == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	525 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	526 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	527 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	528 resultBit = prog.lastB - 1
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	529 else:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	530 output.append(f'\n\tif (!{prog.lastB}) {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	531 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	532 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	533 after = '\n\t}'
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	534 resultBit = f'({prog.lastB} - 1)'
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	535 myRes = prog.lastA
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	536 elif prog.lastOp.op == 'rlc':
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	537 if type(prog.lastB) is int:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	538 if prog.lastB == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	539 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	540 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	541 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	542 resultBit = prog.getLastSize() - prog.lastB
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	543 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	544 output.append(f'\n\tif (!{prog.lastB}) {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	545 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	546 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	547 after = '\n\t}'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	548 resultBit = f'({prog.getLastSize()} - {prog.lastB})'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	549 myRes = prog.lastA
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	550 elif prog.lastOp.op == 'rol':
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	551 if type(prog.lastBUnmasked) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	552 if prog.lastBUnmasked == 0:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	553 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	554 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	555 else:
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	556 output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	557 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	558 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	559 after = '\n\t}'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	560 resultBit = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	561 elif prog.lastOp.op == 'ror':
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	562 if type(prog.lastBUnmasked) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	563 if prog.lastBUnmasked == 0:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	564 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	565 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	566 else:
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	567 output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	568 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	569 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	570 after = '\n\t}'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	571 resultBit = prog.getLastSize() - 1
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	572 elif prog.lastOp.op == 'neg':
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	573 if prog.carryFlowDst:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	574 realSize = prog.getLastSize()
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	575 if realSize != prog.paramSize(prog.carryFlowDst):
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	576 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	577 if type(storage) is tuple:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	578 reg,storageBit = storage
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	579 reg = prog.resolveParam(reg, None, {})
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	580 output.append('\n\t{reg} = {res} ? ({reg} \| {bit}U) : ({reg} & {mask}U);'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	581 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	582 ))
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	583 else:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	584 reg = prog.resolveParam(storage, None, {})
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	585 output.append('\n\t{reg} = {res} != 0;'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	586 reg = reg, res = lastDst
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	587 ))
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	588 continue
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	589 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	590 resultBit = prog.getLastSize()
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	591 elif calc == 'half':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	592 resultBit = prog.getLastSize() - 4
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	593 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	594 elif calc == 'overflow':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	595 resultBit = prog.getLastSize() - 1
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	596 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	597 else:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	598 #Note: offsetting this by the operation size - 8 makes sense for the Z80
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	599 #but might not for other CPUs with this kind of fixed bit flag behavior
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	600 resultBit = int(resultBit) + prog.getLastSize() - 8
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	601 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	602 reg,storageBit = storage
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	603 if storageBit == resultBit:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	604 directFlags.setdefault((reg, myRes), []).append(resultBit)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	605 else:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	606 reg = prog.resolveParam(reg, None, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	607 if resultBit > storageBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	608 op = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	609 shift = resultBit - storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	610 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	611 op = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	612 shift = storageBit - resultBit
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	613 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} {op} {shift}U & {mask}U);'.format(
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	614 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	615 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	616 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	617 reg = prog.resolveParam(storage, None, {})
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	618 maxBit = prog.paramSize(storage) - 1
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	619 if type(resultBit) is int:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	620 mask = f'{1 << resultBit}U'
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	621 else:
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	622 mask = f'(1 << {resultBit})'
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	623 if not type(resultBit) is int:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	624 output.append(f'\n\t{reg} = !!({myRes} & {mask});')
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	625 elif resultBit > maxBit:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	626 mask = f'{1 << maxBit}U'
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	627 output.append('\n\t{reg} = {res} >> {shift} & {mask};'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = mask))
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	628 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	629 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask))
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	630 if after:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	631 output.append(after)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	632 elif calc == 'zero':
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	633 if prog.carryFlowDst:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	634 realSize = prog.getLastSize()
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	635 if realSize != prog.paramSize(prog.carryFlowDst):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	636 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	637 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	638 reg,storageBit = storage
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	639 reg = prog.resolveParam(reg, None, {})
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	640 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} \| {bit}U);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	641 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	642 ))
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	643 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	644 reg = prog.resolveParam(storage, None, {})
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	645 output.append('\n\t{reg} = {res} == 0;'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	646 reg = reg, res = lastDst
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	647 ))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	648 elif calc == 'parity':
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	649 parity = storage
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	650 paritySize = prog.getLastSize()
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	651 if prog.carryFlowDst:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	652 parityDst = paritySrc = prog.carryFlowDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	653 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	654 paritySrc = lastDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	655 decl,name = prog.getTemp(paritySize)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	656 output.append(decl)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	657 parityDst = name
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	658 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	659 raise Exception('Unknown flag calc type: ' + calc)
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	660 for reg, myRes in directFlags:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	661 bits = directFlags[(reg, myRes)]
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	662 resolved = prog.resolveParam(reg, None, {})
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	663 if len(bits) == len(prog.flags.storageToFlags[reg]):
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	664 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes))
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	665 else:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	666 mask = 0
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	667 for bit in bits:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	668 mask \|= 1 << bit
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	669 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} & {mask}U);'.format(
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	670 reg = resolved, mask = mask, res = myRes
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	671 ))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	672 if prog.carryFlowDst:
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	673 if prog.lastOp.op != 'cmp':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	674 if prog.sizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	675 output.append('\n\t{dst} = ({dst} & ~{mask}) \| ({tmpdst} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	676 dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst, mask = ((1 << prog.sizeAdjust) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	677 ))
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	678 prog.sizeAdjust = None
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	679 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	680 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	681 prog.carryFlowDst = None
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	682 if parity:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	683 if paritySize > 8:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	684 if paritySize > 16:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	685 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	686 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	687 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	688 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	689 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	690 if type(parity) is tuple:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	691 reg,bit = parity
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	692 reg = prog.resolveParam(reg, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	693 output.append('\n\t{flag} = ({flag} & ~{mask}U) \| ((0x6996 >> {parity}) << {bit} & {mask}U);'.format(
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	694 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	695 ))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	696 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	697 reg = prog.resolveParam(parity, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	698 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	699
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	700 #TODO: combine explicit flags targeting the same storage location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	701 for flag in explicit:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	702 _addExplicitFlagSet(prog, output, flag, explicit[flag])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	703 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	704
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	705 def _cmpCImpl(prog, params, rawParams, flagUpdates):
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	706 b_size = size = prog.paramSize(rawParams[1])
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	707 needsCarry = False
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	708 if flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	709 for flag in flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	710 calc = prog.flags.flagCalc[flag]
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	711 if calc == 'carry':
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	712 needsCarry = True
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	713 break
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	714 if len(params) > 2:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	715 size = params[2]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	716 if size == 0:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	717 size = 8
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	718 elif size == 1:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	719 size = 16
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	720 else:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	721 size = 32
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	722 prog.lastSize = size
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	723 if needsCarry:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	724 size *= 2
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	725 tmpvar = 'cmp_tmp{sz}__'.format(sz=size)
1745 a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	726 if flagUpdates:
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	727 prog.carryFlowDst = tmpvar
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	728 prog.lastA = params[1]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	729 prog.lastB = params[0]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	730 prog.lastBFlow = params[0]
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	731 scope = prog.getRootScope()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	732 if not scope.resolveLocal(tmpvar):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	733 scope.addLocal(tmpvar, size)
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	734 prog.lastDst = rawParams[1]
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	735 a = params[0]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	736 b = params[1]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	737 a_size = prog.paramSize(rawParams[0])
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	738 if prog.lastSize != a_size:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	739 a = '(({a}) & {mask})'.format(a = a, mask = (1 << prog.lastSize) - 1)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	740 if prog.lastSize != b_size:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	741 b = '(({b}) & {mask})'.format(b = b, mask = (1 << prog.lastSize) - 1)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	742 if size == 64:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	743 a = '((uint64_t){a})'.format(a = a)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	744 b = '((uint64_t){b})'.format(b = b)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	745 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = a, b = b)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	746
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	747 def _asrCImpl(prog, params, rawParams, flagUpdates):
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	748 needsCarry = False
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	749 if flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	750 for flag in flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	751 calc = prog.flags.flagCalc[flag]
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	752 if calc == 'carry':
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	753 needsCarry = True
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	754 decl = ''
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	755 needsSizeAdjust = False
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	756 destSize = prog.paramSize(rawParams[2])
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	757 if len(params) > 3:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	758 size = params[3]
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	759 if size == 0:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	760 size = 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	761 elif size == 1:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	762 size = 16
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	763 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	764 size = 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	765 prog.lastSize = size
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	766 if destSize > size:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	767 needsSizeAdjust = True
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	768 prog.sizeAdjust = size
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	769 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	770 size = destSize
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	771 mask = 1 << (size - 1)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	772 if needsCarry:
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	773 decl,name = prog.getTemp(size)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	774 dst = prog.carryFlowDst = name
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	775 prog.lastA = params[0]
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	776 prog.lastB = params[1]
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	777 if needsSizeAdjust:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	778 sizeMask = (1 << size) - 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	779 return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format(
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	780 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	781 elif needsSizeAdjust:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	782 decl,name = prog.getTemp(size)
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	783 sizeMask = (1 << size) - 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	784 return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' +
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	785 '\n\t{dst} = ({dst} & ~{sizeMask}) \| {name};').format(
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	786 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	787 else:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	788 dst = params[2]
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	789
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	790 return decl + '\n\t{dst} = ({a} >> {b}) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	791 a = params[0], b = params[1], dst = dst, mask = mask, size=size)
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	792
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	793 def _sext(size, src):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	794 if size == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	795 return src \| 0xFF00 if src & 0x80 else src & 0x7F
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	796 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	797 return src \| 0xFFFF0000 if src & 0x8000 else src & 0x7FFF
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	798
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	799 def _sextCImpl(prog, params, rawParms):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	800 if params[0] == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	801 fmt = '\n\t{dst} = {src} & 0x80 ? {src} \| 0xFF00 : {src} & 0x7F;'
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	802 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	803 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} \| 0xFFFF0000 : {src} & 0x7FFF;'
2468 0ca78837e4d2 Implement ext instruction in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2463 diff changeset	804 prog.lastSize = params[0]
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	805 return fmt.format(src=params[1], dst=params[2])
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	806
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	807 def _mulsCImpl(prog, params, rawParams, flagUpdates):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	808 p0Size = prog.paramSize(rawParams[0])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	809 p1Size = prog.paramSize(rawParams[1])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	810 destSize = prog.paramSize(rawParams[2])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	811 if len(params) > 3:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	812 size = params[3]
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	813 if size == 0:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	814 size = 8
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	815 elif size == 1:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	816 size = 16
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	817 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	818 size = 32
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	819 prog.lastSize = size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	820 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	821 size = destSize
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	822 if p0Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	823 p0Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	824 if p1Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	825 p1Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	826 #TODO: Handle case in which destSize > size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	827 return f'\n\t{params[2]} = (int{size}_t)(((int{p0Size}_t){params[0]}) * ((int{p1Size}_t){params[1]}));'
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	828
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	829 def _muluCImpl(prog, params, rawParams, flagUpdates):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	830 p0Size = prog.paramSize(rawParams[0])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	831 p1Size = prog.paramSize(rawParams[1])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	832 destSize = prog.paramSize(rawParams[2])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	833 if len(params) > 3:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	834 size = params[3]
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	835 if size == 0:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	836 size = 8
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	837 elif size == 1:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	838 size = 16
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	839 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	840 size = 32
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	841 prog.lastSize = size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	842 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	843 size = destSize
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	844 if p0Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	845 p0Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	846 if p1Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	847 p1Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	848 #TODO: Handle case in which destSize > size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	849 return f'\n\t{params[2]} = ((uint{p0Size}_t){params[0]}) * ((uint{p1Size}_t){params[1]});'
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	850
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	851 def _getCarryCheck(prog):
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	852 carryFlag = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	853 for flag in prog.flags.flagOrder:
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	854 if prog.flags.flagCalc[flag] == 'carry':
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	855 carryFlag = flag
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	856 break
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	857 if carryFlag is None:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	858 raise Exception('adc requires a defined carry flag')
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	859 carryStorage = prog.flags.getStorage(carryFlag)
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	860 if type(carryStorage) is tuple:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	861 reg,bit = carryStorage
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	862 reg = prog.resolveReg(reg, None, (), False)
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	863 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	864 else:
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	865 return prog.resolveReg(carryStorage, None, (), False)
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	866
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	867 def _adcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	868 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	869 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	870 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	871 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	872 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	873 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	874 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	875 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	876 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	877 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	878 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	879 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	880 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	881 prog.sizeAdjust = size
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	882 needsCarry = needsOflow = needsHalf = False
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	883 if flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	884 for flag in flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	885 calc = prog.flags.flagCalc[flag]
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	886 if calc == 'carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	887 needsCarry = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	888 elif calc == 'half-carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	889 needsHalf = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	890 elif calc == 'overflow':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	891 needsOflow = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	892 decl = ''
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	893 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	894 vals = '1 : 0'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	895 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	896 if len(params) <= 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	897 size = prog.paramSize(rawParams[2])
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	898 if needsCarry:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	899 size *= 2
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	900 decl,name = prog.getTemp(size)
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	901 dst = prog.carryFlowDst = name
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	902 prog.lastA = params[0]
1744 91aa789e57bd Fixed half-carry flag calcuation for adc/sbc in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1742 diff changeset	903 prog.lastB = params[1]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	904 prog.lastBFlow = '(~{b})'.format(b=params[1])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	905 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	906 params[0] = '((uint64_t){a})'.format(a=params[0])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	907 params[1] = '((uint64_t){b})'.format(b=params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	908 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	909 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	910 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	911 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	912 return '{decl}\n\t{tmp} = ({a} & {mask}) + ({b} & {mask}) + ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	913 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	914 )
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	915 else:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	916 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	917 return decl + '\n\t{dst} = {a} + {b} + ({check} ? {vals});'.format(dst = dst,
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	918 a = params[0], b = params[1], check = carryCheck, vals = vals
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	919 )
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	920
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	921 def _sbcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	922 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	923 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	924 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	925 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	926 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	927 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	928 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	929 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	930 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	931 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	932 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	933 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	934 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	935 prog.sizeAdjust = size
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	936 needsCarry = needsOflow = needsHalf = False
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	937 if flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	938 for flag in flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	939 calc = prog.flags.flagCalc[flag]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	940 if calc == 'carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	941 needsCarry = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	942 elif calc == 'half-carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	943 needsHalf = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	944 elif calc == 'overflow':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	945 needsOflow = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	946 decl = ''
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	947 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	948 vals = '1 : 0'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	949 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	950 size = prog.paramSize(rawParams[2])
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	951 if needsCarry:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	952 size *= 2
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	953 decl,name = prog.getTemp(size)
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	954 dst = prog.carryFlowDst = name
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	955 prog.lastA = params[1]
1744 91aa789e57bd Fixed half-carry flag calcuation for adc/sbc in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1742 diff changeset	956 prog.lastB = params[0]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	957 prog.lastBFlow = params[0]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	958 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	959 params[1] = '((uint64_t){a})'.format(a=params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	960 params[0] = '((uint64_t){b})'.format(b=params[0])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	961 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	962 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	963 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	964 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	965 return '{decl}\n\t{tmp} = ({b} & {mask}) - ({a} & {mask}) - ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	966 decl = decl, tmp = name, a = params[0], b = params[1], op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	967 )
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	968 else:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	969 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	970 return decl + '\n\t{dst} = {b} - {a} - ({check} ? {vals});'.format(dst = dst,
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	971 a = params[0], b = params[1], check=_getCarryCheck(prog), vals = vals
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	972 )
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	973
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	974 def _rolCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	975 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	976 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	977 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	978 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	979 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	980 needsCarry = True
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	981 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	982 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	983 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	984 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	985 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	986 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	987 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	988 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	989 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	990 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	991 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	992 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	993 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	994 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	995 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	996 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	997 size = destSize
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	998 rotMask = size - 1
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	999 if type(params[1]) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1000 b = params[1] & rotMask
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1001 mdecl = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1002 ret = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1003 else:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1004 mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1005 ret = f'\n\t{b} = {params[1]} & {rotMask};'
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1006 prog.lastB = b
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1007 prog.lastBUnmasked = params[1]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1008 if needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1009 decl,name = prog.getTemp(size)
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1010 mdecl += decl
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1011 dst = prog.carryFlowDst = name
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1012 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1013 dst = params[2]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1014 ret += '\n\t{dst} = {a} << {b} \| {a} >> ({size} - {b});'.format(dst = dst,
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1015 a = params[0], b = b, size=size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1016 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1017 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1018 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1019 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1020 return mdecl + ret
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1021
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1022 def _rlcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1023 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1024 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1025 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1026 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1027 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1028 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1029 decl = ''
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1030 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1031 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1032 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1033 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1034 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1035 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1036 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1037 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1038 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1039 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1040 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1041 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1042 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1043 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1044 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1045 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1046 size = destSize
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1047 carryCheck = _getCarryCheck(prog)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1048 size = prog.paramSize(rawParams[2])
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1049 if needsCarry or needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1050 decl,name = prog.getTemp(size)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1051 dst = prog.carryFlowDst = name
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1052 prog.lastA = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1053 prog.lastB = params[1]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1054 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1055 dst = params[2]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1056 if size == 32 and (not type(params[1]) is int) or params[1] <= 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1057 # we may need to shift by 32-bits which is too much for a normal int
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1058 a = f'((uint64_t){params[0]})'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1059 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1060 a = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1061 ret = decl + '\n\t{dst} = {a} << {b} \| {a} >> ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst,
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1062 a = a, b = params[1], size=size, check=carryCheck
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1063 )
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1064 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1065 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1066 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1067 return ret
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1068
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1069 def _rorCImpl(prog, params, rawParams, flagUpdates):
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1070 needsCarry = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1071 if flagUpdates:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1072 for flag in flagUpdates:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1073 calc = prog.flags.flagCalc[flag]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1074 if calc == 'carry':
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1075 needsCarry = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1076 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1077 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1078 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1079 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1080 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1081 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1082 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1083 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1084 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1085 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1086 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1087 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1088 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1089 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1090 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1091 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1092 size = destSize
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1093 rotMask = size - 1
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1094 if type(params[1]) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1095 b = params[1] & rotMask
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1096 mdecl = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1097 ret = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1098 else:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1099 mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1100 ret = f'\n\t{b} = {params[1]} & {rotMask};'
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1101 prog.lastB = b
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1102 prog.lastBUnmasked = params[1]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1103 if needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1104 decl,name = prog.getTemp(size)
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1105 dst = prog.carryFlowDst = name
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1106 mdecl += decl
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1107 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1108 dst = params[2]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1109 ret += '\n\t{dst} = {a} >> {b} \| {a} << ({size} - {b});'.format(dst = dst,
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1110 a = params[0], b = b, size=size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1111 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1112 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1113 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1114 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1115 return mdecl + ret
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1116
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1117 def _rrcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1118 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1119 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1120 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1121 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1122 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1123 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1124 decl = ''
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1125 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1126 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1127 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1128 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1129 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1130 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1131 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1132 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1133 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1134 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1135 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1136 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1137 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1138 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1139 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1140 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1141 size = destSize
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1142 carryCheck = _getCarryCheck(prog)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1143 size = prog.paramSize(rawParams[2])
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1144 if needsCarry or needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1145 decl,name = prog.getTemp(size)
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1146 dst = prog.carryFlowDst = name
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1147 prog.lastA = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1148 prog.lastB = params[1]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1149 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1150 dst = params[2]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1151 if size == 32 and (not type(params[1]) is int) or params[1] <= 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1152 # we may need to shift by 32-bits which is too much for a normal int
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1153 a = f'((uint64_t){params[0]})'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1154 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1155 a = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1156 ret = decl + '\n\t{dst} = {a} >> {b} \| {a} << ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst,
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1157 a = a, b = params[1], size=size, check=carryCheck
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1158 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1159 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1160 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1161 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1162 return ret
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1163
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1164 def _updateSyncCImpl(prog, params):
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1165 return '\n\t{sync}(context, target_cycle);'.format(sync=prog.sync_cycle)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	1166
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1167 _opMap = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1168 'mov': Op(lambda val: val).cUnaryOperator(''),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1169 'not': Op(lambda val: ~val).cUnaryOperator('~'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1170 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1171 'neg': Op(lambda val: -val).cUnaryOperator('-'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1172 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	1173 'adc': Op().addImplementation('c', 2, _adcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1174 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	1175 'sbc': Op().addImplementation('c', 2, _sbcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1176 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1177 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1178 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1179 'rol': Op().addImplementation('c', 2, _rolCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1180 'rlc': Op().addImplementation('c', 2, _rlcCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1181 'ror': Op().addImplementation('c', 2, _rorCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1182 'rrc': Op().addImplementation('c', 2, _rrcCImpl),
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1183 'mulu': Op(lambda a, b: a * b).addImplementation('c', 2, _muluCImpl),
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1184 'muls': Op().addImplementation('c', 2, _mulsCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1185 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1186 'or': Op(lambda a, b: a \| b).cBinaryOperator('\|'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1187 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1188 'abs': Op(lambda val: abs(val)).addImplementation(
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1189 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1190 ),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1191 'cmp': Op().addImplementation('c', None, _cmpCImpl),
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	1192 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1193 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1194 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1195 )),
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1196 'pcall': Op().addImplementation('c', None, lambda prog, params: '\n\t(({typ}){fun})({args});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1197 typ = params[1], fun = params[0], args = ', '.join([str(p) for p in params[2:]])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1198 )),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1199 'cycles': Op().addImplementation('c', None,
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1200 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1201 params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1202 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1203 ),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1204 'addsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1205 lambda a, b: b + (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1206 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + ({sz} ? {sz} * 2 : 1);'.format(
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1207 dst = params[2], sz = params[0], val = params[1]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1208 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1209 'decsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1210 lambda a, b: b - (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1211 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - ({sz} ? {sz} * 2 : 1);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1212 dst = params[2], sz = params[0], val = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1213 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1214 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1215 'dispatch': Op().addImplementation('c', None, _dispatchCImpl),
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1216 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl),
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1217 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1218 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1219
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1220 #represents a simple DSL instruction
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1221 class NormalOp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1222 def __init__(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1223 self.op = parts[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1224 self.params = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1225
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1226 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1227 procParams = []
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1228 allParamsConst = flagUpdates is None and not prog.conditional
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1229 opDef = _opMap.get(self.op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1230 for param in self.params:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1231 isDst = (not opDef is None) and len(procParams) in opDef.outOp
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1232 allowConst = (self.op in prog.subroutines or not isDst) and param in parent.regValues
1765 7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1233 if isDst and self.op == 'xchg':
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1234 #xchg uses its regs as both source and destination
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1235 #we need to resolve as both so that disperse/coalesce flag stuff gets done
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1236 prog.resolveParam(param, parent, fieldVals, allowConst, False)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1237 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1238
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1239 if (not type(param) is int) and len(procParams) != len(self.params) - 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1240 allParamsConst = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1241 procParams.append(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1242
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1243 if self.op == 'meta':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1244 param,_,index = self.params[1].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1245 if index:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1246 index = (parent.resolveLocal(index) or index)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1247 if index in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1248 index = str(fieldVals[index])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1249 param = param + '.' + index
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1250 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1251 param = parent.resolveLocal(param) or param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1252 if param in fieldVals:
1991 7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core Michael Pavone <pavone@retrodev.com> parents: 1938 diff changeset	1253 param = fieldVals[param]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1254 prog.meta[self.params[0]] = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1255 elif self.op == 'dis':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1256 #TODO: Disassembler
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1257 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1258 elif not opDef is None:
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1259 if opDef.numParams() > len(procParams):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1260 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1261 if opDef.canEval() and allParamsConst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1262 #do constant folding
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1263 if opDef.numArgs() >= len(procParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1264 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1265 dst = self.params[opDef.numArgs()]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1266 result = opDef.evaluate(procParams[:opDef.numArgs()])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1267 while dst in prog.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1268 dst = prog.meta[dst]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1269 maybeLocal = parent.resolveLocal(dst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1270 if maybeLocal:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1271 dst = maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1272 parent.regValues[dst] = result
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1273 if prog.isReg(dst):
2497 95d9809a3973 Fix constant propagation for sext instruction Michael Pavone <pavone@retrodev.com> parents: 2478 diff changeset	1274 shortProc = (result, procParams[-1])
95d9809a3973 Fix constant propagation for sext instruction Michael Pavone <pavone@retrodev.com> parents: 2478 diff changeset	1275 shortParams = (result, self.params[-1])
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1276 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1277 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1278 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
1728 b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1279 for dstIdx in opDef.outOp:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1280 dst = self.params[dstIdx]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1281 while dst in prog.meta:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1282 dst = prog.meta[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1283 if dst in parent.regValues:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1284 del parent.regValues[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1285
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1286 elif self.op in prog.subroutines:
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1287 procParams = []
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1288 for param in self.params:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1289 begin,sep,end = param.partition('.')
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1290 if sep:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1291 if end in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1292 param = begin + '.' + str(fieldVals[end])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1293 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1294 if param in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1295 param = fieldVals[param]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1296 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1297 maybeLocal = parent.resolveLocal(param)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1298 if maybeLocal and maybeLocal in parent.regValues:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1299 param = parent.regValues[maybeLocal]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1300 procParams.append(param)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1301 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1302 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1303 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1304 prog.lastOp = self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1305
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1306 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1307 return '\n\t' + self.op + ' ' + ' '.join(self.params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1308
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1309 #represents a DSL switch construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1310 class Switch(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1311 def __init__(self, parent, param):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1312 self.op = 'switch'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1313 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1314 self.param = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1315 self.cases = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1316 self.regValues = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1317 self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1318 self.case_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1319 self.current_case = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1320 self.default = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1321 self.default_locals = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1322
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1323 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1324 if op.op == 'case':
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1325 if op.params[0].startswith('0x'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1326 val = int(op.params[0], 16)
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1327 elif op.params[0].startswith('0b'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1328 val = int(op.params[0], 2)
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1329 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1330 val = int(op.params[0])
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1331 self.cases[val] = self.current_case = []
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1332 self.case_locals[val] = self.current_locals = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1333 elif op.op == 'default':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1334 self.default = self.current_case = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1335 self.default_locals = self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1336 elif self.current_case == None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1337 raise ion('Orphan instruction in switch')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1338 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1339 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1340 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1341 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1342 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1343 self.current_case.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1344
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1345 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1346 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1347 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1348 return self.parent.resolveLocal(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1349
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1350 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1351 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1352
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1353 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1354 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1355 return self.current_locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1356 return self.parent.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1357
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1358 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1359 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1360 param = prog.resolveParam(self.param, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1361 if type(param) is int:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1362 self.regValues = self.parent.regValues
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1363 if param in self.cases:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1364 self.current_locals = self.case_locals[param]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1365 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1366 for local in self.case_locals[param]:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1367 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1368 self.processOps(prog, fieldVals, output, otype, self.cases[param])
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1369 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1370 elif self.default:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1371 self.current_locals = self.default_locals
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1372 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1373 for local in self.default_locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1374 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1375 self.processOps(prog, fieldVals, output, otype, self.default)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1376 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1377 else:
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1378 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1379 prog.conditional = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1380 output.append('\n\tswitch(' + param + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1381 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1382 for case in self.cases:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1383 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1384 self.current_locals = self.case_locals[case]
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1385 self.regValues = dict(self.parent.regValues)
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1386 output.append('\n\tcase {0}U: '.format(case) + '{')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1387 for local in self.case_locals[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1388 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1389 self.processOps(prog, fieldVals, output, otype, self.cases[case])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1390 output.append('\n\tbreak;')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1391 output.append('\n\t}')
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1392 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1393 if self.default:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1394 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1395 self.current_locals = self.default_locals
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1396 self.regValues = dict(self.parent.regValues)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1397 output.append('\n\tdefault: {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1398 for local in self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1399 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1400 self.processOps(prog, fieldVals, output, otype, self.default)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1401 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1402 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1403 prog.conditional = oldCond
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1404 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1405
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1406 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1407 keys = self.cases.keys()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1408 keys.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1409 lines = ['\n\tswitch']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1410 for case in keys:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1411 lines.append('\n\tcase {0}'.format(case))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1412 lines.append(''.join([str(op) for op in self.cases[case]]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1413 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1414 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1415
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1416
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1417 def _geuCImpl(prog, parent, fieldVals, output):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1418 if prog.lastOp.op == 'cmp':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1419 output.pop()
1616 8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1420 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1421 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{'
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1422 else:
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1423 raise Exception(">=U not implemented in the general case yet")
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1424
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1425 def _eqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1426 if prog.lastOp.op == 'cmp':
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1427 output.pop()
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1428 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1429 return '\n\tif ({a} == {b}) '.format(a=params[1], b = params[0]) + '{'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1430 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1431 return '\n\tif (!{a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1432
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1433 def _neqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1434 return '\n\tif ({a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1435
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1436 _ifCmpImpl = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1437 'c': {
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1438 '>=U': _geuCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1439 '=': _eqCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1440 '!=': _neqCImpl
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1441 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1442 }
2452 8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1443 _ifCmpEval = {
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1444 '>=U': lambda a, b: a >= b,
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1445 '=': lambda a, b: a == b,
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1446 '!=': lambda a, b: a != b
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1447 }
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1448 #represents a DSL conditional construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1449 class If(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1450 def __init__(self, parent, cond):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1451 self.op = 'if'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1452 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1453 self.cond = cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1454 self.body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1455 self.elseBody = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1456 self.curBody = self.body
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1457 self.locals = {}
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1458 self.elseLocals = {}
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1459 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1460 self.regValues = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1461
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1462 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1463 if op.op in ('case', 'arg'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1464 raise Exception(self.op + ' is not allows inside an if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1465 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1466 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1467 size = op.params[1]
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1468 self.curLocals[name] = size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1469 elif op.op == 'else':
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1470 self.curLocals = self.elseLocals
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1471 self.curBody = self.elseBody
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1472 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1473 self.curBody.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1474
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1475 def localSize(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1476 return self.curLocals.get(name)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1477
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1478 def resolveLocal(self, name):
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1479 if name in self.curLocals:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1480 return name
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1481 return self.parent.resolveLocal(name)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1482
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1483 def _genTrueBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1484 self.curLocals = self.locals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1485 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1486 self.processOps(prog, fieldVals, subOut, otype, self.body)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1487 for local in self.locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1488 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1489 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1490
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1491 def _genFalseBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1492 self.curLocals = self.elseLocals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1493 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1494 self.processOps(prog, fieldVals, subOut, otype, self.elseBody)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1495 for local in self.elseLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1496 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1497 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1498
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1499 def _genConstParam(self, param, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1500 if param:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1501 self._genTrueBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1502 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1503 self._genFalseBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1504
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1505 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1506 self.regValues = parent.regValues
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1507 if self.cond in prog.booleans:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1508 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1509 else:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1510 if self.cond in _ifCmpImpl[otype]:
2452 8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1511 if prog.lastOp.op == 'cmp':
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1512 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1513 if type(params[0]) is int and type(params[1]) is int:
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1514 output.pop()
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1515 res = _ifCmpEval[self.cond](params[1], params[0])
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1516 self._genConstParam(res, prog, fieldVals, output, otype)
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1517 return
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1518 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1519 prog.conditional = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1520 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1521 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1522 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1523 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1524 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1525 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1526 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1527 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1528 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1529 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1530 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1531 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1532 cond = prog.resolveParam(self.cond, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1533 if type(cond) is int:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1534 self._genConstParam(cond, prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1535 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1536 #temp = prog.temp.copy()
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1537 output.append('\n\tif ({cond}) '.format(cond=cond) + '{')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1538 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1539 prog.conditional = True
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1540 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1541 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1542 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1543 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1544 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1545 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1546 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1547 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1548 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1549
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1550
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1551 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1552 lines = ['\n\tif']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1553 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1554 lines.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1555 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1556 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1557
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1558 class Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1559 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1560 self.regs = {}
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1561 self.pointers = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1562 self.regArrays = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1563 self.regToArray = {}
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1564 self.addReg('cycles', 32)
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1565 self.addReg('sync_cycle', 32)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1566
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1567 def addReg(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1568 self.regs[name] = size
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1569
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1570 def addPointer(self, name, size, count):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1571 self.pointers[name] = (size, count)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1572
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1573 def addRegArray(self, name, size, regs):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1574 self.regArrays[name] = (size, regs)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1575 idx = 0
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1576 if not type(regs) is int:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1577 for reg in regs:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1578 self.regs[reg] = size
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1579 self.regToArray[reg] = (name, idx)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1580 idx += 1
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1581
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1582 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1583 return name in self.regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1584
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1585 def isRegArray(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1586 return name in self.regArrays
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1587
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1588 def isRegArrayMember(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1589 return name in self.regToArray
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1590
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1591 def arrayMemberParent(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1592 return self.regToArray[name][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1593
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1594 def arrayMemberIndex(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1595 return self.regToArray[name][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1596
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1597 def arrayMemberName(self, array, index):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1598 if type(index) is int and not type(self.regArrays[array][1]) is int:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1599 return self.regArrays[array][1][index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1600 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1601 return None
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1602
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1603 def isNamedArray(self, array):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1604 return array in self.regArrays and type(self.regArrays[array][1]) is int
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1605
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1606 def processLine(self, parts):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1607 if len(parts) == 3:
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1608 if parts[1].startswith('ptr'):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1609 self.addPointer(parts[0], parts[1][3:], int(parts[2]))
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1610 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1611 self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1612 elif len(parts) > 2:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1613 self.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1614 else:
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1615 if parts[1].startswith('ptr'):
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1616 self.addPointer(parts[0], parts[1][3:], 1)
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1617 else:
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1618 self.addReg(parts[0], int(parts[1]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1619 return self
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1620
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1621 def writeHeader(self, otype, hFile):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1622 fieldList = []
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1623 for pointer in self.pointers:
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1624 stars = '*'
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1625 ptype, count = self.pointers[pointer]
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1626 while ptype.startswith('ptr'):
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1627 stars += '*'
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1628 ptype = ptype[3:]
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1629 if ptype.isdigit():
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1630 ptype = 'uint{sz}_t'.format(sz=ptype)
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1631 if count > 1:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1632 arr = '[{n}]'.format(n=count)
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1633 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1634 arr = ''
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1635 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1636 for reg in self.regs:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1637 if not self.isRegArrayMember(reg):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1638 fieldList.append((self.regs[reg], 1, reg))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1639 for arr in self.regArrays:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1640 size,regs = self.regArrays[arr]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1641 if not type(regs) is int:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1642 regs = len(regs)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1643 fieldList.append((size, regs, arr))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1644 fieldList.sort()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1645 fieldList.reverse()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1646 for size, count, name in fieldList:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1647 if count > 1:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1648 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1649 else:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1650 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1651
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1652 class Flags:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1653 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1654 self.flagBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1655 self.flagCalc = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1656 self.flagStorage = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1657 self.flagOrder = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1658 self.flagReg = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1659 self.storageToFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1660 self.maxBit = -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1661
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1662 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1663 if parts[0] == 'register':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1664 self.flagReg = parts[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1665 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1666 flag,bit,calc,storage = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1667 bit,_,top = bit.partition('-')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1668 bit = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1669 if top:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1670 top = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1671 if top > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1672 self.maxBit = top
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1673 self.flagBits[flag] = (bit,top)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1674 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1675 if bit > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1676 self.maxBit = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1677 self.flagBits[flag] = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1678 self.flagCalc[flag] = calc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1679 self.flagStorage[flag] = storage
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1680 storage,_,storebit = storage.partition('.')
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1681 self.storageToFlags.setdefault(storage, []).append((storebit, flag))
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1682 self.flagOrder.append(flag)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1683 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1684
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1685 def getStorage(self, flag):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1686 if not flag in self.flagStorage:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1687 raise Exception('Undefined flag ' + flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1688 loc,_,bit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1689 if bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1690 return (loc, int(bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1691 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1692 return loc
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1693
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1694 def parseFlagUpdate(self, flagString):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1695 last = ''
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1696 autoUpdate = set()
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1697 explicit = {}
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1698 for c in flagString:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1699 if c.isdigit():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1700 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1701 num = int(c)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1702 if num > 1:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1703 raise Exception(c + ' is not a valid digit for update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1704 explicit[last] = num
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1705 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1706 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1707 raise Exception('Digit must follow flag letter in update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1708 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1709 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1710 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1711 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1712 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1713 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1714 return (autoUpdate, explicit)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1715
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1716 def disperseFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1717 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1718 src = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1719 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1720 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1721 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1722 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1723 bot,top = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1724 mask = ((1 << (top + 1 - bot)) - 1) << bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1725 output.append('\n\t{dst} = {src} & mask;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1726 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1727 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1728 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1729 bitToFlag[self.flagBits[flag]] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1730 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1731 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1732 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1733 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1734 field,_,dstbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1735 dst = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1736 if dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1737 dstbit = int(dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1738 multi.setdefault(dst, []).append((dstbit, bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1739 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1740 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1741 for dst in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1742 didClear = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1743 direct = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1744 for dstbit, bit in multi[dst]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1745 if dstbit == bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1746 direct.append(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1747 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1748 if not didClear:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1749 output.append('\n\t{dst} = 0;'.format(dst=dst))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1750 didClear = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1751 if dstbit > bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1752 shift = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1753 diff = dstbit - bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1754 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1755 shift = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1756 diff = bit - dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1757 output.append('\n\t{dst} \|= {src} {shift} {diff} & {mask};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1758 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1759 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1760 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1761 if len(direct) == len(multi[dst]):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1762 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1763 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1764 mask = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1765 for bit in direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1766 mask = mask \| (1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1767 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1768 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1769
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1770 def coalesceFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1771 dst = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1772 output = ['\n\t{dst} = 0;'.format(dst=dst)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1773 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1774 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1775 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1776 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1777 bot,_ = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1778 src = prog.resolveReg(self.flagStorage[flag], None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1779 if bot:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1780 output.append('\n\t{dst} \|= {src} << {shift};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1781 dst=dst, src = src, shift = bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1782 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1783 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1784 output.append('\n\t{dst} \|= {src};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1785 dst=dst, src = src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1786 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1787 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1788 bitToFlag[bit] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1789 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1790 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1791 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1792 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1793 field,_,srcbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1794 src = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1795 if srcbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1796 srcbit = int(srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1797 multi.setdefault(src, []).append((srcbit,bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1798 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1799 output.append('\n\tif ({src}) {{\n\t\t{dst} \|= 1 << {bit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1800 dst=dst, src=src, bit=bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1801 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1802 for src in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1803 direct = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1804 for srcbit, dstbit in multi[src]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1805 if srcbit == dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1806 direct = direct \| (1 << srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1807 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1808 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} \|= 1 << {dstbit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1809 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1810 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1811 if direct:
1698 90272218469c Fixed missing semicolon in coalesceFlags Michael Pavone <pavone@retrodev.com> parents: 1697 diff changeset	1812 output.append('\n\t{dst} \|= {src} & {mask};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1813 dst=dst, src=src, mask=direct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1814 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1815 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1816
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1817
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1818 class Program:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1819 def __init__(self, regs, instructions, subs, info, flags):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1820 self.regs = regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1821 self.instructions = instructions
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1822 self.subroutines = subs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1823 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1824 self.booleans = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1825 self.prefix = info.get('prefix', [''])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1826 self.opsize = int(info.get('opcode_size', ['8'])[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1827 self.extra_tables = info.get('extra_tables', [])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1828 self.context_type = self.prefix + 'context'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1829 self.body = info.get('body', [None])[0]
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1830 self.interrupt = info.get('interrupt', [None])[0]
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1831 self.sync_cycle = info.get('sync_cycle', [None])[0]
1620 a172f97d873f Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16 Michael Pavone <pavone@retrodev.com> parents: 1619 diff changeset	1832 self.includes = info.get('include', [])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1833 self.flags = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1834 self.lastDst = None
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1835 self.scopes = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1836 self.currentScope = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1837 self.lastOp = None
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1838 self.carryFlowDst = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1839 self.lastA = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1840 self.lastB = None
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	1841 self.lastBFlow = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1842 self.sizeAdjust = None
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1843 self.conditional = False
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1844 self.declares = []
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1845 self.lastSize = None
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1846 self.mainDispatch = set()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1847
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1848 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1849 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1850 for reg in self.regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1851 pieces.append(str(self.regs[reg]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1852 for name in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1853 pieces.append('\n'+str(self.subroutines[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1854 for instruction in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1855 pieces.append('\n'+str(instruction))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1856 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1857
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1858 def writeHeader(self, otype, header):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1859 hFile = open(header, 'w')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1860 macro = header.upper().replace('.', '_')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1861 hFile.write('#ifndef {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1862 hFile.write('\n#define {0}_'.format(macro))
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	1863 hFile.write('\n#include <stdio.h>')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1864 hFile.write('\n#include "backend.h"')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1865 hFile.write(f'\n\ntypedef struct {self.prefix}options {self.prefix}options;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1866 hFile.write(f'\n\ntypedef struct {self.prefix}context {self.prefix}context;')
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1867 for decl in self.declares:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2497 diff changeset	1868 if decl.startswith('define '):
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2497 diff changeset	1869 decl = '#' + decl
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1870 hFile.write('\n' + decl)
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1871 hFile.write(f'\n\nstruct {self.prefix}options {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1872 hFile.write('\n\tcpu_options gen;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1873 hFile.write('\n\tFILE* address_log;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1874 hFile.write('\n};')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1875 hFile.write(f'\n\nstruct {self.prefix}context {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1876 hFile.write(f'\n\t{self.prefix}options *opts;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1877 self.regs.writeHeader(otype, hFile)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1878 hFile.write('\n};')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1879 hFile.write('\n')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1880 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1881 hFile.write('\n#endif //{0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1882 hFile.write('\n')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1883 hFile.close()
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1884
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1885 def _buildTable(self, otype, table, body, lateBody):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1886 pieces = []
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1887 opmap = [None] * (1 << self.opsize)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1888 bodymap = {}
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1889 if table in self.instructions:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1890 instructions = self.instructions[table]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1891 instructions.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1892 for inst in instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1893 for val in inst.allValues():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1894 if opmap[val] is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1895 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1896 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1897 self.needFlagCoalesce = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1898 self.needFlagDisperse = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1899 self.lastOp = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1900 opmap[val] = inst.generateName(val)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1901 bodymap[val] = inst.generateBody(val, self, otype)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1902
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1903 if self.dispatch == 'call':
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1904 lateBody.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1905 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1906 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1907 if op is None:
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1908 lateBody.append('\n\tunimplemented,')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1909 else:
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1910 lateBody.append('\n\t' + op + ',')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1911 body.append(bodymap[inst])
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1912 lateBody.append('\n};')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1913 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1914 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1915 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1916 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1917 if op is None:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1918 body.append('\n\t\t&&unimplemented,')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1919 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1920 body.append('\n\t\t&&' + op + ',')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1921 lateBody.append(bodymap[inst])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1922 body.append('\n\t};')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1923 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1924 raise Exception("unimplmeneted dispatch type " + self.dispatch)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1925 body.extend(pieces)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1926
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1927 def nextInstruction(self, otype):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1928 output = []
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1929 if self.dispatch == 'goto':
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1930 if self.interrupt in self.subroutines:
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1931 output.append('\n\tif (context->cycles >= context->sync_cycle) {')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1932 output.append('\n\tif (context->cycles >= target_cycle) { return; }')
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1933 if self.interrupt in self.subroutines:
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1934 self.meta = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1935 self.temp = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1936 self.subroutines[self.interrupt].inline(self, [], output, otype, None)
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1937 output.append('\n\t}')
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1938
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1939 self.meta = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1940 self.temp = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1941 self.subroutines[self.body].inline(self, [], output, otype, None)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1942 return output
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1943
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1944 def build(self, otype):
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1945 body = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1946 pieces = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1947 for include in self.includes:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1948 body.append('#include "{0}"\n'.format(include))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1949 if self.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1950 body.append('\ntypedef void (impl_fun)({pre}context context, uint32_t target_cycle);'.format(pre=self.prefix))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1951 for table in self.extra_tables:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1952 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1953 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1954 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1955 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1956 body.append('\n{')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1957
1740 28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL Michael Pavone <pavone@retrodev.com> parents: 1737 diff changeset	1958 for table in self.extra_tables:
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1959 self._buildTable(otype, table, body, pieces)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1960 self._buildTable(otype, 'main', body, pieces)
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1961 if self.dispatch == 'call':
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1962 if self.body in self.subroutines:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1963 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1964 pieces.append('\n{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1965 pieces.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1966 pieces.append('\n\twhile (context->cycles < target_cycle)')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1967 pieces.append('\n\t{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1968 if self.interrupt in self.subroutines:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1969 pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1970 pieces.append(f'\n\t\t\t{self.sync_cycle}(context, target_cycle);')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1971 pieces.append('\n\t\t}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1972 self.meta = {}
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1973 self.temp = {}
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1974 intpieces = []
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1975 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1976 for size in self.temp:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1977 pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1978 pieces += intpieces
1883 9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1979 self.meta = {}
9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1980 self.temp = {}
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1981 self.subroutines[self.body].inline(self, [], pieces, otype, None)
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1982 pieces.append('\n\t}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1983 pieces.append('\n}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1984 body.append('\nstatic void unimplemented({pre}context *context, uint32_t target_cycle)'.format(pre = self.prefix))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1985 body.append('\n{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1986 if len(self.mainDispatch) == 1:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1987 dispatch = list(self.mainDispatch)[0]
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1988 body.append(f'\n\tfatal_error("Unimplemented instruction: %X\\n", {dispatch});')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1989 else:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1990 body.append('\n\tfatal_error("Unimplemented instruction\\n");')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1991 body.append('\n}\n')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1992 elif self.dispatch == 'goto':
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1993 body.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1994 body += self.nextInstruction(otype)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1995 pieces.append('\nunimplemented:')
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1996 if len(self.mainDispatch) == 1:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1997 dispatch = list(self.mainDispatch)[0]
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1998 body.append(f'\n\tfatal_error("Unimplemented instruction: %X\\n", {dispatch});')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1999 else:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2000 body.append('\n\tfatal_error("Unimplemented instruction\\n");')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2001 pieces.append('\n}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2002 return ''.join(body) + ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2003
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2004 def checkBool(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2005 if not name in self.booleans:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2006 raise Exception(name + ' is not a defined boolean flag')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2007 return self.booleans[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2008
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2009 def getTemp(self, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2010 if size in self.temp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2011 return ('', self.temp[size])
1742 6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1740 diff changeset	2012 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size);
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2013 return ('', self.temp[size])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2014
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2015 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2016 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2017 while keepGoing:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2018 keepGoing = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2019 try:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2020 if type(param) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2021 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2022 elif param.startswith('0x'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2023 param = int(param, 16)
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	2024 elif param.startswith('0b'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	2025 param = int(param, 2)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2026 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2027 param = int(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2028 except ValueError:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2029
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2030 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2031 if param in parent.regValues and allowConstant:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2032 return parent.regValues[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2033 maybeLocal = parent.resolveLocal(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2034 if maybeLocal:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2035 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2036 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2037 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2038 return maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2039 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2040 param = fieldVals[param]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	2041 fieldVals = {}
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	2042 keepGoing = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2043 elif param in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2044 param = self.meta[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2045 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2046 elif self.isReg(param):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2047 return self.resolveReg(param, parent, fieldVals, isdst)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2048 elif param in self.regs.pointers:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2049 return 'context->' + param
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2050 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2051 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2052 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2053 return param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2054
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2055 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2056 if not type(name) is str:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2057 return False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2058 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2059 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2060 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2061 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2062 return self.regs.isRegArray(begin)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2063 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2064 return self.regs.isReg(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2065
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2066 def resolveReg(self, name, parent, fieldVals, isDst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2067 begin,sep,end = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2068 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2069 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2070 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2071 if not self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2072 end = self.resolveParam(end, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2073 if not type(end) is int and self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2074 arrayName = self.regs.arrayMemberParent(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2075 end = self.regs.arrayMemberIndex(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2076 if arrayName != begin:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2077 end = 'context->{0}[{1}]'.format(arrayName, end)
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2078 if self.regs.isNamedArray(begin):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2079 regName = self.regs.arrayMemberName(begin, end)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2080 else:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2081 regName = '{0}.{1}'.format(begin, end)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2082 ret = 'context->{0}[{1}]'.format(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2083 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2084 regName = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2085 if self.regs.isRegArrayMember(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2086 arr,idx = self.regs.regToArray[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2087 ret = 'context->{0}[{1}]'.format(arr, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2088 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2089 ret = 'context->' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2090 if regName == self.flags.flagReg:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2091 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2092 self.needFlagDisperse = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2093 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2094 self.needFlagCoalesce = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2095 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2096 self.lastDst = regName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2097 return ret
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2098
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2099
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2100
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2101 def paramSize(self, name):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2102 if name in self.meta:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2103 return self.paramSize(self.meta[name])
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2104 for i in range(len(self.scopes) -1, -1, -1):
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2105 size = self.scopes[i].localSize(name)
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2106 if size:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2107 return size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2108 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2109 if sep and self.regs.isRegArray(begin):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2110 return self.regs.regArrays[begin][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2111 if self.regs.isReg(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2112 return self.regs.regs[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2113 return 32
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2114
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2115 def getLastSize(self):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2116 if self.lastSize:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2117 return self.lastSize
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2118 return self.paramSize(self.lastDst)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2119
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2120 def pushScope(self, scope):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2121 self.scopes.append(scope)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2122 self.currentScope = scope
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2123
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2124 def popScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2125 ret = self.scopes.pop()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2126 self.currentScope = self.scopes[-1] if self.scopes else None
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2127 return ret
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2128
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2129 def getRootScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2130 return self.scopes[0]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2131
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2132 def parse(args):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2133 f = args.source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2134 instructions = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2135 subroutines = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2136 registers = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2137 flags = None
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2138 declares = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2139 errors = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2140 info = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2141 line_num = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2142 cur_object = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2143 for line in f:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2144 line_num += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2145 line,_,comment = line.partition('#')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2146 if not line.strip():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2147 continue
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2148 if line[0].isspace():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2149 if not cur_object is None:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2150 sep = True
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2151 parts = []
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2152 while sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2153 before,sep,after = line.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2154 before = before.strip()
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2155 if before:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	2156 parts += [el.strip() for el in before.split(' ') if el.strip()]
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2157 if sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2158 #TODO: deal with escaped quotes
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2159 inside,sep,after = after.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2160 parts.append('"' + inside + '"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2161 line = after
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2162 if type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2163 cur_object[parts[0]] = parts[1:]
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2164 elif type(cur_object) is list:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2165 cur_object.append(' '.join(parts))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2166 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2167 cur_object = cur_object.processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2168
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2169 # if type(cur_object) is Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2170 # if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2171 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2172 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2173 # cur_object.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2174 # elif type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2175 # cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2176 # elif parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2177 # o = Switch(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2178 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2179 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2180 # elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2181 # o = If(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2182 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2183 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2184 # elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2185 # cur_object = cur_object.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2186 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2187 # cur_object.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2188 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2189 errors.append("Orphan instruction on line {0}".format(line_num))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2190 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2191 parts = line.split(' ')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2192 if len(parts) > 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2193 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2194 table,bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2195 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2196 bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2197 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2198 value = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2199 fields = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2200 curbit = len(bitpattern) - 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2201 for char in bitpattern:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2202 value <<= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2203 if char in ('0', '1'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2204 value \|= int(char)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2205 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2206 if char in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2207 fields[char] = (curbit, fields[char][1] + 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2208 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2209 fields[char] = (curbit, 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2210 curbit -= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2211 cur_object = Instruction(value, fields, name.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2212 instructions.setdefault(table, []).append(cur_object)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2213 elif line.strip() == 'regs':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2214 if registers is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2215 registers = Registers()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2216 cur_object = registers
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2217 elif line.strip() == 'info':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2218 cur_object = info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2219 elif line.strip() == 'flags':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2220 if flags is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2221 flags = Flags()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2222 cur_object = flags
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2223 elif line.strip() == 'declare':
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2224 cur_object = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2225 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2226 cur_object = SubRoutine(line.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2227 subroutines[cur_object.name] = cur_object
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2228 if errors:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2229 print(errors)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2230 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2231 p = Program(registers, instructions, subroutines, info, flags)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2232 p.dispatch = args.dispatch
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2233 p.declares = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2234 p.booleans['dynarec'] = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2235 p.booleans['interp'] = True
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2236 if args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2237 for define in args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2238 name,sep,val = define.partition('=')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2239 name = name.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2240 val = val.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2241 if sep:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2242 p.booleans[name] = bool(val)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2243 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2244 p.booleans[name] = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2245
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2246 if 'header' in info:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2247 print('#include "{0}"'.format(info['header'][0]))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2248 p.writeHeader('c', info['header'][0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2249 print('#include "util.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2250 print('#include <stdlib.h>')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2251 print(p.build('c'))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2252
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2253 def main(argv):
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2254 from argparse import ArgumentParser, FileType
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2255 argParser = ArgumentParser(description='CPU emulator DSL compiler')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2256 argParser.add_argument('source', type=FileType('r'))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2257 argParser.add_argument('-D', '--define', action='append')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2258 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2259 parse(argParser.parse_args(argv[1:]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2260
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2261 if __name__ == '__main__':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2262 from sys import argv
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2263 main(argv)

Mercurial > repos > blastem

annotate cpu_dsl.py @ 2585:c730067d5f77