repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 1044:1625555e346e

Properly handle redundant prefixes

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 25 Jul 2016 23:16:04 -0700
parents	3980ef0f6307
children	e0489abfdab0

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	2 Copyright 2013 Michael Pavone
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	5 */
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	9 #include "mem.h"
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	10 #include "util.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	11 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	12 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	13 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	14 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define MODE_UNUSED (MODE_IMMED-1)
854 adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	17 #define MAX_MCYCLE_LENGTH 6
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	19 //#define DO_DEBUG_PRINT
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	20
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	21 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	22 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	23 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	24 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	25 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	26
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	27 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst);
715 1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly Michael Pavone <pavone@retrodev.com> parents: 712 diff changeset	28 void z80_handle_deferred(z80_context * context);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	29
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	30 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	33 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	35 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	39
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	40 uint8_t zf_off(uint8_t flag)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	41 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	42 return offsetof(z80_context, flags) + flag;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	43 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	44
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	45 uint8_t zaf_off(uint8_t flag)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	46 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	47 return offsetof(z80_context, alt_flags) + flag;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	48 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	49
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	50 uint8_t zr_off(uint8_t reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	51 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	52 if (reg > Z80_A) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	53 reg = z80_low_reg(reg);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	54 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	55 return offsetof(z80_context, regs) + reg;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	56 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	57
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	58 uint8_t zar_off(uint8_t reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	59 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	60 if (reg > Z80_A) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	61 reg = z80_low_reg(reg);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	62 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	63 return offsetof(z80_context, alt_regs) + reg;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	64 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	65
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	66 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	67 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	68 if (opts->regs[reg] >= 0) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	69 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	70 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	71 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	72 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	73 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	74
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	75 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	76 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	77 if (opts->regs[reg] >= 0) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	78 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	79 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	80 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	81 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	82 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	83
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	84 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	85 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	86 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	93 ea->mode = MODE_REG_DIRECT;
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	94 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	95 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	96 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	97 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	98 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	99 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	100 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	101 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	102 }
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	103 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	104 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	105 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	106 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	107 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	108 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	109 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	110 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	111 ror_ir(code, 8, ea->base, SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	112 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	113 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	114 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	115 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	116 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	117 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	118 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	120 ea->mode = MODE_REG_DISPLACE8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	121 ea->base = opts->gen.context_reg;
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	122 ea->disp = zr_off(inst->reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	126
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	127 void z80_save_reg(z80inst * inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	129 code_info *code = &opts->gen.code;
716 b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo Michael Pavone <pavone@retrodev.com> parents: 715 diff changeset	130 if (inst->reg == Z80_USE_IMMED \|\| inst->reg == Z80_UNUSED) {
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo Michael Pavone <pavone@retrodev.com> parents: 715 diff changeset	131 return;
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo Michael Pavone <pavone@retrodev.com> parents: 715 diff changeset	132 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	133 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	134 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	135 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	136 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	138 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	140 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	141 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	142 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	143 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	144 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	145 //we can't mix an *H reg with a register that requires the REX prefix
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	146 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	147 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	148 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	149 //temp regs require REX prefix too
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	150 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	151 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	154
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	155 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	157 code_info *code = &opts->gen.code;
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	158 uint8_t size, areg;
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	159 int8_t reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	160 ea->mode = MODE_REG_DIRECT;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	161 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 case Z80_REG:
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	165 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	166 if (inst->reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	167 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	168 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	169 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	170 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	171 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	172 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	173 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	174 } else if(opts->regs[inst->ea_reg] >= 0) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	176 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	177 uint8_t other_reg = opts->regs[inst->reg];
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	178 #ifdef X86_64
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	179 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	180 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	181 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	182 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	183 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	184 #endif
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	185 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	186 } else {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	187 ea->mode = MODE_REG_DISPLACE8;
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	188 ea->base = opts->gen.context_reg;
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	189 ea->disp = zr_off(inst->ea_reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 case Z80_REG_INDIRECT:
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	193 zreg_to_native(opts, inst->ea_reg, areg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	197 //push_r(code, opts->gen.scratch1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	198 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 if (size == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	201 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	203 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	206 //pop_r(code, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	207 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	210 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 case Z80_IMMED_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	217 mov_ir(code, inst->immed, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 if (read) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	220 /*if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	221 push_r(code, opts->gen.scratch1);
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	222 }*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	224 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	226 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	229 //pop_r(code, opts->gen.scratch2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	230 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	233 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	235 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	236 case Z80_IY_DISPLACE:
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	237 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	238 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	242 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	243 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	246 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	248 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	251 //pop_r(code, opts->gen.scratch2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	252 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	255 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	258 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 default:
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	261 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	264
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	265 void z80_save_ea(code_info code, z80inst inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	267 if ((inst->addr_mode & 0x1F) == Z80_REG) {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	268 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	269 if (inst->reg == Z80_IYL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	270 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	271 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	272 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	273 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	274 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	275 }
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	276 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	277 uint8_t other_reg = opts->regs[inst->reg];
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	278 #ifdef X86_64
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	279 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	280 //we can't mix an *H reg with a register that requires the REX prefix
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	281 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	282 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	283 #endif
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	284 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	287
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	288 void z80_save_result(z80_options opts, z80inst inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	290 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	291 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	292 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	293 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	294 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	295 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	296 if (z80_size(inst) == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	297 call(&opts->gen.code, opts->write_8);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	298 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	299 call(&opts->gen.code, opts->write_16_lowfirst);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	300 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	303
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	308
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	309 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	310 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	313
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	314 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	315 {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	316 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	317 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	318 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	319 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	320 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	321 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	322 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	323 puts("--Alternate Regs--");
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	324 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	325 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	326 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	327 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	328 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	329 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	330 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	331 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	332
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	333 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	334 {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	335 uint32_t num_cycles;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	336 host_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	337 uint8_t size;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	338 z80_options *opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	339 uint8_t * start = opts->gen.code.cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	340 code_info *code = &opts->gen.code;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	341 if (!interp) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	342 check_cycles_int(&opts->gen, address);
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	343 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	344 zbreakpoint_patch(context, address, start);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	345 }
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	346 num_cycles = 4 * inst->opcode_bytes;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	347 //TODO: increment R register once for every opcode byte
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	348 #ifdef Z80_LOG_ADDRESS
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	349 log_address(&opts->gen, address, "Z80: %X @ %d\n");
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	350 #endif
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	351 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	354 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	355 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	356 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	357 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	358 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	359 case Z80_REG_INDIRECT:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	360 if (size != SZ_B) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	361 num_cycles += 2;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	362 }
841 58606d16d35c Fix timing of certain variants of LD Michael Pavone <pavone@retrodev.com> parents: 840 diff changeset	363 if (inst->reg == Z80_I \|\| inst->ea_reg == Z80_I \|\| inst->reg == Z80_R \|\| inst->ea_reg == Z80_R) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	364 num_cycles += 1;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	365 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	366 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	367 case Z80_IMMED:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	368 num_cycles += size == SZ_B ? 3 : 6;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	369 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	370 case Z80_IMMED_INDIRECT:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	371 num_cycles += 6;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	372 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	373 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	374 case Z80_IY_DISPLACE:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	375 num_cycles = 8; //3 for displacement, 5 for address addition
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	376 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	377 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	378 cycles(&opts->gen, num_cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	379 if (inst->addr_mode & Z80_DIR) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	380 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	381 translate_z80_reg(inst, &src_op, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	382 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	383 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	384 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	385 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	386 if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	387 if(dst_op.mode == MODE_REG_DISPLACE8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	388 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	389 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	390 mov_rr(code, src_op.base, dst_op.base, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	391 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	392 } else if(src_op.mode == MODE_IMMED) {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	393 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	394 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	395 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	396 mov_ir(code, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	397 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	399 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	400 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	401 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	402 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	403 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	404 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 }
842 ba93a3941300 Set flags for ld a, r Michael Pavone <pavone@retrodev.com> parents: 841 diff changeset	406 if ((inst->ea_reg == Z80_I \|\| inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) {
ba93a3941300 Set flags for ld a, r Michael Pavone <pavone@retrodev.com> parents: 841 diff changeset	407 //ld a, i and ld a, r sets some flags
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	408 cmp_ir(code, 0, dst_op.base, SZ_B);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	409 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	410 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
821 21a69dfb6ee7 Implement half carry for a couple of the trivial cases Michael Pavone <pavone@retrodev.com> parents: 819 diff changeset	411 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	412 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);;
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	413 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	414 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	415 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	416 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	417 z80_save_ea(code, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	418 if (inst->addr_mode & Z80_DIR) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	419 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 case Z80_PUSH:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	423 cycles(&opts->gen, num_cycles + 1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	424 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	425 if (inst->reg == Z80_AF) {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	426 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	427 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	428 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	429 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	430 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	431 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	432 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	433 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	434 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	435 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	436 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	437 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	438 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	439 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	440 zreg_to_native(opts, inst->reg, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	441 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	442 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	443 call(code, opts->write_16_highfirst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	444 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	445 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	446 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 case Z80_POP:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	448 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	449 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	450 call(code, opts->read_16);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	451 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	452 if (inst->reg == Z80_AF) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	453
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	454 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	455 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	456 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	457 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	458 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	459 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	460 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	461 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	462 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	463 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	464 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	465 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	466 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	467 native_to_zreg(opts, opts->gen.scratch1, Z80_A);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	468 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	469 native_to_zreg(opts, opts->gen.scratch1, inst->reg);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	470 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	471 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	472 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	474 case Z80_EX:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	475 cycles(&opts->gen, num_cycles);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	476 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	477 if(inst->reg == Z80_AF) {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	478 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	479 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	480 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	481 native_to_zreg(opts, opts->gen.scratch2, Z80_A);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	482
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	483 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	484 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	485 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	486 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	487 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	488 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	489 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	490 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	491 } else {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	492 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	493 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	494 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	495 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	496 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	497 native_to_zreg(opts, opts->gen.scratch1, Z80_HL);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	498 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	499 }
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	500 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	501 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	502 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	503 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	504 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	505 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	506 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	507 zreg_to_native(opts, inst->reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	508 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	509 native_to_zreg(opts, opts->gen.scratch2, inst->reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	510 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	511 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	512 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	513 cycles(&opts->gen, 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	514 uint8_t high_reg = z80_high_reg(inst->reg);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	515 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	516 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	517 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	518 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	519 //even though some of the upper halves can be used directly
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	520 //the limitations on mixing *H regs with the REX prefix
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	521 //prevent us from taking advantage of it
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	522 uint8_t use_reg = opts->regs[inst->reg];
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	523 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	524 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	525 //restore reg to normal rotation
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	526 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	527 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	528 zreg_to_native(opts, high_reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	529 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	530 native_to_zreg(opts, opts->gen.scratch2, high_reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	531 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	532 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	533 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	534 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	535 cycles(&opts->gen, 2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	536 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	537 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	538 case Z80_EXX:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	539 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	540 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	541 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	542 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	543 native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
840 5822c6e5642f Fix timing of IM instruction Michael Pavone <pavone@retrodev.com> parents: 828 diff changeset	544
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	545 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	546 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	547 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	548 native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
840 5822c6e5642f Fix timing of IM instruction Michael Pavone <pavone@retrodev.com> parents: 828 diff changeset	549
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	550 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	551 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	552 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	553 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	554 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	555 case Z80_LDI: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	556 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	557 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	558 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	559 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	560 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	561 cycles(&opts->gen, 2);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	562 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	563 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	564 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	565 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	566 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	567 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	568 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	569 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	570 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	571 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	572 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	573 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	574 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	575 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	576 }
821 21a69dfb6ee7 Implement half carry for a couple of the trivial cases Michael Pavone <pavone@retrodev.com> parents: 819 diff changeset	577 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	578 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	579 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	580 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	581 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	582 case Z80_LDIR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	583 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	584 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	585 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	586 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	587 call(code, opts->write_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	588 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	589 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	590 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	591 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	592 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	593 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	594 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	595 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	596 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	597 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	598 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	599 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	600 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	601 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	602 }
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	603 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	604 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	605 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	606 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	607 cycles(&opts->gen, 7);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	608 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	609 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	610 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	611 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	612 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	613 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	614 }
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	615 case Z80_LDD: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	616 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	617 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	618 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	619 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	620 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	621 cycles(&opts->gen, 2);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	622 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	623 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	624 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	625 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	626 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	627 if (opts->regs[Z80_HL] >= 0) {
828 22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions. Michael Pavone <pavone@retrodev.com> parents: 821 diff changeset	628 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	629 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	630 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	631 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	632 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	633 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	634 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	635 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	636 }
821 21a69dfb6ee7 Implement half carry for a couple of the trivial cases Michael Pavone <pavone@retrodev.com> parents: 819 diff changeset	637 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	638 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	639 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	640 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	641 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	642 case Z80_LDDR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	643 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	644 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	645 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	646 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	647 call(code, opts->write_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	648 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	649 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	650 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	651 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	652 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	653 if (opts->regs[Z80_HL] >= 0) {
828 22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions. Michael Pavone <pavone@retrodev.com> parents: 821 diff changeset	654 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	655 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	656 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	657 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	658 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	659 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	660 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	661 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	662 }
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	663 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	664 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	665 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	666 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	667 cycles(&opts->gen, 7);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	668 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	669 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	670 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	671 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	672 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	673 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	674 }
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	675 case Z80_CPI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	676 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	677 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	678 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	679 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	680 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	681 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	682 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	683 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	684 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	685 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	686 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	687 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	688 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	689 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	690 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	691 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	692 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	693 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	694 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	695 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	696 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	697 case Z80_CPIR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	698 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	699 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	700 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	701 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	702 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	703 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	704 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	705 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	706 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	707 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	708 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	709 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	710 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	711 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	712 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	713 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	714 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	715 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	716 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	717 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	718 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	719 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	720 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	721 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	722 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	723 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	724 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	725 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	726 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	727 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	728 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	729 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	730 case Z80_CPD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	731 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	732 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	733 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	734 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	735 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	736 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	737 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	738 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	739 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	740 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	741 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	742 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	743 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	744 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	745 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	746 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	747 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	748 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	749 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	750 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	751 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	752 case Z80_CPDR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	753 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	754 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	755 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	756 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	757 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	758 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	759 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	760 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	761 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	762 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	763 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	764 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	765 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	766 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	767 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	768 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	769 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	770 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	771 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	772 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	773 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	774 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	775 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	776 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	777 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	778 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	779 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	780 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	781 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	782 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	783 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	784 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	785 case Z80_ADD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	786 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	787 num_cycles += 8;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	788 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	789 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	790 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	791 num_cycles += 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	792 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	793 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	794 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	795 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	796 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	797 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	798 add_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	799 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	800 add_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	801 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	802 add_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	803 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	804 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	805 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	806 add_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	807 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	808 add_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	809 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	810 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	811 add_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	812 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	813 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	814 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	815 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	816 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	817 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	818 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	819 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	820 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	821 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	822 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	823 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	824 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	825 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	826 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	827 num_cycles += 8;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	828 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	829 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	830 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	831 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	832 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	833 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	834 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	835 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	836 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	837 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	838 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	839 adc_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	840 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	841 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	842 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	843 adc_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	844 }
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	845 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	846 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	847 adc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	848 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	849 adc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	850 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	851 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	852 adc_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	853 }
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	854 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	855 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	856 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	857 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	858 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	859 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	860 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	861 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	862 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	863 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	864 case Z80_SUB:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	865 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	866 num_cycles += 8;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	867 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	868 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	869 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	870 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	871 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	872 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	873 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	874 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	875 sub_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	876 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	877 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	878 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	879 sub_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	880 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	881 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	882 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	883 sub_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	884 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	885 sub_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	886 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	887 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	888 sub_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	889 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	890 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	891 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	892 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	893 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	894 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	895 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	896 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	897 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	898 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	899 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	900 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	901 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	902 num_cycles += 8;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	903 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	904 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	905 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	906 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	907 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	908 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	909 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	910 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	911 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	912 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	913 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	914 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	915 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	916 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	917 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	918 sbb_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	919 }
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	920 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	921 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	922 sbb_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	923 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	924 sbb_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	925 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	926 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	927 sbb_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	928 }
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	929 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	930 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	931 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	932 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	933 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	934 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	935 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	936 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	937 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	938 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	939 case Z80_AND:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	940 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	941 num_cycles += 8;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	942 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	943 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	944 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	945 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	946 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	947 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	948 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	949 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	950 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	951 and_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	952 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	953 and_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	954 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	955 and_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	956 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	957 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	958 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	959 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	960 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	961 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	962 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	963 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	964 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	965 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	966 case Z80_OR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	967 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	968 num_cycles += 8;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	969 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	970 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	971 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	972 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	973 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	974 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	975 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	976 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	977 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	978 or_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	979 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	980 or_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	981 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	982 or_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	983 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	984 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	985 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	986 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	987 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	988 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	989 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	990 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	991 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	992 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	993 case Z80_XOR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	994 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	995 num_cycles += 8;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	996 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	997 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	998 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	999 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1000 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1001 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1002 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1003 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1004 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1005 xor_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1006 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1007 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1008 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1009 xor_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1010 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1011 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1012 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1013 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1014 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1015 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1016 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1017 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1018 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1019 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1020 case Z80_CP:
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1021 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1022 num_cycles += 8;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1023 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1024 num_cycles += 3;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1025 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1026 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1027 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1028 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1029 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1030 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1031 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1032 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1033 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1034 cmp_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1035 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1036 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1037 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1038 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1039 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1040 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1041 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1042 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1043 z80_save_ea(code, inst, opts);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1044 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1045 case Z80_INC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1046 if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1047 num_cycles += 2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1048 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1049 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1050 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1051 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1052 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1053 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1054 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1055 add_ir(code, 1, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1056 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1057 add_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1058 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1059 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1060 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1061 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1062 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1063 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1064 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1065 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1066 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1067 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1068 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1069 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1070 case Z80_DEC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1071 if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1072 num_cycles += 2;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1073 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1074 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1075 translate_z80_reg(inst, &dst_op, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1076 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1077 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1078 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1079 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1080 sub_ir(code, 1, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1081 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1082 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1083 }
840 5822c6e5642f Fix timing of IM instruction Michael Pavone <pavone@retrodev.com> parents: 828 diff changeset	1084
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1085 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1086 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1087 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1088 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1089 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1090 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1091 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1092 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1093 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1094 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1095 break;
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1096 case Z80_DAA:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1097 cycles(&opts->gen, num_cycles);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1098 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1099 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1100 code_ptr corf_low = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1101 jcc(code, CC_NZ, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1102 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1103 and_ir(code, 0xF, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1104 cmp_ir(code, 0xA, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1105
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1106 code_ptr no_corf_low = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1107 jcc(code, CC_C, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1108 *corf_low = code->cur - (corf_low + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1109 mov_ir(code, 6, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1110 //TODO: Deal with edge case of 9 in high nibble
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1111 mov_ir(code, 0x90, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1112 code_ptr after_cmp_set = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1113 jmp(code, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1114
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1115 *no_corf_low = code->cur - (no_corf_low + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1116 mov_ir(code, 0xA0, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1117 *after_cmp_set = code->cur - (after_cmp_set + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1118 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1119 code_ptr corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1120 jcc(code, CC_NZ, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1121 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1122 code_ptr no_corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1123 jcc(code, CC_C, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1124 *corf_high = code->cur - (corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1125 or_ir(code, 0x60, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1126 *no_corf_high = code->cur - (no_corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1127
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1128 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1129 code_ptr not_sub = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1130 jcc(code, CC_Z, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1131 neg_r(code, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1132 *not_sub = code->cur - (not_sub + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1133 add_rr(code, opts->gen.scratch2, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1134 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1135 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1136 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1137 code_ptr no_carry = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1138 jcc(code, CC_NC, code->cur+2);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	1139 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1140 *no_carry = code->cur - (no_carry + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1141 //TODO: Implement half-carry flag
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1142 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1143 case Z80_CPL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1144 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1145 not_r(code, opts->regs[Z80_A], SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1146 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1147 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1148 break;
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1149 case Z80_NEG:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1150 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1151 neg_r(code, opts->regs[Z80_A], SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1152 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1153 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1154 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1155 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1156 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1157 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1158 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1159 case Z80_CCF:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1160 cycles(&opts->gen, num_cycles);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1161 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1162 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1163 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1164 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	1165 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	1166 case Z80_SCF:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1167 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1168 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1169 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1170 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	1171 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1172 case Z80_NOP:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1173 cycles(&opts->gen, num_cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1174 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1175 case Z80_HALT: {
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1176 code_ptr loop_top = code->cur;
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1177 //this isn't terribly efficient, but it's good enough for now
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1178 cycles(&opts->gen, num_cycles);
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1179 check_cycles_int(&opts->gen, address);
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1180 jmp(code, loop_top);
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	1181 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1182 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1183 case Z80_DI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1184 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1185 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1186 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1187 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1188 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	1189 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1190 case Z80_EI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1191 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1192 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1193 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1194 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335 14a937097c2b Some Z80 interrupt fixes Mike Pavone <pavone@retrodev.com> parents: 315 diff changeset	1195 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1196 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1197 call(code, opts->do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	1198 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1199 case Z80_IM:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1200 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1201 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	1202 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1203 case Z80_RLC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1204 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1205 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1206 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1207 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1208 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1209 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1210 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1211 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1212 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1213 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1214 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1215 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1216 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1217 rol_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1218 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1219 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1220 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1221 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1222 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1223 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1224 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1225 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1226 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1227 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1228 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1229 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1230 //rlca does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1231 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1232 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1233 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1234 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1235 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1236 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1237 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1238 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1239 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1240 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1241 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1242 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1243 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1244 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1245 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1246 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1247 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1248 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1249 case Z80_RL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1250 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1251 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1252 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1253 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1254 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1255 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1256 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1257 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1258 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1259 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1260 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1261 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1262 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1263 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1264 rcl_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1265 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1266 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1267 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1268 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1269 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1270 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1271 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1272 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1273 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1274 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1275 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1276 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1277 //rla does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1278 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1279 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1280 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1281 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1282 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1283 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1284 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1285 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1286 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1287 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1288 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1289 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1290 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1291 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1292 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1293 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1294 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1295 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1296 case Z80_RRC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1297 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1298 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1299 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1300 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1301 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1302 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1303 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1304 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1305 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1306 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1307 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1308 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1309 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1310 ror_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1311 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1312 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1313 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1314 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1315 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1316 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1317 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1318 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1319 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1320 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1321 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1322 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1323 //rrca does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1324 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1325 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1326 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1327 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1328 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1329 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1330 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1331 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1332 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1333 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1334 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1335 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1336 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1337 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1338 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1339 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1340 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1341 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1342 case Z80_RR:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1343 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1344 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1345 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1346 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1347 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1348 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1349 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1350 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1351 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1352 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1353 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1354 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1355 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1356 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1357 rcr_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1358 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1359 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1360 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1361 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1362 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1363 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1364 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1365 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1366 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1367 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1368 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1369 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1370 //rra does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1371 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1372 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1373 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1374 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1375 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1376 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1377 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1378 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1379 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1380 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1381 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1382 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1383 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1384 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1385 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1386 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1387 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1388 break;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1389 case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1390 case Z80_SLL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1391 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1392 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1393 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1394 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1395 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1396 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1397 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1398 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1399 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1400 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1401 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1402 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1403 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1404 shl_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1405 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1406 shl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1407 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1408 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1409 if (inst->op == Z80_SLL) {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1410 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1411 or_ir(code, 1, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1412 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1413 or_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1414 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1415 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1416 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1417 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1418 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1419 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1420 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1421 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1422 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1423 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1424 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1425 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1426 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1427 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1428 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1429 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1430 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1431 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1432 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1433 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1434 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1435 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1436 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1437 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1438 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1439 break;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1440 case Z80_SRA:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1441 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1442 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1443 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1444 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1445 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1446 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1447 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1448 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1449 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1450 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1451 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1452 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1453 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1454 sar_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1455 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1456 sar_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1457 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1458 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1459 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1460 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1461 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1462 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1463 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1464 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1465 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1466 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1467 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1468 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1469 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1470 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1471 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1472 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1473 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1474 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1475 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1476 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1477 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1478 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1479 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1480 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1481 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1482 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1483 case Z80_SRL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1484 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1485 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1486 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1487 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1488 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1489 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1490 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1491 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1492 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1493 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1494 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1495 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1496 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1497 shr_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1498 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1499 shr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1500 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1501 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1502 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1503 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1504 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1505 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1506 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1507 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1508 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1509 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1510 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1511 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1512 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1513 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1514 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1515 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1516 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1517 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1518 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1519 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1520 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1521 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1522 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1523 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1524 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1525 break;
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1526 case Z80_RLD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1527 cycles(&opts->gen, num_cycles);
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1528 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1529 call(code, opts->read_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1530 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1531 //After: (HL) = 0x24, A = 0x31
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1532 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1533 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1534 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1535 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1536 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1537 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1538 //opts->gen.scratch1 = 0x0124
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1539 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1540 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1541 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1542 //set flags
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1543 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1544 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1545 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1546 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1547 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1548
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1549 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1550 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1551 call(code, opts->write_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1552 break;
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1553 case Z80_RRD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1554 cycles(&opts->gen, num_cycles);
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1555 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1556 call(code, opts->read_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1557 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1558 //After: (HL) = 0x41, A = 0x32
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1559 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1560 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1561 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1562 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1563 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
967 1eb616b8cbe9 Fix bug in Z80 rrd implementation. This fixes the annoying high pitched wine in Afterburner II. Michael Pavone <pavone@retrodev.com> parents: 966 diff changeset	1564 and_ir(code, 0xF0, opts->gen.scratch2, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1565 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1566 //opts->gen.scratch2 = 0x0040
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1567 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1568 //opts->gen.scratch1 = 0x2041
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1569 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1570 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1571 shr_ir(code, 4, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1572 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1573 //set flags
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1574 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1575 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1576 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1577 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1578 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1579
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1580 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1581 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1582 call(code, opts->write_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1583 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1584 case Z80_BIT: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1585 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1586 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1587 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1588 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1589 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1590 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1591 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737 043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression Michael Pavone <pavone@retrodev.com> parents: 735 diff changeset	1592 src_op.mode = MODE_REG_DIRECT;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1593 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1594 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1595 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1596 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1597 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1598 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1599 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1600 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1601 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1602 cycles(&opts->gen, 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1603 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1604 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1605 bt_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1606 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1607 bt_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1608 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1609 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1610 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1611 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1612 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1613 if (inst->immed == 7) {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1614 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1615 cmp_ir(code, 0, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1616 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1617 cmp_irdisp(code, 0, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1618 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1619 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1620 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1621 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1622 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1623 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1624 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1625 case Z80_SET: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1626 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1627 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1628 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1629 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1630 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1631 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1632 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737 043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression Michael Pavone <pavone@retrodev.com> parents: 735 diff changeset	1633 src_op.mode = MODE_REG_DIRECT;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1634 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1635 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1636 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1637 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1638 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1639 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1640 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1641 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1642 translate_z80_reg(inst, &dst_op, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1643 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1644 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1645 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1646 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1647 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1648 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1649 bts_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1650 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1651 bts_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1652 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1653 if (inst->reg != Z80_USE_IMMED) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1654 if (size == SZ_W) {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1655 #ifdef X86_64
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1656 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1657 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1658 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1659 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1660 } else {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1661 #endif
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1662 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1663 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1664 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1665 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1666 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1667 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1668 #ifdef X86_64
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1669 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1670 #endif
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1671 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1672 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1673 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1674 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1675 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1676 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1677 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1678 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1679 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1680 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1681 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1682 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1683 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1684 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1685 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1686 if ((inst->addr_mode & 0x1F) != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1687 z80_save_result(opts, inst);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1688 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1689 z80_save_reg(inst, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1690 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1691 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1692 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1693 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1694 case Z80_RES: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1695 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1696 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1697 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1698 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1699 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1700 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1701 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737 043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression Michael Pavone <pavone@retrodev.com> parents: 735 diff changeset	1702 src_op.mode = MODE_REG_DIRECT;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1703 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1704 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1705 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1706 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1707 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1708 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1709 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1710 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1711 translate_z80_reg(inst, &dst_op, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1712 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1713 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1714 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1715 cycles(&opts->gen, 1);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1716 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1717 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1718 btr_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1719 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1720 btr_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1721 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1722 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1723 if (size == SZ_W) {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1724 #ifdef X86_64
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1725 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1726 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1727 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1728 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1729 } else {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1730 #endif
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1731 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1732 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1733 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1734 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1735 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1736 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1737 #ifdef X86_64
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1738 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1739 #endif
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1740 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1741 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1742 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1743 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1744 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1745 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1746 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1747 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1748 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1749 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1750 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1751 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1752 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1753 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1754 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1755 if (inst->addr_mode != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1756 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1757 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1758 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1759 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1760 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1761 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1762 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1763 case Z80_JP: {
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	1764 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1765 num_cycles += 6;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1766 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1767 cycles(&opts->gen, num_cycles);
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1768 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1769 code_ptr call_dst = z80_get_native_address(context, inst->immed);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1770 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1771 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1772 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1773 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1774 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1775 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1776 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1777 if (inst->addr_mode == Z80_REG_INDIRECT) {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	1778 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1779 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1780 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1781 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1782 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1783 jmp_r(code, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1784 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1785 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1786 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1787 case Z80_JPCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1788 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1789 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1790 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1791 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1792 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1793 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1794 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1795 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1796 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1797 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1798 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1799 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1800 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1801 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1802 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1803 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1804 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1805 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1806 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1807 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1808 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1809 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1810 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1811 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1812 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1813 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1814 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1815 cycles(&opts->gen, 5);//T States: 5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1816 uint16_t dest_addr = inst->immed;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1817 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1818 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1819 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1820 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1821 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1822 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1823 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1824 *no_jump_off = code->cur - (no_jump_off+1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1825 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1826 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1827 case Z80_JR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1828 cycles(&opts->gen, num_cycles + 8);//T States: 4,3,5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1829 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1830 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1831 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1832 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1833 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1834 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1835 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1836 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1837 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1838 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1839 case Z80_JRCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1840 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1841 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1842 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1843 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1844 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1845 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1846 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1847 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1848 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1849 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1850 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1851 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1852 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1853 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1854 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1855 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1856 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1857 cycles(&opts->gen, 5);//T States: 5
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1858 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1859 code_ptr call_dst = z80_get_native_address(context, dest_addr);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1860 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1861 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1862 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1863 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1864 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1865 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1866 *no_jump_off = code->cur - (no_jump_off+1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1867 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1868 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1869 case Z80_DJNZ: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1870 cycles(&opts->gen, num_cycles + 4);//T States: 5,3
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1871 if (opts->regs[Z80_B] >= 0) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1872 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1873 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1874 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1875 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1876 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1877 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1878 cycles(&opts->gen, 5);//T States: 5
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1879 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1880 code_ptr call_dst = z80_get_native_address(context, dest_addr);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1881 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1882 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1883 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1884 call_dst = code->cur + 256;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1885 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1886 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1887 *no_jump_off = code->cur - (no_jump_off+1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1888 break;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1889 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1890 case Z80_CALL: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1891 cycles(&opts->gen, num_cycles + 7);//T States: 4,3,4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1892 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1893 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1894 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1895 call(code, opts->write_16_highfirst);//T States: 3, 3
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1896 code_ptr call_dst = z80_get_native_address(context, inst->immed);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1897 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1898 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1899 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1900 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1901 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1902 jmp(code, call_dst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1903 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1904 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1905 case Z80_CALLCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1906 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3 (false case)
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1907 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1908 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1909 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1910 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1911 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1912 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1913 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1914 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1915 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1916 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1917 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1918 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1919 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1920 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1921 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1922 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1923 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1924 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1925 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1926 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1927 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1928 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1929 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1930 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1931 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1932 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1933 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1934 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1935 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1936 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1937 call(code, opts->write_16_highfirst);//T States: 3, 3
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1938 code_ptr call_dst = z80_get_native_address(context, inst->immed);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1939 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1940 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1941 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1942 call_dst = code->cur + 256;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1943 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	1944 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1945 *no_call_off = code->cur - (no_call_off+1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1946 break;
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	1947 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1948 case Z80_RET:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1949 cycles(&opts->gen, num_cycles);//T States: 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1950 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1951 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1952 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1953 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1954 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1955 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1956 case Z80_RETCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1957 cycles(&opts->gen, num_cycles + 1);//T States: 5
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1958 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1959 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1960 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1961 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1962 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1963 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1964 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1965 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1966 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1967 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1968 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1969 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1970 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1971 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1972 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1973 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1974 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1975 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1976 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1977 cond = CC_NZ;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1978 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1979 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1980 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1981 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1982 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1983 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1984 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1985 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1986 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1987 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1988 jmp_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1989 *no_call_off = code->cur - (no_call_off+1);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1990 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1991 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1992 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1993 //For some systems, this may need a callback for signalling interrupt routine completion
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1994 cycles(&opts->gen, num_cycles);//T States: 4, 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1995 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1996 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1997 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1998 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1999 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2000 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2001 case Z80_RETN:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2002 cycles(&opts->gen, num_cycles);//T States: 4, 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2003 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2004 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2005 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2006 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2007 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2008 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2009 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2010 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2011 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2012 //RST is basically CALL to an address in page 0
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2013 cycles(&opts->gen, num_cycles + 1);//T States: 5
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2014 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2015 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2016 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2017 call(code, opts->write_16_highfirst);//T States: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2018 code_ptr call_dst = z80_get_native_address(context, inst->immed);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2019 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2020 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2021 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2022 call_dst = code->cur + 256;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2023 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2024 jmp(code, call_dst);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2025 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2026 }
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2027 case Z80_IN:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2028 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2029 num_cycles += 3;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2030 }
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2031 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2032 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2033 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2034 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2035 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2036 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2037 call(code, opts->read_io);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2038 if (inst->addr_mode != Z80_IMMED_INDIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2039 or_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2040 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2041 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2042 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2043 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2044 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2045 }
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2046 if (inst->reg != Z80_UNUSED) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2047 translate_z80_reg(inst, &dst_op, opts);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2048 if (dst_op.mode == MODE_REG_DIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2049 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2050 } else {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2051 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2052 }
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2053 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2054 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2055 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2056 /*case Z80_INI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2057 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2058 case Z80_IND:
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2059 case Z80_INDR:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2060 case Z80_OUT:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2061 if (inst->reg == Z80_A) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2062 num_cycles += 3;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2063 }
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2064 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2065 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2066 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2067 } else {
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2068 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2069 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2070 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2071 translate_z80_reg(inst, &src_op, opts);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2072 if (src_op.mode == MODE_REG_DIRECT) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2073 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2074 } else if (src_op.mode == MODE_IMMED) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2075 mov_ir(code, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2076 } else {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2077 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2078 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2079 call(code, opts->write_io);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2080 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2081 break;
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2082 case Z80_OUTI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2083 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2084 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2085 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2086 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2087 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2088 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2089 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2090 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2091 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2092 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2093 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2094 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2095 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2096 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2097 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2098 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2099 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2100 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2101 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2102 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2103 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2104 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2105 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2106 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2107 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2108 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2109 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2110 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2111 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2112 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2113 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2114 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2115 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2116 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2117 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2118 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2119 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2120 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2121 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2122 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2123 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2124 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2125 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2126 case Z80_OTIR: {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2127 code_ptr start = code->cur;
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2128 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2129 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2130 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2131 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2132 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2133 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2134 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2135 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2136 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2137 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2138 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2139 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2140 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2141 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2142 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2143 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2144 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2145 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2146 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2147 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2148 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2149 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2150 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2151 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2152 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2153 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2154 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2155 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2156 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2157 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2158 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2159 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2160 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2161 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2162 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2163 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2164 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2165 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2166 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2167 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2168 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2169 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2170 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2171 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2172 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2173 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2174 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2175 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2176 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2177 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2178 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2179 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2180 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2181 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2182 case Z80_OUTD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2183 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2184 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2185 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2186 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2187 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2188 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2189 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2190 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2191 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2192 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2193 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2194 //decrement HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2195 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2196 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2197 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2198 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2199 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2200 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2201 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2202 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2203 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2204 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2205 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2206 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2207 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2208 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2209 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2210 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2211 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2212 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2213 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2214 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2215 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2216 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2217 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2218 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2219 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2220 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2221 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2222 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2223 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2224 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2225 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2226 case Z80_OTDR: {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2227 code_ptr start = code->cur;
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2228 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2229 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2230 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2231 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2232 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2233 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2234 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2235 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2236 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2237 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2238 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2239 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2240 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2241 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2242 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2243 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2244 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2245 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2246 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2247 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2248 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2249 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2250 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2251 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2252 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2253 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2254 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2255 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2256 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2257 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2258 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2259 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2260 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2261 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2262 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2263 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2264 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2265 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2266 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2267 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2268 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2269 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2270 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2271 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2272 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2273 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2274 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2275 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2276 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2277 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2278 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2279 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2280 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2281 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2282 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2283 char disbuf[80];
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	2284 z80_disasm(inst, disbuf, address);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2285 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2286 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2287 fclose(f);
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2288 fatal_error("unimplemented Z80 instruction: %s at %X\nZ80 RAM has been saved to zram.bin for debugging", disbuf, address);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2289 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2290 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2291 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2292
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2293 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context)
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2294 {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2295 if (!context->interp_code[opcode]) {
755 7306b3967c51 Cleanup some warnings under clang through a combination of code fixes and supressing specific warnings Michael Pavone <pavone@retrodev.com> parents: 737 diff changeset	2296 if (opcode == 0xCB \|\| (opcode >= 0xDD && (opcode & 0xF) == 0xD)) {
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2297 fatal_error("Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2298 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2299 uint8_t codebuf[8];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2300 memset(codebuf, 0, sizeof(codebuf));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2301 codebuf[0] = opcode;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2302 z80inst inst;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2303 uint8_t * after = z80_decode(codebuf, &inst);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2304 if (after - codebuf > 1) {
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2305 fatal_error("Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2306 }
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2307
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2308 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2309 code_info *code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2310 check_alloc_code(code, ZMAX_NATIVE_SIZE);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2311 context->interp_code[opcode] = code->cur;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2312 translate_z80inst(&inst, context, 0, 1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2313 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2314 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2315 call(code, opts->native_addr);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2316 jmp_r(code, opts->gen.scratch1);
715 1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly Michael Pavone <pavone@retrodev.com> parents: 712 diff changeset	2317 z80_handle_deferred(context);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2318 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2319 return context->interp_code[opcode];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2320 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2321
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2322 code_info z80_make_interp_stub(z80_context * context, uint16_t address)
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2323 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2324 z80_options *opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2325 code_info * code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2326 check_alloc_code(code, 32);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2327 code_info stub = {code->cur, NULL};
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2328 //TODO: make this play well with the breakpoint code
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2329 mov_ir(code, address, opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2330 call(code, opts->read_8);
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2331 //opcode fetch M-cycles have one extra T-state
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2332 cycles(&opts->gen, 1);
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2333 //TODO: increment R
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2334 check_cycles_int(&opts->gen, address);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2335 call(code, opts->gen.save_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2336 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2337 push_r(code, opts->gen.context_reg);
712 382a2b5b70c0 Fix crash bug in Z80 interpreter Michael Pavone <pavone@retrodev.com> parents: 702 diff changeset	2338 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	2339 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2340 pop_r(code, opts->gen.context_reg);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2341 call(code, opts->gen.load_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2342 jmp_r(code, opts->gen.scratch1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2343 stub.last = code->cur;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2344 return stub;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2345 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2346
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2347
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2348 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2349 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2350 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2351 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2352 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2353 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2354 } else {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2355 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2356 map = context->banked_code_map;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2357 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2358 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	2359 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2360 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2361 }
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	2362 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2363 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2364 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2365
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2366 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2367 {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2368 //TODO: Fix for addresses >= 0x4000
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2369 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2370 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2371 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2372 return opts->gen.ram_inst_sizes[0][address & 0x1FFF];
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2373 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2374
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2375 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2376 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2377 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2378 native_map_slot *map;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2379 z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2380 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2381 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2382 map = context->static_code_map;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2383 opts->gen.ram_inst_sizes[0][address] = native_size;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2384 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2385 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2386 } else {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2387 //HERE
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2388 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2389 map = context->banked_code_map;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2390 if (!map->offsets) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2391 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2392 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2393 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2394 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2395 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2396 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2397 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2398 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	2399 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2400 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2401 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2402 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2403 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2404 } else {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2405 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2406 map = context->banked_code_map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2407 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2408 if (!map->offsets) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2409 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2410 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2411 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2412 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2413 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2414 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2415
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2416 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2417
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2418 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2419 {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2420 //TODO: Fixme for address >= 0x4000
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2421 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2422 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2423 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2424 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2425 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2426 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2427 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2428 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2429 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2430 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2431 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2432 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2433 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2434
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2435 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2436 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2437 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2438 if (inst_start != INVALID_INSTRUCTION_START) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2439 code_ptr dst = z80_get_native_address(context, inst_start);
899 07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2440 code_info code = {dst, dst+32, 0};
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2441 z80_options * opts = context->options;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2442 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2443 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2444 call(&code, opts->retrans_stub);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2445 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2446 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2447 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2448
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2449 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2450 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2451 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2452 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2453 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2454 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2455 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2456 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2457 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2458 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2459 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2460 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2461
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2462 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2463 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2464 z80_options * opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2465 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2466 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2467 translate_z80_stream(context, opts->gen.deferred->address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2468 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2469 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2470
559 6b248602ab84 blastem builds and almost works on OS X now Mike Pavone <pavone@retrodev.com> parents: 506 diff changeset	2471 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst");
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	2472 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2473 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2474 char disbuf[80];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2475 z80_options * opts = context->options;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2476 uint8_t orig_size = z80_get_native_inst_size(opts, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2477 code_info *code = &opts->gen.code;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2478 uint8_t after, inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2479 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2480 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2481 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2482 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	2483 z80_disasm(&instbuf, disbuf, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2484 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2485 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2486 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2487 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	2488 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2489 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2490 if (orig_size != ZMAX_NATIVE_SIZE) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	2491 check_alloc_code(code, ZMAX_NATIVE_SIZE);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2492 code_ptr start = code->cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2493 deferred_addr * orig_deferred = opts->gen.deferred;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2494 translate_z80inst(&instbuf, context, address, 0);
644 2d7e84ae818c Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one Michael Pavone <pavone@retrodev.com> parents: 628 diff changeset	2495 /*
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2496 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2497 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2498 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2499 remove_deferred_until(&opts->gen.deferred, orig_deferred);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2500 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2501 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2502 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2503 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2504 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2505 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2506 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2507 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2508 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2509 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2510 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2511 }*/
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2512 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2513 code_info tmp_code = {orig_start, orig_start + 16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2514 jmp(&tmp_code, start);
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	2515 tmp_code = *code;
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	2516 code->cur = start + ZMAX_NATIVE_SIZE;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2517 if (!z80_is_terminal(&instbuf)) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	2518 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst));
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2519 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2520 z80_handle_deferred(context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2521 return start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2522 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2523 code_info tmp_code = *code;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2524 code->cur = orig_start;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2525 code->last = orig_start + ZMAX_NATIVE_SIZE;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2526 translate_z80inst(&instbuf, context, address, 0);
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2527 code_info tmp2 = *code;
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2528 *code = tmp_code;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2529 if (!z80_is_terminal(&instbuf)) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2530
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2531 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2532 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2533 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2534 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2535 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2536 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2537
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2538 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2539 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2540 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2541 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2542 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2543 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2544 z80_options * opts = context->options;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	2545 uint32_t start_address = address;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2546
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2547 do
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2548 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2549 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2550 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2551 do {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2552 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2553 if (existing) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2554 jmp(&opts->gen.code, existing);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2555 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2556 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2557 uint8_t * encoded, *next;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2558 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2559 if (!encoded) {
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2560 code_info stub = z80_make_interp_stub(context, address);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2561 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2562 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2563 }
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2564 //make sure prologue is in a contiguous chunk of code
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2565 check_code_prologue(&opts->gen.code);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2566 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2567 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	2568 z80_disasm(&inst, disbuf, address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2569 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2570 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2571 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2572 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2573 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2574 #endif
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2575 code_ptr start = opts->gen.code.cur;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2576 translate_z80inst(&inst, context, address, 0);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2577 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2578 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	2579 address &= 0xFFFF;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2580 } while (!z80_is_terminal(&inst));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2581 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2582 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2583 address = opts->gen.deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2584 dprintf("defferred address: %X\n", address);
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2585 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2586 } while (opts->gen.deferred);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2587 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2588
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2589 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2590 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2591 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2592
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2593 options->gen.memmap = chunks;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2594 options->gen.memmap_chunks = num_chunks;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2595 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2596 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2597 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2598 options->gen.bus_cycles = 3;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	2599 options->gen.clock_divider = clock_divider;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2600 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2601 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
620 9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken. Michael Pavone <pavone@retrodev.com> parents: 601 diff changeset	2602 options->gen.ram_flags_shift = 7;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2603
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2604 options->flags = 0;
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2605 #ifdef X86_64
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2606 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2607 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2608 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2609 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2610 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2611 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2612 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2613 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2614 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2615 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2616 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2617 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2618 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2619 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2620 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2621 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2622 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2623 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2624 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2625 options->regs[Z80_IY] = R8;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	2626
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2627 options->gen.scratch1 = R13;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2628 options->gen.scratch2 = R14;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2629 #else
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2630 memset(options->regs, -1, sizeof(options->regs));
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2631 options->regs[Z80_A] = RAX;
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	2632 options->regs[Z80_SP] = RBX;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	2633
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2634 options->gen.scratch1 = RCX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2635 options->gen.scratch2 = RDX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2636 #endif
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	2637
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2638 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2639 options->gen.cycles = RBP;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2640 options->gen.limit = RDI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2641
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2642 options->gen.native_code_map = malloc(sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2643 memset(options->gen.native_code_map, 0, sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2644 options->gen.deferred = NULL;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2645 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2646 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2647 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2648
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2649 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2650 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2651
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2652 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2653 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2654 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2655
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2656 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2657 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2658 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2659 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2660 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2661 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2662 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2663 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2664 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2665 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2666 size = SZ_B;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2667 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2668 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2669 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2670 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2671 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2672 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2673 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2674 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2675 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2676 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2677 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2678 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2679 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2680 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2681
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2682 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2683 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2684 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2685 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2686 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2687 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2688 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2689 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2690 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2691 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2692 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2693 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2694 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2695 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2696 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2697 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2698 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2699 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2700 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2701 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2702 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2703 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2704 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2705 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2706 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2707 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2708 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2709 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2710
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2711 options->native_addr = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2712 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2713 push_r(code, options->gen.context_reg);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2714 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D);
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2715 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2716 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2717 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2718 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2719 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2720
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2721 uint32_t tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2722
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2723 options->gen.handle_cycle_limit = code->cur;
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2724 //calculate call/stack adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2725 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2726 call_noalign(code, options->gen.handle_cycle_limit);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2727 uint32_t call_adjust_size = code->cur - options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2728 code->cur = options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2729
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2730 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2731 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2732 jcc(code, CC_B, no_sync);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2733 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2734 call(code, options->save_context_scratch);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2735 tmp_stack_off = code->stack_off;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2736 pop_r(code, RAX); //return address in read/write func
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2737 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2738 pop_r(code, RBX); //return address in translated code
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2739 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2740 sub_ir(code, call_adjust_size, RAX, SZ_PTR); //adjust return address to point to the call + stack adjust that got us here
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2741 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2742 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2743 restore_callee_save_regs(code);
598 faad1927d836 Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80 Michael Pavone <pavone@retrodev.com> parents: 597 diff changeset	2744 *no_sync = code->cur - (no_sync + 1);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2745 //return to caller of z80_run
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2746 retn(code);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2747 code->stack_off = tmp_stack_off;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2748
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2749 options->gen.handle_code_write = (code_ptr)z80_handle_code_write;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2750
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2751 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2752 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2753
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2754 code_ptr skip_int = code->cur;
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2755 //calculate adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2756 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2757 uint32_t adjust_size = code->cur - skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2758 code->cur = skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2759
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2760 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2761 code_ptr skip_sync = code->cur + 1;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2762 jcc(code, CC_B, skip_sync);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2763 //save PC
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2764 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2765 options->do_sync = code->cur;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2766 call(code, options->gen.save_context);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2767 tmp_stack_off = code->stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2768 //pop return address off the stack and save for resume later
898 2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	2769 //pop_rind(code, options->gen.context_reg);
2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	2770 pop_r(code, RAX);
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	2771 add_ir(code, adjust_size, RAX, SZ_PTR);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2772 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
898 2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	2773 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	2774
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2775 //restore callee saved registers
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2776 restore_callee_save_regs(code);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2777 //return to caller of z80_run
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2778 *skip_sync = code->cur - (skip_sync+1);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2779 retn(code);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2780 code->stack_off = tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2781
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2782 options->gen.handle_cycle_limit_int = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2783 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2784 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2785 //set limit to the cycle limit
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2786 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2787 //disable interrupts
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2788 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2789 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2790 cycles(&options->gen, 7);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2791 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2792 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2793 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2794 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2795 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2796 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2797 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2798 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2799 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2800 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2801 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2802 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2803 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2804 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2805 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2806 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2807 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2808 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2809 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2810 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2811 //dispose of return address as we'll be jumping somewhere else
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2812 add_ir(code, 16, RSP, SZ_PTR);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2813 //TODO: Support interrupt mode 0 and 2
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2814 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2815 call(code, options->native_addr);
663 7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	2816 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2817 tmp_stack_off = code->stack_off;
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2818 restore_callee_save_regs(code);
663 7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	2819 //return to caller of z80_run to sync
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	2820 retn(code);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2821 code->stack_off = tmp_stack_off;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2822
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2823 //HACK
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2824 options->gen.address_size = SZ_D;
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2825 options->gen.address_mask = 0xFF;
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2826 options->read_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, READ_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2827 options->write_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, WRITE_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2828 options->gen.address_size = SZ_W;
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	2829 options->gen.address_mask = 0xFFFF;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2830
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2831 options->read_16 = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2832 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2833 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2834 //TODO: figure out how to handle the extra wait state for word reads to bank area
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2835 //may also need special handling to avoid too much stack depth when access is blocked
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2836 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2837 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2838 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2839 #ifndef X86_64
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2840 //scratch 2 is a caller save register in 32-bit builds and may be clobbered by something called from the read8 fun
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2841 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2842 #endif
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2843 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2844 add_ir(code, 1, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2845 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2846 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2847 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2848 shl_ir(code, 8, options->gen.scratch1, SZ_W);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2849 #ifdef X86_64
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2850 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2851 #else
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2852 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2853 #endif
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2854 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2855
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2856 options->write_16_highfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2857 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2858 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2859 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2860 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2861 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2862 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2863 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2864 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2865 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2866 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2867 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2868 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2869 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2870 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2871
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2872 options->write_16_lowfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2873 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2874 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2875 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2876 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2877 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2878 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2879 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2880 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2881 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2882 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2883 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2884 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2885 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2886 retn(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2887
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2888 options->retrans_stub = code->cur;
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2889 tmp_stack_off = code->stack_off;
899 07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2890 //calculate size of patch
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2891 mov_ir(code, 0x7FFF, options->gen.scratch1, SZ_D);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2892 code->stack_off += sizeof(void *);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2893 if (code->stack_off & 0xF) {
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2894 sub_ir(code, 16 - (code->stack_off & 0xF), RSP, SZ_PTR);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2895 }
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2896 call_noalign(code, options->retrans_stub);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2897 uint32_t patch_size = code->cur - options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2898 code->cur = options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2899 code->stack_off = tmp_stack_off;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2900
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2901 //pop return address
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2902 pop_r(code, options->gen.scratch2);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2903 add_ir(code, 16-sizeof(void*), RSP, SZ_PTR);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2904 code->stack_off = tmp_stack_off;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2905 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2906 //adjust pointer before move and call instructions that got us here
899 07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2907 sub_ir(code, patch_size, options->gen.scratch2, SZ_PTR);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2908 push_r(code, options->gen.context_reg);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	2909 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2910 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2911 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2912 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2913 jmp_r(code, options->gen.scratch1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2914
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2915 options->run = (z80_run_fun)code->cur;
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2916 tmp_stack_off = code->stack_off;
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	2917 save_callee_save_regs(code);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	2918 #ifdef X86_64
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2919 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	2920 #else
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	2921 mov_rdispr(code, RSP, 5 * sizeof(int32_t), options->gen.context_reg, SZ_PTR);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	2922 #endif
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2923 call(code, options->load_context_scratch);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2924 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2925 code_ptr no_extra = code->cur+1;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2926 jcc(code, CC_Z, no_extra);
898 2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	2927 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2928 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc));
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2929 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2930 *no_extra = code->cur - (no_extra + 1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2931 jmp_rind(code, options->gen.context_reg);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	2932 code->stack_off = tmp_stack_off;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2933 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2934
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2935 void init_z80_context(z80_context * context, z80_options * options)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2936 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2937 memset(context, 0, sizeof(*context));
360 c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error Mike Pavone <pavone@retrodev.com> parents: 335 diff changeset	2938 context->static_code_map = malloc(sizeof(*context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2939 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2940 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2941 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2942 context->banked_code_map = malloc(sizeof(native_map_slot));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2943 memset(context->banked_code_map, 0, sizeof(native_map_slot));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2944 context->options = options;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2945 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2946 context->int_pulse_start = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2947 context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2948 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2949
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2950 void z80_run(z80_context * context, uint32_t target_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2951 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2952 if (context->reset \|\| context->busack) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2953 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2954 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2955 if (context->current_cycle < target_cycle) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2956 //busreq is sampled at the end of an m-cycle
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2957 //we can approximate that by running for a single m-cycle after a bus request
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2958 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2959 if (!context->native_pc) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2960 context->native_pc = z80_get_native_address_trans(context, context->pc);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2961 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2962 while (context->current_cycle < context->sync_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2963 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2964 if (context->int_pulse_end < context->current_cycle \|\| context->int_pulse_end == CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2965 z80_next_int_pulse(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2966 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2967 if (context->iff1) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2968 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2969 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2970 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2971 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2972 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
670 f4f3e74b0ce6 Restore Z80 interrupt pulse duration and make a small improvement to debug print output Michael Pavone <pavone@retrodev.com> parents: 668 diff changeset	2973 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end);
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2974 context->options->run(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2975 dprintf("Z80 ran to cycle %d\n", context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2976 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2977 if (context->busreq) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2978 context->busack = 1;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2979 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2980 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2981 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2982 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2983 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2984
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2985 void z80_options_free(z80_options *opts)
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2986 {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2987 free(opts->gen.native_code_map);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2988 free(opts->gen.ram_inst_sizes);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2989 free(opts);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2990 }
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	2991
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2992 void z80_assert_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2993 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2994 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2995 context->reset = 1;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2996 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2997
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2998 void z80_clear_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2999 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3000 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3001 if (context->reset) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3002 //TODO: Handle case where reset is not asserted long enough
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3003 context->im = 0;
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3004 context->iff1 = context->iff2 = 0;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3005 context->native_pc = NULL;
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3006 context->extra_pc = NULL;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3007 context->pc = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3008 context->reset = 0;
676 41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3009 if (context->busreq) {
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3010 //TODO: Figure out appropriate delay
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3011 context->busack = 1;
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3012 }
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3013 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3014 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3015
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3016 void z80_assert_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3017 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3018 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3019 context->busreq = 1;
854 adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3020 //this is an imperfect aproximation since most M-cycles take less tstates than the max
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3021 //and a short 3-tstate m-cycle can take an unbounded number due to wait states
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3022 if (context->current_cycle - cycle > MAX_MCYCLE_LENGTH * context->options->gen.clock_divider) {
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3023 context->busack = 1;
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3024 }
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3025 }
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3026
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3027 void z80_clear_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3028 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3029 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3030 context->busreq = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3031 context->busack = 0;
844 74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests Michael Pavone <pavone@retrodev.com> parents: 842 diff changeset	3032 //there appears to be at least a 1 Z80 cycle delay between busreq
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests Michael Pavone <pavone@retrodev.com> parents: 842 diff changeset	3033 //being released and resumption of execution
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests Michael Pavone <pavone@retrodev.com> parents: 842 diff changeset	3034 context->current_cycle += context->options->gen.clock_divider;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3035 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3036
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3037 uint8_t z80_get_busack(z80_context * context, uint32_t cycle)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3038 {
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3039 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3040 return context->busack;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3041 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3042
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3043 void z80_adjust_cycles(z80_context * context, uint32_t deduction)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3044 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3045 if (context->current_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3046 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3047 context->current_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3048 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3049 context->current_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3050 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3051 if (context->int_enable_cycle != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3052 if (context->int_enable_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3053 context->int_enable_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3054 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3055 context->int_enable_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3056 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3057 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3058 if (context->int_pulse_start != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3059 if (context->int_pulse_end < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3060 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3061 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3062 context->int_pulse_end -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3063 if (context->int_pulse_start < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3064 context->int_pulse_start = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3065 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3066 context->int_pulse_start -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3067 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3068 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3069 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3070 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3071
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3072 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3073 {
966 f765c2fc7508 Fix crash bug in Z80 debugger introduced with stack alignment changes Michael Pavone <pavone@retrodev.com> parents: 900 diff changeset	3074 code_info code = {dst, dst+32};
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	3075 mov_ir(&code, address, context->options->gen.scratch1, SZ_W);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3076 call(&code, context->bp_stub);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3077 return code.cur-dst;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3078 }
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3079
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3080 void zcreate_stub(z80_context * context)
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3081 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3082 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3083 code_info *code = &opts->gen.code;
894 a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted. Michael Pavone <pavone@retrodev.com> parents: 884 diff changeset	3084 uint32_t start_stack_off = code->stack_off;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3085 check_code_prologue(code);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3086 context->bp_stub = code->cur;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3087
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3088 //Calculate length of prologue
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3089 check_cycles_int(&opts->gen, 0);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3090 int check_int_size = code->cur-context->bp_stub;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3091 code->cur = context->bp_stub;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3092
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3093 //Calculate length of patch
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3094 int patch_size = zbreakpoint_patch(context, 0, code->cur);
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3095
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3096 //Save context and call breakpoint handler
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3097 call(code, opts->gen.save_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3098 push_r(code, opts->gen.scratch1);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	3099 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	3100 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3101 //Restore context
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3102 call(code, opts->gen.load_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3103 pop_r(code, opts->gen.scratch1);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3104 //do prologue stuff
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3105 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3106 uint8_t * jmp_off = code->cur+1;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3107 jcc(code, CC_NC, code->cur + 7);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3108 pop_r(code, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	3109 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3110 push_r(code, opts->gen.scratch1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3111 jmp(code, opts->gen.handle_cycle_limit_int);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3112 *jmp_off = code->cur - (jmp_off+1);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3113 //jump back to body of translated instruction
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3114 pop_r(code, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	3115 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3116 jmp_r(code, opts->gen.scratch1);
894 a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted. Michael Pavone <pavone@retrodev.com> parents: 884 diff changeset	3117 code->stack_off = start_stack_off;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3118 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3119
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3120 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3121 {
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3122 context->bp_handler = bp_handler;
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3123 uint8_t bit = 1 << (address % 8);
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3124 if (!(bit & context->breakpoint_flags[address / 8])) {
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3125 context->breakpoint_flags[address / 8] \|= bit;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3126 if (!context->bp_stub) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3127 zcreate_stub(context);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3128 }
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3129 uint8_t * native = z80_get_native_address(context, address);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3130 if (native) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3131 zbreakpoint_patch(context, address, native);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3132 }
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3133 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3134 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3135
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3136 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3137 {
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3138 context->breakpoint_flags[address / 8] &= ~(1 << (address % 8));
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3139 uint8_t * native = z80_get_native_address(context, address);
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3140 if (native) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3141 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3142 code_info tmp_code = opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3143 opts->gen.code.cur = native;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3144 opts->gen.code.last = native + 16;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3145 check_cycles_int(&opts->gen, address);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3146 opts->gen.code = tmp_code;
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	3147 }
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3148 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3149

Mercurial > repos > blastem

annotate z80_to_x86.c @ 1044:1625555e346e