repos/blastem: vdp.c annotate

annotate vdp.c @ 470:541c1ae8abf3

Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.

author	Mike Pavone <pavone@retrodev.com>
date	Fri, 13 Sep 2013 19:22:46 -0700
parents	140af5509ce7
children	f065769836e8

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	2 Copyright 2013 Michael Pavone
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	5 */
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "vdp.h"
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	7 #include "blastem.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include <stdlib.h>
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <string.h>
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	10 #include "render.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define NTSC_ACTIVE 225
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 #define PAL_ACTIVE 241
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define BUF_BIT_PRIORITY 0x40
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MAP_BIT_PRIORITY 0x8000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define MAP_BIT_H_FLIP 0x800
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define MAP_BIT_V_FLIP 0x1000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	19 #define SCROLL_BUFFER_SIZE 32
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	22
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	23 #define FIFO_SIZE 4
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	24
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	25 #define MCLKS_SLOT_H40 16
bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	26 #define MCLKS_SLOT_H32 20
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	27 #define VINT_CYCLE_H40 (21MCLKS_SLOT_H40+332+9MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	28 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	29 #define HSYNC_SLOT_H40 21
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	30 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332)
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	31 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17)
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	32 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32)
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	33 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4)
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	34 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	35 #define FIFO_LATENCY 3
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	36
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	37 int32_t color_map[1 << 12];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	38 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	39
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	40 uint8_t debug_base[][3] = {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	41 {127, 127, 127}, //BG
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	42 {0, 0, 127}, //A
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	43 {127, 0, 0}, //Window
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	44 {0, 127, 0}, //B
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	45 {127, 0, 127} //Sprites
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	46 };
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	47
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	48 uint8_t color_map_init_done;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	49
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 void init_vdp_context(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 {
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	52 memset(context, 0, sizeof(*context));
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 context->vdpmem = malloc(VRAM_SIZE);
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	54 memset(context->vdpmem, 0, VRAM_SIZE);
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	55 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8));
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	56 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8));
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	57 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8));
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	58 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8));
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	59 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	60 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	62 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	63 context->sprite_draws = MAX_DRAWS;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	64 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	65 context->fifo_end = context->fifo_cur + FIFO_SIZE;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	66 context->b32 = render_depth() == 32;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	67 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	68 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	69 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	70 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	71 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	72 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	73 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	74 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	75 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	76 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	77 r = levels[((color >> 1) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	78 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	79 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	80 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	81 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	82 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	83 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	84 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	85 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	86 }
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	87 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	88 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	89 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	90 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	91 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	92 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	93 uint8_t r,g,b;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	94 b = debug_base[src][0];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	95 g = debug_base[src][1];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	96 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	97 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	98 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	99 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	100 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	101 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	102 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	103 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	104 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	105 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	106 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	107 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	108 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	109 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	110 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	111 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	112 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	113 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	114 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	115 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	116 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	117 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	118 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	119 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	120 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	121 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	122 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	123 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	124 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	125 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	126 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	127 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	129
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	130 int is_refresh(vdp_context * context, uint32_t slot)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	131 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	132 if (context->latched_mode & BIT_H40) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	133 return (slot == 37 \|\| slot == 69 \|\| slot == 102 \|\| slot == 133 \|\| slot == 165 \|\| slot == 197 \|\| slot >= 210);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	134 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	135 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	136 //These numbers are guesses based on H40 numbers
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	137 return (slot == 24 \|\| slot == 56 \|\| slot == 88 \|\| slot == 120 \|\| slot == 152);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	138 //The numbers below are the refresh slots during active display
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	139 //return (slot == 66 \|\| slot == 98 \|\| slot == 130 \|\| slot == 162);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	140 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	141 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	142
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	143 void render_sprite_cells(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 {
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	145 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	146 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	147
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 }
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	157 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	158 context->cur_slot--;
143 e5487ef04619 Fix infinite loop bug in sprite rendering Mike Pavone <pavone@retrodev.com> parents: 142 diff changeset	159 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	160 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 context->linebuf[x] = (context->vdpmem[address] >> 4) \| d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 x += dir;
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	164 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 context->linebuf[x] = (context->vdpmem[address] & 0xF) \| d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	171
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	172 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	173 {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	174 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	175 uint16_t current_index = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	176 uint8_t count = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	177 do {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	178 uint16_t address = current_index * 8 + sat_address;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	179 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	180 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	181 int16_t y = ((context->vdpmem[address] & 0x3) << 8 \| context->vdpmem[address+1]) & 0x1FF;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	182 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 \| context->vdpmem[address + 7]) & 0x1FF;
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	183 uint16_t link = context->vdpmem[address+3] & 0x7F;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	184 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	185 uint8_t pri = context->vdpmem[address + 4] >> 7;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	186 uint16_t pattern = ((context->vdpmem[address + 4] << 8 \| context->vdpmem[address + 5]) & 0x7FF) << 5;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	187 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	188 current_index = link;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	189 count++;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	190 } while (current_index != 0 && count < 80);
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	191 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	192
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	193 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	194 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	195 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	196 printf("Mode Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	197 "00: %.2X \| H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	198 "01: %.2X \| Display %s, V-ints %s, Height: %d, Mode %d\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	199 "0B: %.2X \| E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	200 "0C: %.2X \| Width: %d, Shadow/Highlight: %s\n",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	201 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0,
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	202 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	203 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	204 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	205 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	206 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	207 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	208 printf("\nTable Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	209 "02: %.2X \| Scroll A Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	210 "03: %.2X \| Window Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	211 "04: %.2X \| Scroll B Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	212 "05: %.2X \| Sprite Attribute Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	213 "0D: %.2X \| HScroll Data Table: $%.4X\n",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	214 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	215 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	216 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	217 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	218 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10);
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	219 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	220 printf("\nMisc Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	221 "07: %.2X \| Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	222 "0A: %.2X \| H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	223 "0F: %.2X \| Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	224 "10: %.2X \| Scroll A/B Size: %sx%s\n",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	225 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F,
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	226 context->regs[REG_HINT], context->regs[REG_HINT],
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	227 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	228 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
438 b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	229 printf("\nInternal Group\n"
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	230 "Address: %X\n"
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	231 "CD: %X\n"
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	232 "Pending: %s\n",
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	233 context->address, context->cd, (context->flags & FLAG_PENDING) ? "true" : "false");
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	234
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	235 //TODO: Window Group, DMA Group
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	236 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	237
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 void scan_sprite_table(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 if (context->sprite_index && context->slot_counter) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 line &= 0xFF;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	243 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	244 uint8_t height_mult;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	245 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	246 line *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	247 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	248 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	249 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	250 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	251 ymin = 256;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	252 height_mult = 16;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	253 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	254 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	255 ymin = 128;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	256 height_mult = 8;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	257 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 context->sprite_index &= 0x7F;
38 898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	259 if (context->latched_mode & BIT_H40) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	260 if (context->sprite_index >= MAX_SPRITES_FRAME) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	261 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	262 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	263 }
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	264 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	265 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	266 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	267 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 //TODO: Read from SAT cache rather than from VRAM
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 uint16_t address = context->sprite_index * 8 + sat_address;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	271 line += ymin;
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	272 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 \| context->vdpmem[address+1]) & ymask;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	273 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	274 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	275 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	276 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	279 context->sprite_info_list[context->slot_counter].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 context->sprite_index = context->vdpmem[address+3] & 0x7F;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 if (context->sprite_index && context->slot_counter)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 address = context->sprite_index * 8 + sat_address;
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	285 y = ((context->vdpmem[address] & 0x3) << 8 \| context->vdpmem[address+1]) & ymask;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	286 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	287 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	288 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	289 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	292 context->sprite_info_list[context->slot_counter].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 }
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	294 context->sprite_index = context->vdpmem[address+3] & 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	298
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 void read_sprite_x(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	301 if (context->cur_slot >= context->slot_counter) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	302 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	303 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	304 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	305 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	306 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	307 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	308 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	309 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	310 line *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	311 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	312 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	313 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	314 height *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	315 }
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	316 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	317 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) \| context->vdpmem[att_addr+1];
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	318 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	319 uint8_t row;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	320 if (tileinfo & MAP_BIT_V_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	321 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	322 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	323 row = line-context->sprite_info_list[context->cur_slot].y;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	324 }
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	325 uint16_t address;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	326 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	327 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	328 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	329 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	330 }
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	331 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 \| context->vdpmem[att_addr + 3]) & 0x1FF;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	332 if (x) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	333 context->flags \|= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	334 } else if(context->flags & (FLAG_CAN_MASK \| FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	335 context->flags \|= FLAG_MASKED;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	336 }
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	337
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	338 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	339 int16_t i;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	340 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	341 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	342 --context->sprite_draws;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	343 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	344 }
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	345 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	346 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	347 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	348 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	349 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	350 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	351 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	352 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	353 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	354 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	355 //printf("Sprite %d \| x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35 233c7737c152 Small fix to overflow flag Mike Pavone <pavone@retrodev.com> parents: 34 diff changeset	356 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	357 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	358 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	359 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	360 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	361 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	362 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	363 }
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	364 if (i < width) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	365 context->flags \|= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	366 }
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	367 context->cur_slot--;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	369 context->flags \|= FLAG_DOT_OFLOW;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	373
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	374 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	375 {
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	376 uint16_t addr = (address/2) & (CRAM_SIZE-1);
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	377 context->cram[addr] = value;
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	378 context->colors[addr] = color_map[value & 0xEEE];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	379 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) \| FBUF_SHADOW];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	380 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) \| FBUF_HILIGHT];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	381 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	382
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	383 #define VRAM_READ 0
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	384 #define VRAM_WRITE 1
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	385 #define CRAM_READ 8
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	386 #define CRAM_WRITE 3
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	387 #define VSRAM_READ 4
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	388 #define VSRAM_WRITE 5
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	389 #define DMA_START 0x20
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	390
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	391 void external_slot(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	392 {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	393 fifo_entry * start = (context->fifo_end - FIFO_SIZE);
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	394 if (context->flags2 & FLAG2_READ_PENDING) {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	395 context->flags2 &= ~FLAG2_READ_PENDING;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	396 context->flags \|= FLAG_UNUSED_SLOT;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	397 return;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	398 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	399 if (context->fifo_cur != start && start->cycle <= context->cycles) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	400 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	401 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	402 case VRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	403 if (start->partial) {
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	404 printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	405 context->last_fifo_val = start->value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	406 context->vdpmem[start->address ^ 1] = start->value;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	407 } else {
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	408 printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	409 context->vdpmem[start->address] = start->value >> 8;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	410 start->partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	411 //skip auto-increment and removal of entry from fifo
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	412 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	413 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	414 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	415 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	416 //printf("CRAM Write \| %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	417 write_cram(context, start->address, start->value);
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	418 context->last_fifo_val = start->value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	419 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	420 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	421 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	422 if (((start->address/2) & 63) < VSRAM_SIZE) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	423 //printf("VSRAM Write: %X to %X\n", start->value, context->address);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	424 context->vsram[(start->address/2) & 63] = start->value;
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	425 context->last_fifo_val = start->value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	426 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	427
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	428 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	429 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	430 fifo_entry * cur = start+1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	431 if (cur < context->fifo_cur) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	432 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur));
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	433 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	434 context->fifo_cur -= 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	435 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	436 context->flags \|= FLAG_UNUSED_SLOT;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	437 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	438 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	439
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	440 void run_dma_src(vdp_context * context, uint32_t slot)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	441 {
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	442 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	443 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	444 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	445 if (context->fifo_cur == context->fifo_end) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	446 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	447 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	448 uint16_t read_val;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	449 uint8_t ran_source = 0, partial = 0;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	450 uint16_t dma_len;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	451 switch(context->regs[REG_DMASRC_H] & 0xC0)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	452 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	453 //68K -> VDP
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	454 case 0:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	455 case 0x40:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	456 if (!slot \|\| !is_refresh(context, slot-1)) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	457 read_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) \| (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	458 ran_source = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	459 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	460 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	461 //Copy
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	462 case 0xC0:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	463 if (context->flags & FLAG_UNUSED_SLOT) {
131 8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances Mike Pavone <pavone@retrodev.com> parents: 109 diff changeset	464 switch(context->dma_cd & 0xF)
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	465 {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	466 case VRAM_WRITE:
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	467 read_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]];
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	468 break;
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	469 case CRAM_WRITE:
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	470 read_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)];
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	471 break;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	472 case VSRAM_WRITE:
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	473 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	474 read_val = context->vsram[context->regs[REG_DMASRC_L] & 63];
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	475 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	476 read_val = 0;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	477 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	478 break;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	479 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	480 ran_source = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	481 context->flags &= ~FLAG_UNUSED_SLOT;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	482 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	483 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	484 case 0x80:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	485 read_val = (context->cd & 0xF) == VRAM_WRITE ? context->last_write_val >> 8 : context->last_write_val;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	486 partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	487 ran_source = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	488 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	489 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	490
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	491 if (ran_source) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	492 context->fifo_cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	493 context->fifo_cur->address = context->address;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	494 context->fifo_cur->value = read_val;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	495 context->fifo_cur->cd = context->cd;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	496 context->fifo_cur->partial = partial;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	497 context->fifo_cur++;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	498 context->regs[REG_DMASRC_L] += 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	499 if (!context->regs[REG_DMASRC_L]) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	500 context->regs[REG_DMASRC_M] += 1;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	501 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	502 context->address += context->regs[REG_AUTOINC];
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	503 dma_len = ((context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L]) - 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	504 context->regs[REG_DMALEN_H] = dma_len >> 8;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	505 context->regs[REG_DMALEN_L] = dma_len;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	506 if (!dma_len) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	507 //printf("DMA end at cycle %d\n", context->cycles);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	508 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	509 context->cd &= 0xF;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	510 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	511 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	512 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	513
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	514 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	515 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	516
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	517 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	519 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	520 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	521 line *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	522 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	523 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	524 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	525 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	526 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	527 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	528 } else {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	529 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	530 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	531 vscroll_shift = 3;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	532 }
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	533 if (!vsram_off) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	534 uint16_t left_col, right_col;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	535 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	536 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	537 right_col = 42;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	538 } else {
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	539 left_col = 0;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	540 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	541 if (right_col) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	542 right_col += 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	543 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	544 }
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	545 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	546 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	547 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	548 bottom_line = context->double_res ? 481 : 241;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	549 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	550 top_line = 0;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	551 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	552 }
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	553 if ((column >= left_col && column < right_col) \|\| (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	554 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	555 uint16_t line_offset, offset, mask;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	556 if (context->latched_mode & BIT_H40) {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	557 address &= 0xF000;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	558 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	559 mask = 0x7F;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	560
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	561 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	562 address &= 0xF800;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	563 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	564 mask = 0x3F;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	565 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	566 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	567 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	568 mask \|= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	569 }
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	570 offset = address + line_offset + (((column - 2) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	571 context->col_1 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	572 //printf("Window \| top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	573 offset = address + line_offset + (((column - 1) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	574 context->col_2 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	575 context->v_offset = (line) & v_offset_mask;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	576 context->flags \|= FLAG_WINDOW;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	577 return;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	578 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	579 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	580 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	581 uint16_t vscroll;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	582 switch(context->regs[REG_SCROLL] & 0x30)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	583 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	584 case 0:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	585 vscroll = 0xFF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	586 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	587 case 0x10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	588 vscroll = 0x1FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	589 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	590 case 0x20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	591 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	592 vscroll = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	593 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	594 case 0x30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	595 vscroll = 0x3FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	596 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	597 }
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	598 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	599 vscroll <<= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	600 vscroll \|= 1;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	601 }
454 e9b6fe443bf2 Fix per-column scrolling bug Mike Pavone <pavone@retrodev.com> parents: 453 diff changeset	602 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? (column-2)&63 : 0) + vsram_off] + line);
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	603 context->v_offset = vscroll & v_offset_mask;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	604 //printf("%s \| line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	605 vscroll >>= vscroll_shift;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	606 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	607 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	608 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	609 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	610 case 0:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	611 hscroll_mask = 0x1F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	612 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	613 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	614 case 0x1:
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	615 hscroll_mask = 0x3F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	616 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	617 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	618 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	619 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	620 hscroll_mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	621 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	622 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	623 case 0x3:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	624 hscroll_mask = 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	625 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	626 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	627 }
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	628 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	629 for (int i = 0; i < 2; i++) {
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	630 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	631 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	632 //printf("%s \| line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	633 uint16_t col_val = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	634 if (i) {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	635 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	636 } else {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	637 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	638 }
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	639 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	640 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	641
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	642 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	643 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	644 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	645 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	646
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	647 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	648 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	649 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	650 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	651
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	652 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	653 {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	654 uint16_t address;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	655 uint8_t shift, add;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	656 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	657 address = ((col & 0x3FF) << 6);
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	658 shift = 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	659 add = context->framebuf != context->oddbuf ? 1 : 0;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	660 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	661 address = ((col & 0x7FF) << 5);
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	662 shift = 0;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	663 add = 0;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	664 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	665 if (col & MAP_BIT_V_FLIP) {
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	666 address += 28 - 4 * context->v_offset/((context->v_offset << shift) + add)/;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	667 } else {
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	668 address += 4 * context->v_offset/((context->v_offset << shift) + add)/;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	669 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	670 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	671 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	672 if (col & MAP_BIT_H_FLIP) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	673 offset += 7;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	674 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	675 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	676 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	677 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	678 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	679 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	680 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	681 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] >> 4);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	682 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	683 offset &= SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	684 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] & 0xF);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	685 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	686 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	687 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	688 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	689
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	690 void render_map_1(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	691 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	692 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	693 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	694
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	695 void render_map_2(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	696 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	697 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	698 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	699
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	700 void render_map_3(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	701 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	702 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	703 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	704
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	705 void render_map_output(uint32_t line, int32_t col, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	706 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	707 if (line >= 240) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	708 return;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	709 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	710 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	711 uint16_t *dst;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	712 uint32_t *dst32;
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	713 uint8_t sprite_buf, plane_a, *plane_b;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	714 int plane_a_off, plane_b_off;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	715 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	716 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	717 col-=2;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	718 if (context->b32) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	719 dst32 = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	720 dst32 += line * 320 + col * 8;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	721 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	722 dst = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	723 dst += line * 320 + col * 8;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	724 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	725 sprite_buf = context->linebuf + col * 8;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	726 uint8_t a_src, src;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	727 if (context->flags & FLAG_WINDOW) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	728 plane_a_off = context->buf_a_off;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	729 a_src = DBG_SRC_W;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	730 } else {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	731 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	732 a_src = DBG_SRC_A;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	733 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	734 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
30 03f9bb57cc54 Small cleanup Mike Pavone <pavone@retrodev.com> parents: 29 diff changeset	735 //printf("A \| tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	736
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	737 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	738 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	739 uint8_t pixel;
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	740 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	741 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	742 uint32_t * colors = context->colors;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	743 src = 0;
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	744 uint8_t sprite_color = *sprite_buf & 0x3F;
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	745 if (sprite_color == 0x3E \|\| sprite_color == 0x3F) {
232 54873acb982e Shadow and higlight operators were switched Mike Pavone <pavone@retrodev.com> parents: 230 diff changeset	746 if (sprite_color == 0x3F) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	747 colors += CRAM_SIZE;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	748 src = DBG_SHADOW;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	749 } else {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	750 colors += CRAM_SIZE*2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	751 src = DBG_HILIGHT;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	752 }
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	753 if (plane_a & BUF_BIT_PRIORITY && plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	754 pixel = *plane_a;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	755 src \|= a_src;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	756 } else if (plane_b & BUF_BIT_PRIORITY && plane_b & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	757 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	758 src \|= DBG_SRC_B;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	759 } else if (*plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	760 pixel = *plane_a;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	761 src \|= a_src;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	762 } else if (*plane_b & 0xF){
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	763 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	764 src \|= DBG_SRC_B;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	765 } else {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	766 pixel = context->regs[REG_BG_COLOR] & 0x3F;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	767 src \|= DBG_SRC_BG;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	768 }
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	769 } else {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	770 if (sprite_buf & BUF_BIT_PRIORITY && sprite_buf & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	771 pixel = *sprite_buf;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	772 src = DBG_SRC_S;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	773 } else if (plane_a & BUF_BIT_PRIORITY && plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	774 pixel = *plane_a;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	775 src = a_src;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	776 } else if (plane_b & BUF_BIT_PRIORITY && plane_b & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	777 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	778 src = DBG_SRC_B;
233 9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	779 } else {
9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	780 if (!(plane_a & BUF_BIT_PRIORITY \|\| plane_a & BUF_BIT_PRIORITY)) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	781 colors += CRAM_SIZE;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	782 src = DBG_SHADOW;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	783 }
233 9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	784 if (*sprite_buf & 0xF) {
9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	785 pixel = *sprite_buf;
9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	786 if (*sprite_buf & 0xF == 0xE) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	787 colors = context->colors;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	788 src = DBG_SRC_S;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	789 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	790 src \|= DBG_SRC_S;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	791 }
233 9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	792 } else if (*plane_a & 0xF) {
9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	793 pixel = *plane_a;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	794 src \|= a_src;
233 9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	795 } else if (*plane_b & 0xF){
9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	796 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	797 src \|= DBG_SRC_B;
233 9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	798 } else {
9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	799 pixel = context->regs[REG_BG_COLOR] & 0x3F;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	800 src \|= DBG_SRC_BG;
233 9d10669f2579 Less broken implementation of shadow/highlight Mike Pavone <pavone@retrodev.com> parents: 232 diff changeset	801 }
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	802 }
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	803 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	804 pixel &= 0x3F;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	805 uint32_t outpixel;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	806 if (context->debug) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	807 outpixel = context->debugcolors[src];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	808 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	809 outpixel = colors[pixel];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	810 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	811 if (context->b32) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	812 *(dst32++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	813 } else {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	814 *(dst++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	815 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	816 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) \| ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) \| src;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	817 }
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	818 } else {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	819 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	820 uint8_t pixel;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	821 src = 0;
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	822 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	823 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	824 if (sprite_buf & BUF_BIT_PRIORITY && sprite_buf & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	825 pixel = *sprite_buf;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	826 src = DBG_SRC_S;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	827 } else if (plane_a & BUF_BIT_PRIORITY && plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	828 pixel = *plane_a;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	829 src = a_src;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	830 } else if (plane_b & BUF_BIT_PRIORITY && plane_b & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	831 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	832 src = DBG_SRC_B;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	833 } else if (*sprite_buf & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	834 pixel = *sprite_buf;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	835 src = DBG_SRC_S;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	836 } else if (*plane_a & 0xF) {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	837 pixel = *plane_a;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	838 src = a_src;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	839 } else if (*plane_b & 0xF){
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	840 pixel = *plane_b;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	841 src = DBG_SRC_B;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	842 } else {
d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	843 pixel = context->regs[REG_BG_COLOR] & 0x3F;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	844 src = DBG_SRC_BG;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	845 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	846 uint32_t outpixel;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	847 if (context->debug) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	848 outpixel = context->debugcolors[src];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	849 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	850 outpixel = context->colors[pixel & 0x3F];
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	851 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	852 if (context->b32) {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	853 *(dst32++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	854 } else {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	855 *(dst++) = outpixel;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	856 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	857 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) \| ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) \| src;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	858 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	859 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	860 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	861 //dst = context->framebuf + line * 320;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	862 //sprite_buf = context->linebuf + col * 8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	863 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	864 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	865 //end = dst + 8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	866 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	867 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	868 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	869 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	870
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	871 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	872 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	873 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	874 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	875 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	876 external_slot(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	877 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	878 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	879 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	880 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	881 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	882 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	883 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	884 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	885 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	886 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	887 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	888 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	889 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	890 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	891 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	892 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	893 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	894 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	895 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	896
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	897 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	898 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	899 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	900 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	901 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	902 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	903 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	904 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	905 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	906 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	907 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	908 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	909 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	910 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	911 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	912 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	913 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	914 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	915 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	916 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	917 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	918 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	919 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	920 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	921
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	922 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	923 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	924 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	925 uint32_t mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	926 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	927 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	928 //sprite render to line buffer starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	929 case 0:
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	930 context->cur_slot = MAX_DRAWS-1;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	931 memset(context->linebuf, 0, LINEBUF_SIZE);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	932 case 1:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	933 case 2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	934 case 3:
329 fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	935 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	936 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	937 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	938 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	939 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	940 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	941 //sprite attribute table scan starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	942 case 4:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	943 render_sprite_cells( context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	944 context->sprite_index = 0x80;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	945 context->slot_counter = MAX_SPRITES_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	946 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	947 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	948 case 5:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	949 case 6:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	950 case 7:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	951 case 8:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	952 case 9:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	953 case 10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	954 case 11:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	955 case 12:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	956 case 13:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	957 case 14:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	958 case 15:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	959 case 16:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	960 case 17:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	961 case 18:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	962 case 19:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	963 case 20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	964 //!HSYNC asserted
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	965 case 21:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	966 case 22:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	967 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	968 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	969 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	970 case 23:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	971 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	972 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	973 case 24:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	974 case 25:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	975 case 26:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	976 case 27:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	977 case 28:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	978 case 29:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	979 case 30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	980 case 31:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	981 case 32:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	982 case 33:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	983 case 34:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	984 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	985 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	986 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	987 case 35:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	988 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	989 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	990 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	991 mask \|= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	992 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	993 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	994 mask \|= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	995 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	996 line &= mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	997 address += line * 4;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	998 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	999 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1000 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1001 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1002 case 36:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1003 //!HSYNC high
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1004 case 37:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1005 case 38:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1006 case 39:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1007 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1008 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1009 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1010 case 40:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1011 read_map_scroll_a(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1012 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1013 case 41:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1014 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1015 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1016 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1017 case 42:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1018 render_map_1(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1019 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1020 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1021 case 43:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1022 render_map_2(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1023 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1024 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1025 case 44:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1026 read_map_scroll_b(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1027 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1028 case 45:
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1029 render_sprite_cells(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1030 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1031 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1032 case 46:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1033 render_map_3(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1034 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1035 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1036 case 47:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1037 render_map_output(line, 0, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1038 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1039 //reverse context slot counter so it counts the number of sprite slots
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1040 //filled rather than the number of available slots
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1041 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1042 context->cur_slot = MAX_SPRITES_LINE-1;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1043 context->sprite_draws = MAX_DRAWS;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	1044 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1045 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1046 COLUMN_RENDER_BLOCK(2, 48)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1047 COLUMN_RENDER_BLOCK(4, 56)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1048 COLUMN_RENDER_BLOCK(6, 64)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1049 COLUMN_RENDER_BLOCK_REFRESH(8, 72)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1050 COLUMN_RENDER_BLOCK(10, 80)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1051 COLUMN_RENDER_BLOCK(12, 88)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1052 COLUMN_RENDER_BLOCK(14, 96)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1053 COLUMN_RENDER_BLOCK_REFRESH(16, 104)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1054 COLUMN_RENDER_BLOCK(18, 112)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1055 COLUMN_RENDER_BLOCK(20, 120)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1056 COLUMN_RENDER_BLOCK(22, 128)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1057 COLUMN_RENDER_BLOCK_REFRESH(24, 136)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1058 COLUMN_RENDER_BLOCK(26, 144)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1059 COLUMN_RENDER_BLOCK(28, 152)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1060 COLUMN_RENDER_BLOCK(30, 160)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1061 COLUMN_RENDER_BLOCK_REFRESH(32, 168)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1062 COLUMN_RENDER_BLOCK(34, 176)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1063 COLUMN_RENDER_BLOCK(36, 184)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1064 COLUMN_RENDER_BLOCK(38, 192)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1065 COLUMN_RENDER_BLOCK_REFRESH(40, 200)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1066 case 208:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1067 case 209:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1068 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1069 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1070 default:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1071 //leftovers from HSYNC clock change nonsense
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1072 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1073 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1074 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1075
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1076 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1077 {
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1078 uint16_t address;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1079 uint32_t mask;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1080 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1081 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1082 //sprite render to line buffer starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1083 case 0:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1084 context->cur_slot = MAX_DRAWS_H32-1;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1085 memset(context->linebuf, 0, LINEBUF_SIZE);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1086 case 1:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1087 case 2:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1088 case 3:
329 fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1089 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1090 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1091 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1092 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1093 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1094 break;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1095 //sprite attribute table scan starts
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1096 case 4:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1097 render_sprite_cells( context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1098 context->sprite_index = 0x80;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1099 context->slot_counter = MAX_SPRITES_LINE_H32;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1100 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1101 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1102 case 5:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1103 case 6:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1104 case 7:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1105 case 8:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1106 case 9:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1107 case 10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1108 case 11:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1109 case 12:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1110 case 13:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1111 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1112 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1113 case 14:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1114 external_slot(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1115 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1116 case 15:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1117 case 16:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1118 case 17:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1119 case 18:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1120 case 19:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1121 //HSYNC start
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1122 case 20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1123 case 21:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1124 case 22:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1125 case 23:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1126 case 24:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1127 case 25:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1128 case 26:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1129 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1130 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1131 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1132 case 27:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1133 external_slot(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1134 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1135 case 28:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1136 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1137 mask = 0;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1138 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1139 mask \|= 0xF8;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1140 }
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1141 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1142 mask \|= 0x7;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1143 }
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1144 line &= mask;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1145 address += line * 4;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1146 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1147 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1148 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1149 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1150 case 29:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1151 case 30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1152 case 31:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1153 case 32:
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1154 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1155 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1156 break;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1157 //!HSYNC high
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1158 case 33:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1159 read_map_scroll_a(0, line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1160 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1161 case 34:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1162 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1163 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1164 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1165 case 35:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1166 render_map_1(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1167 scan_sprite_table(line, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1168 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1169 case 36:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1170 render_map_2(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1171 scan_sprite_table(line, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1172 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1173 case 37:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1174 read_map_scroll_b(0, line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1175 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1176 case 38:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1177 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1178 scan_sprite_table(line, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1179 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1180 case 39:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1181 render_map_3(context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1182 scan_sprite_table(line, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1183 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1184 case 40:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1185 render_map_output(line, 0, context);
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1186 scan_sprite_table(line, context);//Just a guess
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1187 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1188 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1189 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1190 context->cur_slot = MAX_SPRITES_LINE_H32-1;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1191 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1192 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1193 break;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1194 COLUMN_RENDER_BLOCK(2, 41)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1195 COLUMN_RENDER_BLOCK(4, 49)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1196 COLUMN_RENDER_BLOCK(6, 57)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1197 COLUMN_RENDER_BLOCK_REFRESH(8, 65)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1198 COLUMN_RENDER_BLOCK(10, 73)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1199 COLUMN_RENDER_BLOCK(12, 81)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1200 COLUMN_RENDER_BLOCK(14, 89)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1201 COLUMN_RENDER_BLOCK_REFRESH(16, 97)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1202 COLUMN_RENDER_BLOCK(18, 105)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1203 COLUMN_RENDER_BLOCK(20, 113)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1204 COLUMN_RENDER_BLOCK(22, 121)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1205 COLUMN_RENDER_BLOCK_REFRESH(24, 129)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1206 COLUMN_RENDER_BLOCK(26, 137)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1207 COLUMN_RENDER_BLOCK(28, 145)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1208 COLUMN_RENDER_BLOCK(30, 153)
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1209 COLUMN_RENDER_BLOCK_REFRESH(32, 161)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1210 case 169:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1211 case 170:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1212 external_slot(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1213 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1214 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1215 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1216 void latch_mode(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1217 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1218 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) \| (context->regs[REG_MODE_2] & BIT_PAL);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1219 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1220
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1221 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1222 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1223 if (line > 0) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1224 line -= 1;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1225 int starti = -1;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1226 if (context->latched_mode & BIT_H40) {
462 5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1227 if (slot >= 55 && slot < 210) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1228 uint32_t x = (slot-55)*2;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1229 starti = line * 320 + x;
462 5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1230 } else if (slot < 5) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1231 uint32_t x = (slot + 155)*2;
5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1232 starti = (line-1)*320 + x;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1233 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1234 } else {
462 5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1235 if (slot >= 48 && slot < 171) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1236 uint32_t x = (slot-48)*2;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1237 starti = line * 320 + x;
462 5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1238 } else if (slot < 5) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1239 uint32_t x = (slot + 123)*2;
5677c053edd6 Fix timing of backdrop rendering when the display is turned off Mike Pavone <pavone@retrodev.com> parents: 461 diff changeset	1240 starti = (line-1)*320 + x;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1241 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1242 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1243 if (starti >= 0) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1244 if (context->b32) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1245 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1246 uint32_t * start = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1247 start += starti;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1248 for (int i = 0; i < 2; i++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1249 *(start++) = color;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1250 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1251 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1252 uint16_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1253 uint16_t * start = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1254 start += starti;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1255 for (int i = 0; i < 2; i++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1256 *(start++) = color;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1257 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1258 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1259 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1260 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1261 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1262
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1263 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1264 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1265 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1266 {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1267 context->flags &= ~FLAG_UNUSED_SLOT;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1268 uint32_t line = context->cycles / MCLKS_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1269 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
334 4c91470e1a53 Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect Mike Pavone <pavone@retrodev.com> parents: 333 diff changeset	1270 if (!context->cycles) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1271 latch_mode(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1272 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1273 uint32_t linecyc = context->cycles % MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1274 if (linecyc == 0) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1275 if (line <= 1 \|\| line >= active_lines) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1276 context->hint_counter = context->regs[REG_HINT];
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1277 } else if (context->hint_counter) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1278 context->hint_counter--;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1279 } else {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1280 context->flags2 \|= FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1281 context->hint_counter = context->regs[REG_HINT];
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1282 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1283 } else if(line == active_lines) {
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	1284 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1285 if (linecyc == intcyc) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1286 context->flags2 \|= FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1287 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1288 }
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1289 uint32_t inccycles, slot;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1290 if (context->latched_mode & BIT_H40){
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1291 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1292 slot = linecyc/MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1293 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1294 } else if(linecyc < MCLK_WEIRD_END) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1295 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1296 {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1297 case 0:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1298 inccycles = 19;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1299 slot = 0;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1300 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1301 case 19:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1302 slot = 1;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1303 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1304 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1305 case 39:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1306 slot = 2;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1307 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1308 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1309 case 59:
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1310 slot = 3;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1311 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1312 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1313 case 79:
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1314 slot = 4;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1315 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1316 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1317 case 97:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1318 slot = 5;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1319 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1320 break;
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1321 case 117:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1322 slot = 6;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1323 inccycles = 20;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1324 break;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1325 case 137:
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1326 slot = 7;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1327 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1328 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1329 case 157:
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1330 slot = 8;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1331 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1332 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1333 case 175:
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1334 slot = 9;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1335 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1336 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1337 case 195:
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1338 slot = 10;
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1339 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1340 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1341 case 215:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1342 slot = 11;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1343 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1344 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1345 case 235:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1346 slot = 12;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1347 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1348 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1349 case 253:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1350 slot = 13;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1351 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1352 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1353 case 273:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1354 slot = 14;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1355 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1356 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1357 case 293:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1358 slot = 15;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1359 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1360 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1361 case 313:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1362 slot = 16;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1363 inccycles = 19;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1364 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1365 default:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1366 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1367 exit(1);
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1368 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1369 slot += HSYNC_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1370 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1371 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1372 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1373 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1374 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1375 inccycles = MCLKS_SLOT_H32;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1376 slot = linecyc/MCLKS_SLOT_H32;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1377 }
329 fd5f6577db9b Implement first line/last line weirdness in VDP Mike Pavone <pavone@retrodev.com> parents: 328 diff changeset	1378 if ((line < active_lines \|\| (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) {
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1379 //first sort-of active line is treated as 255 internally
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	1380 //it's used for gathering sprite info for line
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1381 line = (line - 1) & 0xFF;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	1382
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1383 //Convert to slot number
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1384 if (context->latched_mode & BIT_H40){
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1385 vdp_h40(line, slot, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1386 } else {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1387 vdp_h32(line, slot, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1388 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1389 } else {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1390 if (!is_refresh(context, slot)) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1391 external_slot(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1392 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1393 if (line < active_lines) {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1394 check_render_bg(context, line, slot);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1395 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1396 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1397 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, slot)) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1398 run_dma_src(context, slot);
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1399 }
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1400 context->cycles += inccycles;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1401 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1402 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1403
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1404 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1405 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1406 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1407 vdp_run_context(context, target_cycles);
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1408 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1409 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1410
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1411 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1412 {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1413 for(;;) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1414 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1415 if (!dmalen) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1416 dmalen = 0x10000;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1417 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1418 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1419 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 \|\| (context->cd & 0xF) == VRAM_WRITE) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1420 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1421 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1422 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1423 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1424 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1425 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1426 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1427 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1428 } else {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1429 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1430 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1431 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1432 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1433 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1434 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1435 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1436
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1437 int vdp_control_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1438 {
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1439 printf("control port write: %X at %d\n", value, context->cycles);
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1440 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1441 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1442 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1443 if (context->flags & FLAG_PENDING) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1444 context->address = (context->address & 0x3FFF) \| (value << 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1445 context->cd = (context->cd & 0x3) \| ((value >> 2) & 0x3C);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1446 context->flags &= ~FLAG_PENDING;
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1447 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1448 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1449 //
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1450 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1451 //DMA copy or 68K -> VDP, transfer starts immediately
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1452 context->flags \|= FLAG_DMA_RUN;
131 8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances Mike Pavone <pavone@retrodev.com> parents: 109 diff changeset	1453 context->dma_cd = context->cd;
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1454 //printf("DMA start at cycle %d\n", context->cycles);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1455 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1456 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) \| (context->regs[REG_DMASRC_M] << 9) \| (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L]);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1457 return 1;
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1458 } else {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1459 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1460 }
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1461 } else {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1462 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1463 }
63 a6dd5b7a971b Add FPS counter to console output Mike Pavone <pavone@retrodev.com> parents: 58 diff changeset	1464 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1465 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1466 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1467 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1468 uint8_t reg = (value >> 8) & 0x1F;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1469 if (reg < VDP_REGS) {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	1470 //printf("register %d set to %X\n", reg, value & 0xFF);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1471 context->regs[reg] = value;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	1472 if (reg == REG_MODE_2) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	1473 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled");
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	1474 }
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1475 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1476 context->double_res = (value & (BIT_INTERLACE \| BIT_DOUBLE_RES)) == (BIT_INTERLACE \| BIT_DOUBLE_RES);
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	1477 if (!context->double_res) {
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	1478 context->framebuf = context->oddbuf;
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	1479 }
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1480 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1481 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1482 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1483 context->flags \|= FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1484 context->address = (context->address &0xC000) \| (value & 0x3FFF);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1485 context->cd = (context->cd &0x3C) \| (value >> 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1486 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1487 }
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1488 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1489 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1490
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1491 int vdp_data_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1492 {
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1493 printf("data port write: %X at %d\n", value, context->cycles);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1494 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1495 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1496 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1497 if (!(context->cd & 1)) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1498 //ignore writes when cd is configured for read
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1499 return 0;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1500 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1501 context->flags &= ~FLAG_PENDING;
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	1502 /*if (context->fifo_cur == context->fifo_end) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1503 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	1504 }*/
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1505 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1506 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1507 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1508 while (context->fifo_cur == context->fifo_end) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1509 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1510 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1511 context->fifo_cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1512 context->fifo_cur->address = context->address;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1513 context->fifo_cur->value = value;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1514 context->last_write_val = value;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1515 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1516 context->flags \|= FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1517 }
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1518 context->fifo_cur->cd = context->cd;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1519 context->fifo_cur->partial = 0;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1520 context->fifo_cur++;
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1521 context->address += context->regs[REG_AUTOINC];
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1522 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1523 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1524
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1525 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1526 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1527 //TODO: implement test register
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1528 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1529
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1530 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1531 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1532 context->flags &= ~FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1533 uint16_t value = 0x3400;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1534 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1535 value \|= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1536 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1537 if (context->fifo_cur == context->fifo_end) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1538 value \|= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1539 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1540 if (context->flags2 & FLAG2_VINT_PENDING) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1541 value \|= 0x80;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1542 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1543 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1544 value \|= 0x10;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1545 }
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1546 uint32_t line= context->cycles / MCLKS_LINE;
789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1547 uint32_t linecyc = context->cycles % MCLKS_LINE;
459 c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1548 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) {
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1549 value \|= 0x8;
789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1550 }
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	1551 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) {
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1552 value \|= 0x4;
789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1553 }
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	1554 if (context->flags & FLAG_DMA_RUN) {
141 576f55711d8d Fix DMA in progress flag in VDP status register Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	1555 value \|= 0x2;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1556 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1557 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1558 value \|= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1559 }
459 c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1560 //printf("status read at cycle %d returned %X\n", context->cycles, value);
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	1561 //TODO: Sprite overflow, sprite collision, odd frame flag
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1562 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1563 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1564
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1565 #define CRAM_BITS 0xEEE
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1566 #define VSRAM_BITS 0x3FF
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1567
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1568 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1569 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1570 context->flags &= ~FLAG_PENDING;
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1571 if (context->cd & 1) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1572 return 0;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1573 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1574 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1575 context->flags &= ~FLAG_UNUSED_SLOT;
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1576 context->flags2 \|= FLAG2_READ_PENDING;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1577 while (!(context->flags & FLAG_UNUSED_SLOT)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1578 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1579 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1580 uint16_t value = 0;
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	1581 switch (context->cd & 0xF)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1582 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1583 case VRAM_READ:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1584 value = context->vdpmem[context->address] << 8;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1585 context->flags &= ~FLAG_UNUSED_SLOT;
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1586 context->flags2 \|= FLAG2_READ_PENDING;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1587 while (!(context->flags & FLAG_UNUSED_SLOT)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1588 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1589 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1590 value \|= context->vdpmem[context->address ^ 1];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1591 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1592 case CRAM_READ:
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1593 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1594 value \|= context->last_fifo_val & ~CRAM_BITS;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1595 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1596 case VSRAM_READ:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1597 if (((context->address / 2) & 63) < VSRAM_SIZE) {
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1598 value = context->vsram[context->address & 63] & VSRAM_BITS;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1599 value \|= context->last_fifo_val & ~VSRAM_BITS;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1600 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1601 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1602 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1603 context->address += context->regs[REG_AUTOINC];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1604 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1605 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1606
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1607 uint16_t vdp_hv_counter_read(vdp_context * context)
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1608 {
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	1609 //TODO: deal with clock adjustemnts handled in vdp_run_context
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1610 uint32_t line= context->cycles / MCLKS_LINE;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1611 if (!line) {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1612 line = 0xFF;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1613 } else {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1614 line--;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1615 if (line > 0xEA) {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1616 line = (line + 0xFA) & 0xFF;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1617 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1618 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1619 uint32_t linecyc = context->cycles % MCLKS_LINE;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1620 if (context->latched_mode & BIT_H40) {
332 671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1621 uint32_t slot;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1622 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1623 slot = linecyc/MCLKS_SLOT_H40;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1624 } else if(linecyc < MCLK_WEIRD_END) {
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1625 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1626 {
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1627 case 0:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1628 slot = 0;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1629 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1630 case 19:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1631 slot = 1;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1632 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1633 case 39:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1634 slot = 2;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1635 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1636 case 59:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1637 slot = 2;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1638 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1639 case 79:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1640 slot = 3;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1641 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1642 case 97:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1643 slot = 4;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1644 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1645 case 117:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1646 slot = 5;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1647 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1648 case 137:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1649 slot = 6;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1650 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1651 case 157:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1652 slot = 7;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1653 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1654 case 175:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1655 slot = 8;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1656 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1657 case 195:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1658 slot = 9;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1659 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1660 case 215:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1661 slot = 11;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1662 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1663 case 235:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1664 slot = 12;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1665 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1666 case 253:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1667 slot = 13;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1668 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1669 case 273:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1670 slot = 14;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1671 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1672 case 293:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1673 slot = 15;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1674 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1675 case 313:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1676 slot = 16;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1677 break;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1678 default:
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1679 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1680 exit(1);
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1681 }
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1682 slot += HSYNC_SLOT_H40;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1683 } else {
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1684 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1685 }
671a5be51522 Update hv counter calculation for clock wonkiness Mike Pavone <pavone@retrodev.com> parents: 331 diff changeset	1686 linecyc = slot * 2;
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1687 if (linecyc >= 86) {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1688 linecyc -= 86;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1689 } else {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1690 linecyc += 334;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1691 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1692 if (linecyc > 0x16C) {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1693 linecyc += 92;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1694 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1695 } else {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1696 linecyc /= 10;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1697 if (linecyc >= 74) {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1698 linecyc -= 74;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1699 } else {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1700 linecyc += 268;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1701 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1702 if (linecyc > 0x127) {
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1703 linecyc += 170;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1704 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1705 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1706 linecyc &= 0xFF;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1707 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1708 line <<= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1709 if (line & 0x100) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1710 line \|= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1711 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1712 }
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1713 return (line << 8) \| linecyc;
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1714 }
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 135 diff changeset	1715
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1716 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1717 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1718 //TODO: Find out what actually gets returned here
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1719 return 0xFFFF;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1720 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1721
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1722 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1723 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1724 context->cycles -= deduction;
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1725 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1726 if (start->cycle >= deduction) {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1727 start->cycle -= deduction;
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1728 } else {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1729 start->cycle = 0;
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1730 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1731 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1732 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	1733
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1734 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1735 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1736 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1737 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1738 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1739 if (context->flags2 & FLAG2_HINT_PENDING) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1740 return context->cycles;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1741 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1742 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1743 uint32_t line = context->cycles / MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1744 if (line >= active_lines) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1745 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1746 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1747 uint32_t linecyc = context->cycles % MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1748 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1749 if (!line) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1750 hcycle += MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1751 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1752 return hcycle;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1753 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1754
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1755 uint32_t vdp_next_vint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1756 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	1757 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1758 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1759 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1760 if (context->flags2 & FLAG2_VINT_PENDING) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1761 return context->cycles;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1762 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1763 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1764 uint32_t vcycle = MCLKS_LINE * active_lines;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1765 if (context->latched_mode & BIT_H40) {
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	1766 vcycle += VINT_CYCLE_H40;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1767 } else {
331 de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes Mike Pavone <pavone@retrodev.com> parents: 330 diff changeset	1768 vcycle += VINT_CYCLE_H32;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1769 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1770 if (vcycle < context->cycles) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1771 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1772 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1773 return vcycle;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1774 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1775
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1776 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1777 {
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1778 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1779 uint32_t vcycle = MCLKS_LINE * active_lines;
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1780 if (context->latched_mode & BIT_H40) {
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1781 vcycle += VINT_CYCLE_H40;
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1782 } else {
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1783 vcycle += VINT_CYCLE_H32;
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1784 }
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1785 return vcycle;
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1786 }
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	1787
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1788 void vdp_int_ack(vdp_context * context, uint16_t int_num)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1789 {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1790 if (int_num == 6) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1791 context->flags2 &= ~FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1792 } else if(int_num ==4) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1793 context->flags2 &= ~FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1794 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1795 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	1796

Mercurial > repos > blastem

annotate vdp.c @ 470:541c1ae8abf3