Mercurial > repos > blastem
annotate m68k_to_x86.c @ 545:67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 16 Feb 2014 19:54:27 -0800 |
parents | 8a26567852b7 |
children | 90aca661542b |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_x86.h" |
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7 #include "m68k_to_x86.h" |
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8 #include "68kinst.h" |
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9 #include "mem.h" |
211 | 10 #include "x86_backend.h" |
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11 #include <stdio.h> |
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12 #include <stddef.h> |
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13 #include <stdlib.h> |
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14 #include <string.h> |
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15 |
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16 #define BUS 4 |
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17 #define PREDEC_PENALTY 2 |
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18 #define CYCLES RAX |
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19 #define LIMIT RBP |
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20 #define SCRATCH1 RCX |
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21 #define SCRATCH2 RDI |
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22 #define CONTEXT RSI |
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23 |
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24 #define FLAG_N RBX |
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25 #define FLAG_V BH |
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26 #define FLAG_Z RDX |
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27 #define FLAG_C DH |
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28 |
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29 char disasm_buf[1024]; |
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30 |
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31 m68k_context * sync_components(m68k_context * context, uint32_t address); |
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32 |
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33 void m68k_invalid(); |
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34 void set_sr(); |
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35 void set_ccr(); |
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36 void get_sr(); |
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37 void bcd_add(); |
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38 void bcd_sub(); |
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39 |
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40 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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41 { |
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42 dst = add_ir(dst, num, CYCLES, SZ_D); |
118 | 43 return dst; |
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44 } |
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45 |
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46 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address, x86_68k_options * opts) |
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47 { |
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48 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
82
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49 uint8_t * jmp_off = dst+1; |
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50 dst = jcc(dst, CC_NC, dst + 7); |
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51 dst = mov_ir(dst, address, SCRATCH1, SZ_D); |
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52 dst = call(dst, opts->handle_cycle_limit_int); |
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53 *jmp_off = dst - (jmp_off+1); |
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54 return dst; |
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55 } |
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56 |
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57 uint8_t * check_cycles(uint8_t * dst, x86_68k_options * opts) |
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58 { |
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59 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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60 uint8_t * jmp_off = dst+1; |
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61 dst = jcc(dst, CC_NC, dst + 7); |
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62 dst = call(dst, opts->handle_cycle_limit); |
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63 *jmp_off = dst - (jmp_off+1); |
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64 return dst; |
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65 } |
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66 |
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67 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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68 { |
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69 if (op->addr_mode == MODE_REG) { |
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70 return opts->dregs[op->params.regs.pri]; |
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71 } |
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72 if (op->addr_mode == MODE_AREG) { |
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73 return opts->aregs[op->params.regs.pri]; |
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74 } |
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75 return -1; |
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76 } |
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77 |
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78 //must be called with an m68k_op_info that uses a register |
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79 size_t reg_offset(m68k_op_info *op) |
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80 { |
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81 if (op->addr_mode == MODE_REG) { |
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82 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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83 } |
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84 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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85 } |
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86 |
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87 void print_regs_exit(m68k_context * context) |
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88 { |
207 | 89 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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90 for (int i = 0; i < 8; i++) { |
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91 printf("d%d: %X\n", i, context->dregs[i]); |
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92 } |
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93 for (int i = 0; i < 8; i++) { |
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94 printf("a%d: %X\n", i, context->aregs[i]); |
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95 } |
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96 exit(0); |
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97 } |
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98 |
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99 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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100 { |
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101 int8_t reg = native_reg(&(inst->src), opts); |
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102 uint8_t sec_reg; |
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103 int32_t dec_amount,inc_amount; |
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104 if (reg >= 0) { |
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105 ea->mode = MODE_REG_DIRECT; |
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106 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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107 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D); |
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108 ea->base = SCRATCH1; |
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109 } else { |
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110 ea->base = reg; |
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111 } |
18
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|
112 return out; |
14
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|
113 } |
18
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114 switch (inst->src.addr_mode) |
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115 { |
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|
116 case MODE_REG: |
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117 case MODE_AREG: |
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118 //We only get one memory parameter, so if the dst operand is a register in memory, |
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|
119 //we need to copy this to a temp register first |
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|
120 reg = native_reg(&(inst->dst), opts); |
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|
121 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) |
18
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122 || inst->op == M68K_EXG) { |
447
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|
123 |
18
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124 ea->mode = MODE_REG_DISPLACE8; |
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125 ea->base = CONTEXT; |
52
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51
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|
126 ea->disp = reg_offset(&(inst->src)); |
18
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127 } else { |
181
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128 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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129 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D); |
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130 } else { |
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131 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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132 } |
18
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133 ea->mode = MODE_REG_DIRECT; |
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134 ea->base = SCRATCH1; |
181
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135 //we're explicitly handling the areg dest here, so we exit immediately |
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136 return out; |
18
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137 } |
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138 break; |
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139 case MODE_AREG_PREDEC: |
216
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Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
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213
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|
140 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 :1)); |
18
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141 out = cycles(out, PREDEC_PENALTY); |
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142 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
158
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|
143 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
18
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144 } else { |
158
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157
diff
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|
145 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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146 } |
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147 case MODE_AREG_INDIRECT: |
447
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148 case MODE_AREG_POSTINC: |
18
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149 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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150 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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151 } else { |
52
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|
152 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
18
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153 } |
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154 switch (inst->extra.size) |
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155 { |
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156 case OPSIZE_BYTE: |
343
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157 out = call(out, opts->read_8); |
18
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158 break; |
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159 case OPSIZE_WORD: |
343
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160 out = call(out, opts->read_16); |
18
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161 break; |
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162 case OPSIZE_LONG: |
343
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163 out = call(out, opts->read_32); |
18
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164 break; |
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165 } |
447
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|
166 |
18
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167 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
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182
diff
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|
168 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1)); |
18
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169 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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170 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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171 } else { |
52
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51
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|
172 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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173 } |
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174 } |
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175 ea->mode = MODE_REG_DIRECT; |
184
ebcbdd1c4cc8
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183
diff
changeset
|
176 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1; |
18
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177 break; |
71
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178 case MODE_AREG_DISPLACE: |
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179 out = cycles(out, BUS); |
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180 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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181 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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182 } else { |
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183 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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184 } |
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185 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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186 switch (inst->extra.size) |
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187 { |
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188 case OPSIZE_BYTE: |
343
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189 out = call(out, opts->read_8); |
71
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190 break; |
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191 case OPSIZE_WORD: |
343
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192 out = call(out, opts->read_16); |
71
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193 break; |
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194 case OPSIZE_LONG: |
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195 out = call(out, opts->read_32); |
71
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196 break; |
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|
197 } |
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198 ea->mode = MODE_REG_DIRECT; |
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199 ea->base = SCRATCH1; |
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|
200 break; |
81
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78
diff
changeset
|
201 case MODE_AREG_INDEX_DISP8: |
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78
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|
202 out = cycles(out, 6); |
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|
203 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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|
204 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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|
205 } else { |
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|
206 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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|
207 } |
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changeset
|
208 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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|
209 if (inst->src.params.regs.sec & 1) { |
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|
210 if (inst->src.params.regs.sec & 0x10) { |
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|
211 if (opts->aregs[sec_reg] >= 0) { |
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changeset
|
212 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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78
diff
changeset
|
213 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
214 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
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parents:
78
diff
changeset
|
215 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
216 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
217 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
218 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
219 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
220 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
221 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
222 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
223 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
224 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
225 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
226 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
227 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
228 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
229 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
230 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
231 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
232 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
233 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
234 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
235 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
236 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
237 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
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78
diff
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|
238 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
239 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
240 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
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|
241 } |
97
c7185fd840fc
Fix address register indexed addressing (probably)
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parents:
96
diff
changeset
|
242 switch (inst->extra.size) |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
changeset
|
243 { |
c7185fd840fc
Fix address register indexed addressing (probably)
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parents:
96
diff
changeset
|
244 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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324
diff
changeset
|
245 out = call(out, opts->read_8); |
97
c7185fd840fc
Fix address register indexed addressing (probably)
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parents:
96
diff
changeset
|
246 break; |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
changeset
|
247 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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324
diff
changeset
|
248 out = call(out, opts->read_16); |
97
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
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|
249 break; |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
changeset
|
250 case OPSIZE_LONG: |
343
467bfa17004a
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324
diff
changeset
|
251 out = call(out, opts->read_32); |
97
c7185fd840fc
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96
diff
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|
252 break; |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
changeset
|
253 } |
c7185fd840fc
Fix address register indexed addressing (probably)
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96
diff
changeset
|
254 ea->mode = MODE_REG_DIRECT; |
c7185fd840fc
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96
diff
changeset
|
255 ea->base = SCRATCH1; |
81
6d231dbe75ab
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78
diff
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|
256 break; |
71
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
257 case MODE_PC_DISPLACE: |
f80fa1776507
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70
diff
changeset
|
258 out = cycles(out, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
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parents:
73
diff
changeset
|
259 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
f80fa1776507
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70
diff
changeset
|
260 switch (inst->extra.size) |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
261 { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
262 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
263 out = call(out, opts->read_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
264 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
265 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
266 out = call(out, opts->read_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
267 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
268 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
269 out = call(out, opts->read_32); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
270 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
271 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
272 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
273 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
274 break; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
275 case MODE_PC_INDEX_DISP8: |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
276 out = cycles(out, 6); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
277 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
278 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
279 if (inst->src.params.regs.sec & 1) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
280 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
281 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
282 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
283 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
284 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
285 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
286 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
287 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
288 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
289 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
290 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
291 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
292 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
293 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
294 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
295 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
296 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
297 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
298 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
299 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
300 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
301 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
302 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
303 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
304 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
305 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
306 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
307 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
308 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
309 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
310 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
311 } |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
312 switch (inst->extra.size) |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
313 { |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
314 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
315 out = call(out, opts->read_8); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
316 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
317 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
318 out = call(out, opts->read_16); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
319 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
320 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
321 out = call(out, opts->read_32); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
322 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
323 } |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
324 ea->mode = MODE_REG_DIRECT; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
325 ea->base = SCRATCH1; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
326 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
327 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
328 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
329 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
330 out = cycles(out, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
331 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
332 out = cycles(out, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
333 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
334 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
335 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
336 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
337 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
338 out = call(out, opts->read_8); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
339 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
340 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
341 out = call(out, opts->read_16); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
342 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
343 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
344 out = call(out, opts->read_32); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
345 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
346 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
347 ea->mode = MODE_REG_DIRECT; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
348 ea->base = SCRATCH1; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
349 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
350 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
351 case MODE_IMMEDIATE_WORD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
352 if (inst->variant != VAR_QUICK) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
353 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
354 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
355 ea->mode = MODE_IMMED; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
356 ea->disp = inst->src.params.immed; |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
357 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
358 ea->disp |= 0xFFFF0000; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
359 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
360 return out; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
361 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
362 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
363 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
364 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
365 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
366 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
367 if (ea->mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
368 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
369 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
370 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
371 ea->mode = MODE_REG_DIRECT; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
372 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
373 ea->base = SCRATCH1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
374 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
375 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
376 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
377 |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
378 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
379 { |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
380 int8_t reg = native_reg(&(inst->dst), opts), sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
381 int32_t dec_amount, inc_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
382 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
383 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
384 ea->base = reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
385 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
386 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
387 switch (inst->dst.addr_mode) |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 { |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 case MODE_REG: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 case MODE_AREG: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
391 ea->mode = MODE_REG_DISPLACE8; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
392 ea->base = CONTEXT; |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
393 ea->disp = reg_offset(&(inst->dst)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
394 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
395 case MODE_AREG_PREDEC: |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
396 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
397 out = push_r(out, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
398 } |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
399 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
400 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
401 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
402 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
403 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
404 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
405 case MODE_AREG_INDIRECT: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
406 case MODE_AREG_POSTINC: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
407 if (fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
408 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
409 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
410 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
411 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
412 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
413 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
414 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
415 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
416 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
417 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
418 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
419 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
420 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
421 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
422 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
423 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
424 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
425 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
426 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
427 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
428 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
429 //restore src operand to SCRATCH2 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
430 out =pop_r(out, SCRATCH2); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
431 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
432 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
433 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
434 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
435 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
436 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
437 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
438 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
439 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
440 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
441 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
442 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
443 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
444 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
445 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
446 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
447 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
448 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
449 ea->base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
450 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
451 case MODE_AREG_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
452 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
453 reg = fake_read ? SCRATCH2 : SCRATCH1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
454 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
455 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
456 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
457 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
458 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
459 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
460 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
461 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
462 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
463 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
464 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
465 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
466 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
467 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
468 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
469 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
470 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
471 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
472 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
473 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
474 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
475 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
476 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
477 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
478 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
479 case MODE_AREG_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
480 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
481 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
482 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
483 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
484 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
485 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
486 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
487 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
488 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
489 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
490 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
491 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
492 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
493 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
494 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
495 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
496 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
497 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
498 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
499 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
500 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
501 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
502 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
503 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
504 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
505 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
506 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
507 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
508 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
509 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
510 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
511 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
512 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
513 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
514 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
515 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
516 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
517 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
518 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
519 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
520 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
521 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
522 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
523 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
524 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
525 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
526 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
527 out = call(out, opts->read_8); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
528 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
529 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
530 out = call(out, opts->read_16); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
531 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
532 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
533 out = call(out, opts->read_32); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
534 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
535 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
536 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
537 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
538 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
539 ea->base = SCRATCH1; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
540 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
541 case MODE_PC_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
542 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
543 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
544 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
545 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
546 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
547 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
548 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
549 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
550 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
551 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
552 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
553 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
554 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
555 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
556 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
557 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
558 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
559 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
560 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
561 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
562 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
563 case MODE_PC_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
564 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
565 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
566 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
567 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
568 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
569 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
570 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
571 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
572 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
573 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
574 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
575 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
576 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
577 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
578 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
579 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
580 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
581 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
582 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
583 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
584 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
585 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
586 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
587 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
588 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
589 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
590 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
591 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
592 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
593 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
594 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
595 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
596 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
597 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
598 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
599 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
600 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
601 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
602 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
603 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
604 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
605 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
606 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
607 out = call(out, opts->read_8); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
608 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
609 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
610 out = call(out, opts->read_16); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
611 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
612 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
613 out = call(out, opts->read_32); |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
614 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
615 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
616 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
617 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
618 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
619 ea->base = SCRATCH1; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
620 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
621 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
622 case MODE_ABSOLUTE_SHORT: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
623 //Add cycles for reading address from instruction stream |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
624 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0)); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
625 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
626 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
627 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
628 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
629 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
630 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
631 out = call(out, opts->read_8); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
632 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
633 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
634 out = call(out, opts->read_16); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
635 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
636 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
637 out = call(out, opts->read_32); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
638 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
639 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
640 out = pop_r(out, SCRATCH2); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
641 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
642 ea->mode = MODE_REG_DIRECT; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
643 ea->base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
644 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
645 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
646 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
647 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
648 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
649 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
650 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
651 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
652 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
653 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
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|
654 { |
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655 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
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656 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) { |
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657 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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658 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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659 } else { |
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660 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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661 } |
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662 } |
18
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663 switch (inst->extra.size) |
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664 { |
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665 case OPSIZE_BYTE: |
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666 out = call(out, opts->write_8); |
18
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667 break; |
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668 case OPSIZE_WORD: |
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669 out = call(out, opts->write_16); |
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670 break; |
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671 case OPSIZE_LONG: |
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672 out = call(out, opts->write_32_lowfirst); |
18
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673 break; |
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674 } |
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675 } |
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676 return out; |
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677 } |
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diff
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|
678 |
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679 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
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680 { |
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681 address &= 0xFFFFFF; |
95
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diff
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|
682 address /= 2; |
18
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683 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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684 if (!native_code_map[chunk].base) { |
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|
685 return NULL; |
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diff
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|
686 } |
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687 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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688 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
18
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689 return NULL; |
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|
690 } |
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691 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
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692 } |
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|
693 |
235
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|
694 uint8_t * get_native_from_context(m68k_context * context, uint32_t address) |
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|
695 { |
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|
696 return get_native_address(context->native_code_map, address); |
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|
697 } |
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|
698 |
193
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699 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address) |
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|
700 { |
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701 address &= 0xFFFFFF; |
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|
702 address /= 2; |
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703 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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diff
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|
704 if (!native_code_map[chunk].base) { |
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192
diff
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|
705 return 0; |
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|
706 } |
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|
707 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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708 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
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192
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|
709 return 0; |
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|
710 } |
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|
711 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
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diff
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|
712 --address; |
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diff
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|
713 chunk = address / NATIVE_CHUNK_SIZE; |
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diff
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|
714 offset = address % NATIVE_CHUNK_SIZE; |
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192
diff
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|
715 } |
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|
716 return address*2; |
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|
717 } |
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|
718 |
192
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diff
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|
719 void map_native_address(m68k_context * context, uint32_t address, uint8_t * native_addr, uint8_t size, uint8_t native_size) |
18
3e7bfde7606e
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14
diff
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|
720 { |
192
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|
721 native_map_slot * native_code_map = context->native_code_map; |
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188
diff
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|
722 x86_68k_options * opts = context->options; |
18
3e7bfde7606e
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parents:
14
diff
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|
723 address &= 0xFFFFFF; |
192
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diff
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|
724 if (address > 0xE00000) { |
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188
diff
changeset
|
725 context->ram_code_flags[(address & 0xC000) >> 14] |= 1 << ((address & 0x3800) >> 11); |
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188
diff
changeset
|
726 if (((address & 0x3FFF) + size) & 0xC000) { |
1db07e112bf7
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188
diff
changeset
|
727 context->ram_code_flags[((address+size) & 0xC000) >> 14] |= 1 << (((address+size) & 0x3800) >> 11); |
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diff
changeset
|
728 } |
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|
729 uint32_t slot = (address & 0xFFFF)/1024; |
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diff
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|
730 if (!opts->ram_inst_sizes[slot]) { |
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diff
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|
731 opts->ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512); |
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188
diff
changeset
|
732 } |
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|
733 opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size; |
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diff
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|
734 } |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
735 address/= 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
736 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
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diff
changeset
|
737 if (!native_code_map[chunk].base) { |
3e7bfde7606e
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diff
changeset
|
738 native_code_map[chunk].base = native_addr; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
739 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
740 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
18
3e7bfde7606e
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diff
changeset
|
741 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
742 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
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diff
changeset
|
743 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
193
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744 for(address++,size-=2; size; address++,size-=2) { |
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|
745 chunk = address / NATIVE_CHUNK_SIZE; |
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diff
changeset
|
746 offset = address % NATIVE_CHUNK_SIZE; |
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diff
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|
747 if (!native_code_map[chunk].base) { |
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diff
changeset
|
748 native_code_map[chunk].base = native_addr; |
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|
749 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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|
750 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
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|
751 } |
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|
752 native_code_map[chunk].offsets[offset] = EXTENSION_WORD; |
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diff
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|
753 } |
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diff
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|
754 } |
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192
diff
changeset
|
755 |
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diff
changeset
|
756 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address) |
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diff
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|
757 { |
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|
758 if (address < 0xE00000) { |
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diff
changeset
|
759 return 0; |
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diff
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|
760 } |
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diff
changeset
|
761 uint32_t slot = (address & 0xFFFF)/1024; |
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diff
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|
762 return opts->ram_inst_sizes[slot][((address & 0xFFFF)/2)%512]; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
763 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
764 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
765 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
766 { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
767 int8_t reg, flags_reg, sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
768 uint8_t dir = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
769 int32_t offset; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
770 int32_t inc_amount, dec_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
771 x86_ea src; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
772 dst = translate_m68k_src(inst, &src, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
773 reg = native_reg(&(inst->dst), opts); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
774 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
775 //update statically set flags |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
776 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
777 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
778 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
779 |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
780 if (inst->dst.addr_mode != MODE_AREG) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
781 if (src.mode == MODE_REG_DIRECT) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
782 flags_reg = src.base; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
783 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
784 if (reg >= 0) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
785 flags_reg = reg; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
786 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
787 if(src.mode == MODE_REG_DISPLACE8) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
788 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
789 } else { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
790 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
791 } |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
792 src.mode = MODE_REG_DIRECT; |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
793 flags_reg = src.base = SCRATCH1; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
794 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
795 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
796 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
797 uint8_t size = inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
798 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
799 { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
800 case MODE_AREG: |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
801 size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
802 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
803 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
804 if (src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
805 dst = mov_rr(dst, src.base, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
806 } else if (src.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
807 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
808 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
809 dst = mov_ir(dst, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
810 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
811 } else if(src.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
812 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
813 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
814 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
815 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
816 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
817 dst = cmp_ir(dst, 0, flags_reg, size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
818 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
819 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
820 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
822 case MODE_AREG_PREDEC: |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
823 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
824 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
825 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
826 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
827 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
828 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
830 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
831 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
832 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
833 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
834 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
835 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
836 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
837 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
838 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
839 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
840 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
841 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
842 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
843 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
844 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
845 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
846 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
847 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
848 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
849 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
850 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
851 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
852 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
853 dst = call(dst, opts->write_8); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
854 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
855 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
856 dst = call(dst, opts->write_16); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
857 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
858 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
859 dst = call(dst, opts->write_32_highfirst); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
860 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
861 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
862 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
863 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
864 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
865 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
866 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
867 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
868 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
869 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
871 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
872 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
873 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
874 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
875 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
876 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
877 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
878 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
879 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
880 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
881 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
882 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
883 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
884 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
885 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
886 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
887 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
888 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
889 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
890 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
891 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
892 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
893 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
894 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
895 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
896 dst = call(dst, opts->write_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
897 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
898 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
899 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
900 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
901 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
902 dst = call(dst, opts->write_32_highfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
903 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
904 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
905 break; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
906 case MODE_AREG_INDEX_DISP8: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
907 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
908 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
909 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
910 } else { |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
911 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
912 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
913 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
914 if (inst->dst.params.regs.sec & 1) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
915 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
916 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
917 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
918 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
919 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
920 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
921 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
922 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
923 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
924 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
925 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
926 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
927 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
928 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
929 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
930 dst = push_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
931 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
932 if (inst->dst.params.regs.sec & 0x10) { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
933 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
934 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
935 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
936 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
937 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
938 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
939 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
940 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
941 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
942 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
943 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
944 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
945 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
946 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
947 dst = pop_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
948 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
949 } |
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
950 if (inst->dst.params.regs.displacement) { |
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
951 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
952 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
953 if (src.mode == MODE_REG_DIRECT) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
954 if (src.base != SCRATCH1) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
955 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
956 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
957 } else if (src.mode == MODE_REG_DISPLACE8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
958 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
959 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
960 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
961 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
962 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
963 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
964 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
965 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
966 } |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
967 switch (inst->extra.size) |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
968 { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
969 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
970 dst = call(dst, opts->write_8); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
971 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
972 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
973 dst = call(dst, opts->write_16); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
974 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
975 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
976 dst = call(dst, opts->write_32_highfirst); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
977 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
978 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
979 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
980 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
981 dst = cycles(dst, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
982 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
983 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
984 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
985 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
986 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
987 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
988 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
989 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
990 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
991 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
992 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
993 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
994 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
995 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
996 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
997 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
998 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
999 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1000 dst = call(dst, opts->write_8); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1001 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1002 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1003 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1004 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1005 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1006 dst = call(dst, opts->write_32_highfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1007 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1008 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1009 break; |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1010 case MODE_PC_INDEX_DISP8: |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1011 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1012 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1013 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1014 if (inst->dst.params.regs.sec & 1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1015 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1016 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1017 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1018 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1019 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1020 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1021 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1022 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1023 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1024 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1025 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1026 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1027 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1028 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1029 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1030 dst = push_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1031 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1032 if (inst->dst.params.regs.sec & 0x10) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1033 if (opts->aregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1034 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1035 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1036 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1037 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1038 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1039 if (opts->dregs[sec_reg] >= 0) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1040 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1041 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1042 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1043 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1044 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1045 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1046 if (src.base == SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1047 dst = pop_r(dst, SCRATCH1); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1048 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1049 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1050 if (inst->dst.params.regs.displacement) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1051 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1052 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1053 if (src.mode == MODE_REG_DIRECT) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1054 if (src.base != SCRATCH1) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1055 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1056 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1057 } else if (src.mode == MODE_REG_DISPLACE8) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1058 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1059 } else { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1060 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1061 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1062 if (inst->dst.addr_mode != MODE_AREG) { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1063 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1064 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1065 dst = setcc_r(dst, CC_S, FLAG_N); |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1066 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1067 switch (inst->extra.size) |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1068 { |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1069 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1070 dst = call(dst, opts->write_8); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1071 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1072 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1073 dst = call(dst, opts->write_16); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1074 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1075 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1076 dst = call(dst, opts->write_32_highfirst); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1077 break; |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1078 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1079 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1080 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1081 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1082 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1083 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1084 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1085 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1086 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1087 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1088 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1089 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1090 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1091 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1092 dst = cycles(dst, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1093 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1094 dst = cycles(dst, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1095 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1096 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1097 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1098 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1099 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1100 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1101 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1102 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1103 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1104 case OPSIZE_BYTE: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1105 dst = call(dst, opts->write_8); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1106 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1107 case OPSIZE_WORD: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1108 dst = call(dst, opts->write_16); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1109 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1110 case OPSIZE_LONG: |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1111 dst = call(dst, opts->write_32_highfirst); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1112 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1113 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1114 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1115 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1116 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1117 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1118 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1120 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1121 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1122 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1123 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1124 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1125 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1126 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1127 { |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1128 int8_t bit,reg,sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1129 uint8_t early_cycles; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1130 if(inst->src.addr_mode == MODE_REG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1131 //reg to mem |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1132 early_cycles = 8; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1133 int8_t dir; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1134 switch (inst->dst.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1135 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1136 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1137 case MODE_AREG_PREDEC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1138 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1139 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1140 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1141 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1142 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1143 break; |
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1144 case MODE_AREG_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1145 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1146 reg = SCRATCH2; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1147 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1148 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1149 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1150 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1151 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1152 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1153 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1154 case MODE_AREG_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1155 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1156 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1157 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1158 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1159 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1160 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1161 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1162 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1163 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1164 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1165 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1166 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1167 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1168 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1169 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1170 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1171 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1172 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1173 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1174 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1175 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1176 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1177 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1178 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1179 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1180 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1181 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1182 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1183 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1184 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1185 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1186 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1187 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1188 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1189 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1190 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1191 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1192 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1193 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1194 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1195 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1196 case MODE_PC_DISPLACE: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1197 early_cycles += BUS; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1198 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1199 break; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1200 case MODE_PC_INDEX_DISP8: |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1201 early_cycles += 6; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1202 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1203 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1204 if (inst->dst.params.regs.sec & 1) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1205 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1206 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1207 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1208 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1209 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1210 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1211 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1212 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1213 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1214 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1215 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1216 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1217 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1218 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1219 if (inst->dst.params.regs.sec & 0x10) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1220 if (opts->aregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1221 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1222 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1223 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1224 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1225 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1226 if (opts->dregs[sec_reg] >= 0) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1227 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1228 } else { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1229 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1230 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1231 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1232 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1233 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1234 if (inst->dst.params.regs.displacement) { |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1235 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1236 } |
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1237 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1238 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1239 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1240 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1241 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1242 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1243 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1244 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1245 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1246 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1247 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1248 } |
210
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1249 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1250 reg = 15; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1251 dir = -1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1252 } else { |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1253 reg = 0; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1254 dir = 1; |
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1255 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1256 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1257 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1258 if (inst->src.params.immed & (1 << bit)) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1259 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1260 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1261 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1262 dst = push_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1263 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1264 if (opts->aregs[reg-8] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1265 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1266 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1267 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1268 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1269 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1270 if (opts->dregs[reg] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1271 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1272 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1273 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1274 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1275 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1276 if (inst->extra.size == OPSIZE_LONG) { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1277 dst = call(dst, opts->write_32_lowfirst); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1278 } else { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1279 dst = call(dst, opts->write_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1280 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1281 dst = pop_r(dst, SCRATCH2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1282 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1283 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1284 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1285 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1286 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1287 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1288 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1289 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1290 } else { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1291 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1292 } |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1293 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1294 } else { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1295 //mem to reg |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1296 early_cycles = 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1297 switch (inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1298 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1299 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1300 case MODE_AREG_POSTINC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1301 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1302 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1303 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1304 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1305 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1306 break; |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1307 case MODE_AREG_DISPLACE: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1308 early_cycles += BUS; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1309 reg = SCRATCH2; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1310 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1311 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1312 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1313 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1314 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1315 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1316 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1317 case MODE_AREG_INDEX_DISP8: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1318 early_cycles += 6; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1319 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1320 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1321 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1322 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1323 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1324 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1325 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1326 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1327 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1328 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1329 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1330 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1331 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1332 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1333 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1334 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1335 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1336 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1337 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1338 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1339 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1340 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1341 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1342 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1343 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1344 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1345 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1346 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1347 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1348 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1349 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1350 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1351 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1352 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1353 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1354 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1355 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1356 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1357 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1358 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1359 case MODE_PC_DISPLACE: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1360 early_cycles += BUS; |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1361 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1362 break; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1363 case MODE_PC_INDEX_DISP8: |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1364 early_cycles += 6; |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1365 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1366 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1367 if (inst->src.params.regs.sec & 1) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1368 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1369 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1370 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1371 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1372 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1373 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1374 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1375 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1376 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1377 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1378 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1379 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1380 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1381 } else { |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1382 if (inst->src.params.regs.sec & 0x10) { |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1383 if (opts->aregs[sec_reg] >= 0) { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1384 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1385 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1386 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1387 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1388 } else { |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1389 if (opts->dregs[sec_reg] >= 0) { |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1390 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1391 } else { |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1392 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1393 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1394 } |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1395 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
eba78ad49a11
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Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1396 } |
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1397 if (inst->src.params.regs.displacement) { |
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1398 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1399 } |
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1400 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1401 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1402 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1403 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1404 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1405 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1406 break; |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1407 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1408 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1409 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1410 exit(1); |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1411 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1412 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1413 for(reg = 0; reg < 16; reg ++) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1414 if (inst->dst.params.immed & (1 << reg)) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1415 dst = push_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1416 if (inst->extra.size == OPSIZE_LONG) { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1417 dst = call(dst, opts->read_32); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1418 } else { |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1419 dst = call(dst, opts->read_16); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1420 } |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1421 if (inst->extra.size == OPSIZE_WORD) { |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1422 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1423 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1424 if (reg > 7) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1425 if (opts->aregs[reg-8] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1426 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1427 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1428 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1429 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1430 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1431 if (opts->dregs[reg] >= 0) { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1432 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1433 } else { |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1434 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1435 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1436 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1437 dst = pop_r(dst, SCRATCH1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1438 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1439 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1440 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1441 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1442 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1443 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1444 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1445 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1446 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1447 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1448 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1449 //prefetch |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1450 dst = cycles(dst, 4); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1451 return dst; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1452 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1453 |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1454 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1455 { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1456 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1457 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1458 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1459 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1460 int8_t reg = native_reg(&(inst->dst), opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1461 if (reg >= 0) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1462 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1463 return xor_rr(dst, reg, reg, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1464 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1465 x86_ea dst_op; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1466 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1467 if (dst_op.mode == MODE_REG_DIRECT) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1468 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1469 } else { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1470 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1471 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1472 dst = m68k_save_result(inst, dst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1473 return dst; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1474 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1475 |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1476 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1477 { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1478 x86_ea dst_op; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1479 uint8_t dst_size = inst->extra.size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1480 inst->extra.size--; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1481 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1482 if (dst_op.mode == MODE_REG_DIRECT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1483 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1484 dst = cmp_ir(dst, 0, dst_op.base, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1485 } else { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1486 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1487 dst = cmp_ir(dst, 0, SCRATCH1, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1488 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1489 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1490 inst->extra.size = dst_size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1491 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1492 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1493 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1494 dst = setcc_r(dst, CC_S, FLAG_N); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1495 //M68K EXT only operates on registers so no need for a call to save result here |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1496 return dst; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1497 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1498 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1499 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1500 { |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1501 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1502 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1503 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1504 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1505 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1506 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1507 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1508 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1509 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1510 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1511 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1512 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1513 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1514 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1515 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1516 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1517 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1518 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1519 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1520 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1521 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1522 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1523 if (dst_reg >= 0) { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1524 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1525 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1526 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1527 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1528 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1529 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1530 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1531 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1532 } else { |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1533 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1534 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1535 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1536 } else { |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1537 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1538 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1539 } |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1540 } |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1541 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1542 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1543 break; |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1544 case MODE_AREG_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1545 dst = cycles(dst, 12); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1546 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1547 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1548 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1549 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1550 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1551 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1552 if (inst->src.params.regs.sec & 1) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1553 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1554 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1555 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1556 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1557 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1558 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1559 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1560 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1561 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1562 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1563 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1564 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1565 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1566 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1567 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1568 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1569 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1570 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1571 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1572 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1573 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1574 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1575 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1576 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1577 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1578 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1579 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1580 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1581 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1582 if (inst->src.params.regs.displacement) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1583 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1584 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1585 if (dst_reg >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1586 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1587 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1588 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1589 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1590 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1591 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1592 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1593 if (dst_reg >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1594 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1595 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1596 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1597 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1598 break; |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1599 case MODE_PC_INDEX_DISP8: |
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1600 dst = cycles(dst, BUS*3); |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1601 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1602 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1603 if (inst->src.params.regs.sec & 1) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1604 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1605 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1606 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1607 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1608 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1609 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1610 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1611 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1612 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1613 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1614 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1615 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1616 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1617 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1618 if (inst->src.params.regs.sec & 0x10) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1619 if (opts->aregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1620 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1621 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1622 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1623 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1624 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1625 if (opts->dregs[sec_reg] >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1626 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1627 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1628 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1629 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1630 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1631 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1632 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1633 if (inst->src.params.regs.displacement) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1634 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1635 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1636 if (dst_reg >= 0) { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1637 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1638 } else { |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1639 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1640 } |
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1641 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1642 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1643 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1644 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1645 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1646 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1647 } else { |
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1648 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1649 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1650 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1651 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1652 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1653 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1654 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1655 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1656 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1657 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1658 |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1659 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1660 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1661 uint8_t sec_reg; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1662 switch(inst->src.addr_mode) |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1663 { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1664 case MODE_AREG_INDIRECT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1665 dst = cycles(dst, BUS); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1666 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1667 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1668 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1669 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1670 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1671 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1672 case MODE_AREG_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1673 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1674 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1675 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1676 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1677 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1678 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1679 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1680 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1681 case MODE_AREG_INDEX_DISP8: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1682 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1683 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1684 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1685 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1686 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1687 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1688 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1689 if (inst->src.params.regs.sec & 1) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1690 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1691 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1692 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1693 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1694 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1695 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1696 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1697 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1698 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1699 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1700 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1701 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1702 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1703 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1704 if (inst->src.params.regs.sec & 0x10) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1705 if (opts->aregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1706 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1707 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1708 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1709 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1710 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1711 if (opts->dregs[sec_reg] >= 0) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1712 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1713 } else { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1714 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1715 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1716 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1717 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1718 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1719 if (inst->src.params.regs.displacement) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1720 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1721 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1722 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1723 case MODE_PC_DISPLACE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1724 dst = cycles(dst, 8); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1725 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1726 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1727 case MODE_ABSOLUTE: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1728 case MODE_ABSOLUTE_SHORT: |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1729 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1730 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1731 break; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1732 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1733 m68k_disasm(inst, disasm_buf); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1734 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1735 exit(1); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1736 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1737 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1738 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1739 dst = call(dst, opts->write_32_lowfirst); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1740 return dst; |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1741 } |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1742 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1743 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1744 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1745 int32_t disp = inst->src.params.immed; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1746 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1747 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1748 dst = cycles(dst, 10); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1749 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1750 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1751 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1752 dst = call(dst, opts->write_32_highfirst); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1753 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1754 if (!dest_addr) { |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1755 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1756 //dummy address to be replaced later |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1757 dest_addr = dst + 256; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1758 } |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
1759 dst = jmp(dst, (char *)dest_addr); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1760 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1761 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1762 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1763 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1764 { |
156
3900cfde9dbb
Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Mike Pavone <pavone@retrodev.com>
parents:
155
diff
changeset
|
1765 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1766 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1767 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1768 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1769 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1770 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1771 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1772 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1773 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1774 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1775 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1776 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1777 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1778 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1779 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1780 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1781 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1782 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1783 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1784 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1785 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1786 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1787 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1788 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1789 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1790 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1791 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1792 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1793 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1794 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1795 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1796 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1797 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1798 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1799 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1800 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1801 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1802 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1803 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1804 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1805 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1806 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1807 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1808 case COND_LESS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1809 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1810 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1811 case COND_GREATER: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1812 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1813 case COND_LESS_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1814 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1815 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1816 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1817 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1818 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1819 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1820 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1821 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1822 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1823 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1824 dst = jcc(dst, cond, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1825 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1826 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1827 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1828 |
112 | 1829 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
1830 { | |
1831 uint8_t cond = inst->extra.cond; | |
1832 x86_ea dst_op; | |
1833 inst->extra.size = OPSIZE_BYTE; | |
1834 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); | |
1835 if (cond == COND_TRUE || cond == COND_FALSE) { | |
1836 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) { | |
1837 dst = cycles(dst, 6); | |
1838 } else { | |
1839 dst = cycles(dst, BUS); | |
1840 } | |
1841 if (dst_op.mode == MODE_REG_DIRECT) { | |
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1842 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B); |
112 | 1843 } else { |
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1844 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1845 } |
1846 } else { | |
1847 uint8_t cc = CC_NZ; | |
1848 switch (cond) | |
1849 { | |
1850 case COND_HIGH: | |
1851 cc = CC_Z; | |
1852 case COND_LOW_SAME: | |
1853 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1854 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); | |
1855 break; | |
1856 case COND_CARRY_CLR: | |
1857 cc = CC_Z; | |
1858 case COND_CARRY_SET: | |
1859 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); | |
1860 break; | |
1861 case COND_NOT_EQ: | |
1862 cc = CC_Z; | |
1863 case COND_EQ: | |
1864 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); | |
1865 break; | |
1866 case COND_OVERF_CLR: | |
1867 cc = CC_Z; | |
1868 case COND_OVERF_SET: | |
1869 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); | |
1870 break; | |
1871 case COND_PLUS: | |
1872 cc = CC_Z; | |
1873 case COND_MINUS: | |
1874 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); | |
1875 break; | |
1876 case COND_GREATER_EQ: | |
1877 cc = CC_Z; | |
1878 case COND_LESS: | |
1879 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); | |
1880 break; | |
1881 case COND_GREATER: | |
1882 cc = CC_Z; | |
1883 case COND_LESS_EQ: | |
1884 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); | |
1885 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); | |
1886 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); | |
1887 break; | |
1888 } | |
179
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1889 uint8_t *true_off = dst + 1; |
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1890 dst = jcc(dst, cc, dst+2); |
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1891 dst = cycles(dst, BUS); |
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1892 if (dst_op.mode == MODE_REG_DIRECT) { |
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
1893 dst = mov_ir(dst, 0, dst_op.base, SZ_B); |
112 | 1894 } else { |
179
68af8a56ab7a
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Mike Pavone <pavone@retrodev.com>
parents:
178
diff
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|
1895 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 1896 } |
179
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1897 uint8_t *end_off = dst+1; |
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1898 dst = jmp(dst, dst+2); |
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1899 *true_off = dst - (true_off+1); |
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1900 dst = cycles(dst, 6); |
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1901 if (dst_op.mode == MODE_REG_DIRECT) { |
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1902 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B); |
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1903 } else { |
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1904 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B); |
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1905 } |
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1906 *end_off = dst - (end_off+1); |
112 | 1907 } |
1908 dst = m68k_save_result(inst, dst, opts); | |
1909 return dst; | |
1910 } | |
1911 | |
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1912 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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1913 { |
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1914 uint8_t * dest_addr, sec_reg; |
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1915 uint32_t m68k_addr; |
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1916 switch(inst->src.addr_mode) |
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1917 { |
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1918 case MODE_AREG_INDIRECT: |
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1919 dst = cycles(dst, BUS*2); |
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1920 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1921 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1922 } else { |
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1923 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
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1924 } |
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1925 dst = call(dst, opts->native_addr); |
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1926 dst = jmp_r(dst, SCRATCH1); |
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1927 break; |
132
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1928 case MODE_AREG_INDEX_DISP8: |
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1929 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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1930 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1931 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1932 } else { |
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1933 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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1934 } |
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1935 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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1936 if (inst->src.params.regs.sec & 1) { |
516
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1937 //32-bit index register |
132
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1938 if (inst->src.params.regs.sec & 0x10) { |
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1939 if (opts->aregs[sec_reg] >= 0) { |
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1940 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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1941 } else { |
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1942 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1943 } |
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1944 } else { |
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1945 if (opts->dregs[sec_reg] >= 0) { |
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1946 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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1947 } else { |
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1948 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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1949 } |
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1950 } |
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1951 } else { |
516
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1952 //16-bit index register |
132
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1953 if (inst->src.params.regs.sec & 0x10) { |
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1954 if (opts->aregs[sec_reg] >= 0) { |
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1955 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1956 } else { |
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1957 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1958 } |
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1959 } else { |
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1960 if (opts->dregs[sec_reg] >= 0) { |
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1961 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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1962 } else { |
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1963 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
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1964 } |
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1965 } |
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1966 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
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1967 } |
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1968 if (inst->src.params.regs.displacement) { |
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1969 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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1970 } |
544
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1971 dst = call(dst, opts->native_addr); |
132
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1972 dst = jmp_r(dst, SCRATCH1); |
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1973 break; |
76
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1974 case MODE_PC_DISPLACE: |
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1975 dst = cycles(dst, 10); |
124
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1976 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
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1977 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
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1978 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
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1979 if (!dest_addr) { |
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1980 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
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1981 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
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1982 dest_addr = dst + 256; |
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1983 } |
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1984 dst = jmp(dst, dest_addr); |
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1985 } else { |
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1986 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
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1987 dst = call(dst, opts->native_addr); |
124
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1988 dst = jmp_r(dst, SCRATCH1); |
76
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1989 } |
71
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|
1990 break; |
132
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|
1991 case MODE_PC_INDEX_DISP8: |
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1992 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
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1993 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
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1994 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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1995 if (inst->src.params.regs.sec & 1) { |
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1996 if (inst->src.params.regs.sec & 0x10) { |
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1997 if (opts->aregs[sec_reg] >= 0) { |
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1998 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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1999 } else { |
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2000 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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2001 } |
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2002 } else { |
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2003 if (opts->dregs[sec_reg] >= 0) { |
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2004 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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2005 } else { |
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2006 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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2007 } |
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2008 } |
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2009 } else { |
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2010 if (inst->src.params.regs.sec & 0x10) { |
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2011 if (opts->aregs[sec_reg] >= 0) { |
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2012 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
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Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2013 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2014 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2015 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2016 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2017 if (opts->dregs[sec_reg] >= 0) { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2018 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2019 } else { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2020 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2021 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2022 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2023 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2024 } |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2025 if (inst->src.params.regs.displacement) { |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2026 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2027 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2028 dst = call(dst, opts->native_addr); |
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2029 dst = jmp_r(dst, SCRATCH1); |
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2030 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2031 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2032 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2033 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2034 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2035 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2036 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2037 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2038 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2039 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2040 dest_addr = dst + 256; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2041 } |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2042 dst = jmp(dst, dest_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2043 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2044 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2045 dst = call(dst, opts->native_addr); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2046 dst = jmp_r(dst, SCRATCH1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2047 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2048 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2049 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2050 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2051 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode); |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
102
diff
changeset
|
2052 exit(1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2053 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2054 return dst; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2055 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2056 |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2057 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2058 { |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2059 uint8_t * dest_addr, sec_reg; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2060 uint32_t after; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2061 uint32_t m68k_addr; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2062 switch(inst->src.addr_mode) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2063 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2064 case MODE_AREG_INDIRECT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2065 dst = cycles(dst, BUS*2); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2066 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2067 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2068 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2069 dst = call(dst, opts->write_32_highfirst); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2070 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2071 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2072 } else { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2073 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2074 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2075 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2076 dst = jmp_r(dst, SCRATCH1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2077 break; |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2078 case MODE_AREG_DISPLACE: |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2079 dst = cycles(dst, BUS*2); |
187
8e138da572ab
Fix return address for areg displacement mode JSR
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
2080 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2081 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2082 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2083 dst = call(dst, opts->write_32_highfirst); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2084 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2085 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2086 } else { |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2087 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2088 } |
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2089 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2090 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2091 dst = jmp_r(dst, SCRATCH1); |
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2092 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2093 case MODE_AREG_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2094 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2095 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2096 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2097 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2098 dst = call(dst, opts->write_32_highfirst); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2099 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2100 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2101 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2102 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2103 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2104 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2105 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2106 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2107 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2108 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2109 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2110 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2111 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2112 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2113 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2114 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2115 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2116 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2117 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2118 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2119 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2120 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2121 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2122 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2123 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2124 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2125 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2126 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2127 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2128 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2129 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2130 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2131 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2132 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2133 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2134 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2135 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2136 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2137 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2138 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2139 dst = jmp_r(dst, SCRATCH1); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2140 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2141 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2142 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2143 dst = cycles(dst, 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2144 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2145 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2146 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2147 dst = call(dst, opts->write_32_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2148 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2149 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2150 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2151 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2152 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2153 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2154 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2155 } |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2156 dst = jmp(dst, dest_addr); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2157 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2158 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2159 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2160 dst = jmp_r(dst, SCRATCH1); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2161 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2162 break; |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2163 case MODE_PC_INDEX_DISP8: |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2164 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2165 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2166 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2167 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2168 dst = call(dst, opts->write_32_highfirst); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2169 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2170 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2171 if (inst->src.params.regs.sec & 1) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2172 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2173 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2174 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2175 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2176 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2177 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2178 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2179 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2180 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2181 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2182 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2183 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2184 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2185 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2186 if (inst->src.params.regs.sec & 0x10) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2187 if (opts->aregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2188 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2189 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2190 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2191 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2192 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2193 if (opts->dregs[sec_reg] >= 0) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2194 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2195 } else { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2196 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2197 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2198 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2199 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2200 } |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2201 if (inst->src.params.regs.displacement) { |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2202 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2203 } |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2204 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2205 dst = jmp_r(dst, SCRATCH1); |
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2206 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2207 case MODE_ABSOLUTE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2208 case MODE_ABSOLUTE_SHORT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2209 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2210 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2211 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2212 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2213 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2214 dst = call(dst, opts->write_32_highfirst); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2215 m68k_addr = inst->src.params.immed; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2216 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2217 dest_addr = get_native_address(opts->native_code_map, m68k_addr); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2218 if (!dest_addr) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2219 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2220 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2221 dest_addr = dst + 256; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2222 } |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2223 dst = jmp(dst, dest_addr); |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2224 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2225 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2226 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2227 dst = jmp_r(dst, SCRATCH1); |
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2228 } |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2229 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2230 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2231 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2232 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode); |
105 | 2233 exit(1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2234 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2235 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2236 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2237 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2238 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2239 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2240 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2241 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2242 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2243 dst = call(dst, opts->read_32); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2244 dst = call(dst, opts->native_addr); |
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2245 dst = jmp_r(dst, SCRATCH1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2246 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2247 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2248 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2249 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2250 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2251 //best case duration |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2252 dst = cycles(dst, 10); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2253 uint8_t * skip_loc = NULL; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2254 //TODO: Check if COND_TRUE technically valid here even though |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2255 //it's basically a slow NOP |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2256 if (inst->extra.cond != COND_FALSE) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2257 uint8_t cond = CC_NZ; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2258 switch (inst->extra.cond) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2259 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2260 case COND_HIGH: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2261 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2262 case COND_LOW_SAME: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2263 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2264 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2265 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2266 case COND_CARRY_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2267 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2268 case COND_CARRY_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2269 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2270 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2271 case COND_NOT_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2272 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2273 case COND_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2274 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2275 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2276 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2277 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2278 case COND_OVERF_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2279 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2280 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2281 case COND_PLUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2282 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2283 case COND_MINUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2284 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2285 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2286 case COND_GREATER_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2287 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2288 case COND_LESS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2289 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2290 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2291 case COND_GREATER: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2292 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2293 case COND_LESS_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2294 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2295 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2296 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2297 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2298 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2299 skip_loc = dst + 1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2300 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2301 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2302 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2303 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2304 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2305 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2306 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2307 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2308 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2309 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2310 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2311 uint32_t after = inst->address + 2; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2312 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2313 if (!dest_addr) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2314 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2315 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2316 dest_addr = dst + 256; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2317 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2318 dst = jmp(dst, dest_addr); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2319 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2320 if (skip_loc) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2321 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2322 *skip_loc = dst - (skip_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2323 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2324 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2325 dst = cycles(dst, 4); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2326 } |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2327 return dst; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2328 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2329 |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2330 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2331 { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2332 int8_t reg = native_reg(&(inst->src), opts); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2333 //compensate for displacement word |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2334 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2335 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2336 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2337 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2338 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2339 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2340 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2341 } |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2342 dst = call(dst, opts->write_32_highfirst); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2343 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2344 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2345 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2346 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2347 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2348 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2349 //prefetch |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2350 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2351 return dst; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2352 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2353 |
172 | 2354 uint8_t * translate_m68k_movep(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2355 { | |
2356 int8_t reg; | |
2357 dst = cycles(dst, BUS*2); | |
2358 if (inst->src.addr_mode == MODE_REG) { | |
2359 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { | |
2360 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); | |
2361 } else { | |
2362 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); | |
2363 } | |
2364 if (inst->dst.params.regs.displacement) { | |
2365 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); | |
2366 } | |
2367 reg = native_reg(&(inst->src), opts); | |
2368 if (inst->extra.size == OPSIZE_LONG) { | |
2369 if (reg >= 0) { | |
2370 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2371 dst = shr_ir(dst, 24, SCRATCH1, SZ_D); | |
2372 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2373 dst = call(dst, opts->write_8); |
172 | 2374 dst = pop_r(dst, SCRATCH2); |
2375 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
2376 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2377 |
172 | 2378 } else { |
2379 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B); | |
2380 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2381 dst = call(dst, opts->write_8); |
172 | 2382 dst = pop_r(dst, SCRATCH2); |
2383 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B); | |
2384 } | |
2385 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2386 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2387 dst = call(dst, opts->write_8); |
172 | 2388 dst = pop_r(dst, SCRATCH2); |
2389 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
2390 } | |
2391 if (reg >= 0) { | |
2392 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2393 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); | |
2394 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2395 dst = call(dst, opts->write_8); |
172 | 2396 dst = pop_r(dst, SCRATCH2); |
2397 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
2398 } else { | |
2399 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B); | |
2400 dst = push_r(dst, SCRATCH2); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2401 dst = call(dst, opts->write_8); |
172 | 2402 dst = pop_r(dst, SCRATCH2); |
2403 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B); | |
2404 } | |
2405 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2406 dst = call(dst, opts->write_8); |
172 | 2407 } else { |
2408 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | |
2409 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); | |
2410 } else { | |
2411 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); | |
2412 } | |
2413 if (inst->src.params.regs.displacement) { | |
2414 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); | |
2415 } | |
2416 reg = native_reg(&(inst->dst), opts); | |
2417 if (inst->extra.size == OPSIZE_LONG) { | |
2418 if (reg >= 0) { | |
2419 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2420 dst = call(dst, opts->read_8); |
172 | 2421 dst = shl_ir(dst, 24, SCRATCH1, SZ_D); |
2422 dst = mov_rr(dst, SCRATCH1, reg, SZ_D); | |
2423 dst = pop_r(dst, SCRATCH1); | |
2424 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2425 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2426 dst = call(dst, opts->read_8); |
172 | 2427 dst = shl_ir(dst, 16, SCRATCH1, SZ_D); |
2428 dst = or_rr(dst, SCRATCH1, reg, SZ_D); | |
2429 } else { | |
2430 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2431 dst = call(dst, opts->read_8); |
172 | 2432 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B); |
2433 dst = pop_r(dst, SCRATCH1); | |
2434 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2435 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2436 dst = call(dst, opts->read_8); |
172 | 2437 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B); |
2438 } | |
2439 dst = pop_r(dst, SCRATCH1); | |
2440 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
2441 } | |
2442 dst = push_r(dst, SCRATCH1); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2443 dst = call(dst, opts->read_8); |
172 | 2444 if (reg >= 0) { |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2445 |
172 | 2446 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
2447 dst = mov_rr(dst, SCRATCH1, reg, SZ_W); | |
2448 dst = pop_r(dst, SCRATCH1); | |
2449 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2450 dst = call(dst, opts->read_8); |
172 | 2451 dst = mov_rr(dst, SCRATCH1, reg, SZ_B); |
2452 } else { | |
2453 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B); | |
2454 dst = pop_r(dst, SCRATCH1); | |
2455 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2456 dst = call(dst, opts->read_8); |
172 | 2457 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B); |
2458 } | |
2459 } | |
2460 return dst; | |
2461 } | |
2462 | |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2463 uint8_t * translate_m68k_cmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2464 { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2465 uint8_t size = inst->extra.size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2466 x86_ea src_op, dst_op; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2467 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2468 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2469 dst = push_r(dst, SCRATCH1); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2470 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2471 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2472 src_op.base = SCRATCH2; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2473 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2474 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2475 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2476 size = OPSIZE_LONG; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2477 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2478 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2479 dst = cycles(dst, BUS); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2480 if (src_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2481 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2482 dst = cmp_rr(dst, src_op.base, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2483 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2484 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2485 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2486 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2487 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2488 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2489 if (dst_op.mode == MODE_REG_DIRECT) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2490 dst = cmp_ir(dst, src_op.disp, dst_op.base, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2491 } else { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2492 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2493 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
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parents:
179
diff
changeset
|
2494 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2495 dst = setcc_r(dst, CC_C, FLAG_C); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2496 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2497 dst = setcc_r(dst, CC_S, FLAG_N); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2498 dst = setcc_r(dst, CC_O, FLAG_V); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2499 return dst; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2500 } |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2501 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2502 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2503 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2504 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2505 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2506 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2507 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2508 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2509 uint8_t * end_off = NULL; |
207 | 2510 uint8_t * nz_off = NULL; |
2511 uint8_t * z_off = NULL; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2512 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2513 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2514 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2515 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2516 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2517 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2518 if (src_op->mode == MODE_IMMED) { |
207 | 2519 if (src_op->disp != 1 && inst->op == M68K_ASL) { |
2520 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2521 for (int i = 0; i < src_op->disp; i++) { | |
2522 if (dst_op->mode == MODE_REG_DIRECT) { | |
2523 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2524 } else { | |
2525 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2526 } | |
2527 //dst = setcc_r(dst, CC_O, FLAG_V); | |
2528 dst = jcc(dst, CC_NO, dst+4); | |
2529 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2530 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2531 } else { |
207 | 2532 if (dst_op->mode == MODE_REG_DIRECT) { |
2533 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); | |
2534 } else { | |
2535 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); | |
2536 } | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
2537 dst = setcc_r(dst, CC_O, FLAG_V); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2538 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2539 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2540 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2541 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2542 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2543 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2544 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2545 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2546 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2547 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2548 dst = and_ir(dst, 63, RCX, SZ_D); |
207 | 2549 nz_off = dst+1; |
2550 dst = jcc(dst, CC_NZ, dst+2); | |
2551 //Flag behavior for shift count of 0 is different for x86 than 68K | |
2552 if (dst_op->mode == MODE_REG_DIRECT) { | |
2553 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size); | |
2554 } else { | |
2555 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2556 } | |
2557 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
2558 dst = setcc_r(dst, CC_S, FLAG_N); | |
2559 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2560 //For other instructions, this flag will be set below | |
2561 if (inst->op == M68K_ASL) { | |
2562 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2563 } | |
2564 z_off = dst+1; | |
2565 dst = jmp(dst, dst+2); | |
2566 *nz_off = dst - (nz_off + 1); | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2567 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2568 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2569 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
207 | 2570 if (inst->op == M68K_ASL) { |
2571 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB | |
2572 //Easiest way to deal with this is to shift one bit at a time | |
2573 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
2574 uint8_t * loop_start = dst; | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2575 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2576 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2577 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2578 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2579 } |
207 | 2580 //dst = setcc_r(dst, CC_O, FLAG_V); |
2581 dst = jcc(dst, CC_NO, dst+4); | |
2582 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2583 dst = loop(dst, loop_start); | |
2584 } else { | |
2585 //x86 shifts modulo 32 for operand sizes less than 64-bits | |
2586 //but M68K shifts modulo 64, so we need to check for large shifts here | |
2587 dst = cmp_ir(dst, 32, RCX, SZ_B); | |
2588 uint8_t * norm_shift_off = dst + 1; | |
2589 dst = jcc(dst, CC_L, dst+2); | |
2590 if (special) { | |
2591 if (inst->extra.size == OPSIZE_LONG) { | |
2592 uint8_t * neq_32_off = dst + 1; | |
2593 dst = jcc(dst, CC_NZ, dst+2); | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2594 |
207 | 2595 //set the carry bit to the lsb |
2596 if (dst_op->mode == MODE_REG_DIRECT) { | |
2597 dst = special(dst, 1, dst_op->base, SZ_D); | |
2598 } else { | |
2599 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); | |
2600 } | |
2601 dst = setcc_r(dst, CC_C, FLAG_C); | |
2602 dst = jmp(dst, dst+4); | |
2603 *neq_32_off = dst - (neq_32_off+1); | |
2604 } | |
2605 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
2606 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
2607 dst = mov_ir(dst, 0, FLAG_N, SZ_B); | |
2608 if (dst_op->mode == MODE_REG_DIRECT) { | |
2609 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); | |
2610 } else { | |
2611 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
2612 } | |
2613 } else { | |
2614 if (dst_op->mode == MODE_REG_DIRECT) { | |
2615 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); | |
2616 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
2617 } else { | |
2618 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); | |
2619 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
2620 } | |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2621 |
207 | 2622 } |
2623 end_off = dst+1; | |
2624 dst = jmp(dst, dst+2); | |
2625 *norm_shift_off = dst - (norm_shift_off+1); | |
2626 if (dst_op->mode == MODE_REG_DIRECT) { | |
2627 dst = shift_clr(dst, dst_op->base, inst->extra.size); | |
2628 } else { | |
2629 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); | |
2630 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2631 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2632 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2633 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2634 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2635 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2636 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2637 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2638 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2639 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2640 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2641 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2642 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2643 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2644 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2645 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
207 | 2646 if (z_off) { |
2647 *z_off = dst - (z_off + 1); | |
2648 } | |
219
8d3c16071559
Fix overflow flag behavior for lsl/lsr/asr
Mike Pavone <pavone@retrodev.com>
parents:
218
diff
changeset
|
2649 if (inst->op != M68K_ASL) { |
207 | 2650 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
2651 } | |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2652 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2653 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2654 } |
66 | 2655 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2656 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2657 |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2658 #define BIT_SUPERVISOR 5 |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2659 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2660 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2661 { |
122 | 2662 uint8_t * end_off, *zero_off, *norm_off; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2663 uint8_t dst_reg; |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
2664 dst = check_cycles_int(dst, inst->address, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2665 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2666 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2667 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2668 return translate_m68k_lea(dst, inst, opts); |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2669 } else if(inst->op == M68K_PEA) { |
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2670 return translate_m68k_pea(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2671 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2672 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2673 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2674 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2675 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2676 return translate_m68k_jmp(dst, inst, opts); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2677 } else if(inst->op == M68K_JSR) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2678 return translate_m68k_jsr(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2679 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2680 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2681 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2682 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2683 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2684 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2685 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2686 return translate_m68k_movem(dst, inst, opts); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2687 } else if(inst->op == M68K_LINK) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2688 return translate_m68k_link(dst, inst, opts); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2689 } else if(inst->op == M68K_EXT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2690 return translate_m68k_ext(dst, inst, opts); |
112 | 2691 } else if(inst->op == M68K_SCC) { |
2692 return translate_m68k_scc(dst, inst, opts); | |
172 | 2693 } else if(inst->op == M68K_MOVEP) { |
2694 return translate_m68k_movep(dst, inst, opts); | |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2695 } else if(inst->op == M68K_INVALID) { |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2696 if (inst->src.params.immed == 0x7100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2697 return retn(dst); |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2698 } |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2699 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D); |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2700 return call(dst, (uint8_t *)m68k_invalid); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2701 } else if(inst->op == M68K_CMP) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2702 return translate_m68k_cmp(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2703 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2704 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2705 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2706 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2707 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2708 if (inst->dst.addr_mode != MODE_UNUSED) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
2709 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2710 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2711 uint8_t size; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2712 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2713 { |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2714 case M68K_ABCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2715 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2716 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2717 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2718 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2719 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2720 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2721 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2722 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2723 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2724 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2725 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2726 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2727 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2728 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2729 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2730 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2731 dst = add_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2732 dst = call(dst, (uint8_t *)bcd_add); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2733 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2734 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2735 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2736 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2737 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2738 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2739 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2740 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2741 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2742 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2743 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2744 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2745 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2746 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2747 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2748 dst = cycles(dst, BUS); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2749 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2750 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2751 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2752 dst = add_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2753 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2754 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2755 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2756 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2757 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2758 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2759 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2760 dst = add_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2761 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2762 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2763 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2764 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2765 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2766 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2767 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2768 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2769 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2770 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2771 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2772 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2773 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2774 case M68K_ADDX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2775 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2776 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2777 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2778 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2779 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2780 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2781 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2782 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2783 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2784 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2785 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2786 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2787 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2788 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2789 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2790 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2791 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2792 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2793 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2794 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2795 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2796 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2797 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2798 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2799 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2800 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2801 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2802 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2803 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2804 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2805 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2806 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2807 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2808 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2809 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2810 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2811 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2812 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2813 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2814 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2815 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2816 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2817 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2818 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2819 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2820 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2821 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2822 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2823 case M68K_ANDI_CCR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2824 case M68K_ANDI_SR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2825 dst = cycles(dst, 20); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2826 //TODO: If ANDI to SR, trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2827 if (!(inst->src.params.immed & 0x1)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2828 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2829 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2830 if (!(inst->src.params.immed & 0x2)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2831 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2832 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2833 if (!(inst->src.params.immed & 0x4)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2834 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2835 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2836 if (!(inst->src.params.immed & 0x8)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2837 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2838 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2839 if (!(inst->src.params.immed & 0x10)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2840 dst = mov_irind(dst, 0, CONTEXT, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2841 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2842 if (inst->op == M68K_ANDI_SR) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2843 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2844 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2845 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2846 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2847 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2848 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2849 } |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2850 if (inst->src.params.immed & 0x700) { |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
2851 dst = call(dst, opts->do_sync); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
2852 } |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2853 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2854 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2855 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2856 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2857 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2858 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2859 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2860 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2861 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2862 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2863 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2864 break; |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2865 case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2866 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2867 case M68K_BSET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2868 case M68K_BTST: |
457
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2869 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : ( |
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2870 inst->op == M68K_BTST ? 6 : (inst->op == M68K_BCLR ? 10 : 8)) |
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
2871 ); |
67 | 2872 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2873 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2874 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2875 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2876 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2877 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2878 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2879 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2880 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2881 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2882 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2883 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2884 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2885 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2886 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2887 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2888 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2889 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2890 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2891 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2892 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2893 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2894 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2895 if (dst_op.mode == MODE_REG_DIRECT) { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2896 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2897 } else { |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2898 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2899 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2900 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2901 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2902 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != SCRATCH1 && src_op.base != SCRATCH2)) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2903 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2904 dst = push_r(dst, SCRATCH2); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2905 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2906 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2907 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2908 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2909 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2910 src_op.base = SCRATCH2; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2911 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2912 if (src_op.mode == MODE_REG_DIRECT) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2913 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2914 } else { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2915 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2916 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2917 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2918 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2919 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2920 uint8_t size = inst->extra.size; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2921 if (dst_op.mode == MODE_REG_DISPLACE8) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2922 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2923 if (src_op.mode == MODE_REG_DIRECT) { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2924 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2925 } else { |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2926 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2927 src_op.mode = MODE_REG_DIRECT; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2928 } |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2929 src_op.base = SCRATCH1; |
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2930 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2931 //b### with register destination is modulo 32 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2932 //x86 with a memory destination isn't modulo anything |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2933 //so use an and here to force the value to be modulo 32 |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2934 dst = and_ir(dst, 31, SCRATCH1, SZ_D); |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2935 } else if(inst->dst.addr_mode != MODE_REG) { |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2936 //b### with memory destination is modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2937 //x86-64 doesn't support 8-bit bit operations |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2938 //so we fake it by forcing the bit number to be modulo 8 |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2939 dst = and_ir(dst, 7, src_op.base, SZ_D); |
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2940 size = SZ_D; |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
2941 } |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2942 if (inst->op == M68K_BTST) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2943 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2944 dst = bt_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2945 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2946 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2947 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2948 } else if (inst->op == M68K_BSET) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2949 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2950 dst = bts_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2951 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2952 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2953 } |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2954 } else if (inst->op == M68K_BCLR) { |
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2955 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2956 dst = btr_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2957 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2958 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2959 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2960 } else { |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2961 if (dst_op.mode == MODE_REG_DIRECT) { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2962 dst = btc_rr(dst, src_op.base, dst_op.base, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2963 } else { |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
2964 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
2965 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2966 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2967 if (src_op.base == SCRATCH2) { |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2968 dst = pop_r(dst, SCRATCH2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2969 } |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2970 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2971 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2972 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2973 dst = setcc_r(dst, CC_NC, FLAG_Z); |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2974 if (inst->op != M68K_BTST) { |
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
2975 dst = m68k_save_result(inst, dst, opts); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2976 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
2977 break; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2978 case M68K_CHK: |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2979 { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2980 dst = cycles(dst, 6); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2981 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2982 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2983 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2984 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
2985 } |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2986 uint32_t isize; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2987 switch(inst->src.addr_mode) |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2988 { |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2989 case MODE_AREG_DISPLACE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2990 case MODE_AREG_INDEX_DISP8: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2991 case MODE_ABSOLUTE_SHORT: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2992 case MODE_PC_INDEX_DISP8: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2993 case MODE_PC_DISPLACE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2994 case MODE_IMMEDIATE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2995 isize = 4; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2996 break; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2997 case MODE_ABSOLUTE: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2998 isize = 6; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
2999 break; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3000 default: |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3001 isize = 2; |
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3002 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3003 uint8_t * passed = dst+1; |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3004 dst = jcc(dst, CC_GE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3005 dst = mov_ir(dst, 1, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3006 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3007 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3008 dst = jmp(dst, opts->trap); |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3009 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3010 if (dst_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3011 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3012 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3013 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3014 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3015 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3016 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3017 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3018 } else if(dst_op.mode == MODE_REG_DISPLACE8) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3019 if (src_op.mode == MODE_REG_DIRECT) { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3020 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3021 } else { |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3022 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3023 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3024 } |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3025 passed = dst+1; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3026 dst = jcc(dst, CC_LE, dst+2); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3027 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3028 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3029 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3030 dst = jmp(dst, opts->trap); |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3031 *passed = dst - (passed+1); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3032 dst = cycles(dst, 4); |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3033 break; |
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3034 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3035 case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3036 case M68K_DIVU: |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3037 { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3038 //TODO: cycle exact division |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3039 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3040 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3041 dst = push_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3042 dst = push_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3043 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3044 dst = mov_rr(dst, dst_op.base, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3045 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3046 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3047 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3048 if (src_op.mode == MODE_IMMED) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3049 dst = mov_ir(dst, (src_op.disp & 0x8000) && inst->op == M68K_DIVS ? src_op.disp | 0xFFFF0000 : src_op.disp, SCRATCH2, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3050 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3051 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3052 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3053 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3054 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3055 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3056 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3057 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3058 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3059 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3060 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3061 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3062 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3063 dst = cmp_ir(dst, 0, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3064 uint8_t * not_zero = dst+1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3065 dst = jcc(dst, CC_NZ, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3066 dst = pop_r(dst, RAX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3067 dst = pop_r(dst, RDX); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3068 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3069 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3070 dst = jmp(dst, opts->trap); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3071 *not_zero = dst - (not_zero+1); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3072 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3073 dst = cdq(dst); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3074 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3075 dst = xor_rr(dst, RDX, RDX, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3076 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3077 if (inst->op == M68K_DIVS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3078 dst = idiv_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3079 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3080 dst = div_r(dst, SCRATCH2, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3081 } |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3082 uint8_t * skip_sec_check; |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3083 if (inst->op == M68K_DIVS) { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3084 dst = cmp_ir(dst, 0x8000, RAX, SZ_D); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3085 skip_sec_check = dst + 1; |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3086 dst = jcc(dst, CC_GE, dst+2); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3087 dst = cmp_ir(dst, -0x8000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3088 norm_off = dst+1; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3089 dst = jcc(dst, CC_L, dst+2); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3090 } else { |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3091 dst = cmp_ir(dst, 0x10000, RAX, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3092 norm_off = dst+1; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3093 dst = jcc(dst, CC_NC, dst+2); |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3094 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3095 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3096 dst = mov_rr(dst, RDX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3097 dst = shl_ir(dst, 16, dst_op.base, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3098 dst = mov_rr(dst, RAX, dst_op.base, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3099 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3100 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3101 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3102 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3103 } |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3104 dst = cmp_ir(dst, 0, RAX, SZ_W); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3105 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3106 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3107 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3108 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3109 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3110 end_off = dst+1; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3111 dst = jmp(dst, dst+2); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3112 *norm_off = dst - (norm_off + 1); |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3113 if (inst->op == M68K_DIVS) { |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3114 *skip_sec_check = dst - (skip_sec_check+1); |
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3115 } |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3116 dst = pop_r(dst, RAX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3117 dst = pop_r(dst, RDX); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3118 dst = mov_ir(dst, 1, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3119 *end_off = dst - (end_off + 1); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3120 break; |
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3121 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3122 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3123 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3124 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3125 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3126 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3127 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3128 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3129 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3130 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3131 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3132 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3133 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3134 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3135 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3136 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3137 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3138 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3139 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3140 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3141 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3142 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3143 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3144 break; |
171 | 3145 case M68K_EORI_CCR: |
3146 case M68K_EORI_SR: | |
3147 dst = cycles(dst, 20); | |
3148 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3149 if (inst->src.params.immed & 0x1) { | |
3150 dst = xor_ir(dst, 1, FLAG_C, SZ_B); | |
3151 } | |
3152 if (inst->src.params.immed & 0x2) { | |
3153 dst = xor_ir(dst, 1, FLAG_V, SZ_B); | |
3154 } | |
3155 if (inst->src.params.immed & 0x4) { | |
3156 dst = xor_ir(dst, 1, FLAG_Z, SZ_B); | |
3157 } | |
3158 if (inst->src.params.immed & 0x8) { | |
3159 dst = xor_ir(dst, 1, FLAG_N, SZ_B); | |
3160 } | |
3161 if (inst->src.params.immed & 0x10) { | |
3162 dst = xor_irdisp8(dst, 1, CONTEXT, 0, SZ_B); | |
3163 } | |
3164 if (inst->op == M68K_ORI_SR) { | |
3165 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); | |
3166 if (inst->src.params.immed & 0x700) { | |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3167 dst = call(dst, opts->do_sync); |
171 | 3168 } |
3169 } | |
3170 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3171 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3172 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3173 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3174 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3175 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3176 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3177 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3178 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3179 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3180 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3181 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3182 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3183 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3184 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3185 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3186 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3187 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3188 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3189 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3190 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3191 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3192 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3193 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3194 case M68K_ILLEGAL: |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
3195 dst = call(dst, opts->save_context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3196 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3197 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3198 break; |
105 | 3199 case M68K_MOVE_FROM_SR: |
3200 //TODO: Trap if not in system mode | |
3201 dst = call(dst, (uint8_t *)get_sr); | |
3202 if (dst_op.mode == MODE_REG_DIRECT) { | |
3203 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W); | |
3204 } else { | |
3205 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W); | |
3206 } | |
3207 dst = m68k_save_result(inst, dst, opts); | |
3208 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3209 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3210 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3211 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3212 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3213 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3214 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3215 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3216 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3217 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3218 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3219 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3220 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3221 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3222 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3223 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3224 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3225 } |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3226 dst = call(dst, opts->do_sync); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3227 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3228 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3229 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3230 if (src_op.base != SCRATCH1) { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3231 if (src_op.mode == MODE_REG_DIRECT) { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3232 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3233 } else { |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3234 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3235 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3236 } |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3237 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr)); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3238 dst = cycles(dst, 12); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3239 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3240 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3241 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3242 case M68K_MOVE_USP: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3243 dst = cycles(dst, BUS); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3244 //TODO: Trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3245 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3246 if (inst->src.addr_mode == MODE_UNUSED) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3247 if (dst_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3248 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3249 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3250 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3251 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3252 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3253 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3254 if (src_op.mode == MODE_REG_DIRECT) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3255 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3256 } else { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3257 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3258 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3259 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3260 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3261 break; |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3262 //case M68K_MOVEP: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3263 case M68K_MULS: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3264 case M68K_MULU: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3265 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3266 if (src_op.mode == MODE_IMMED) { |
223
17534fb7c4f5
Fix muls with a negative immediate source.
Mike Pavone <pavone@retrodev.com>
parents:
221
diff
changeset
|
3267 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : ((src_op.disp & 0x8000) ? src_op.disp | 0xFFFF0000 : src_op.disp), SCRATCH1, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3268 } else if (src_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3269 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3270 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3271 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3272 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3273 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3274 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3275 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3276 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3277 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3278 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3279 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3280 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3281 if (dst_op.mode == MODE_REG_DIRECT) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3282 dst_reg = dst_op.base; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3283 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3284 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3285 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3286 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3287 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3288 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3289 dst_reg = SCRATCH2; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3290 if (inst->op == M68K_MULS) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3291 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3292 } else { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3293 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3294 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3295 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3296 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3297 if (dst_op.mode == MODE_REG_DISPLACE8) { |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3298 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3299 } |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3300 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3301 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3302 dst = cmp_ir(dst, 0, dst_reg, SZ_D); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3303 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3304 dst = setcc_r(dst, CC_S, FLAG_N); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3305 break; |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3306 //case M68K_NBCD: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3307 case M68K_NEG: |
173 | 3308 dst = cycles(dst, BUS); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3309 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3310 dst = neg_r(dst, dst_op.base, inst->extra.size); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3311 } else { |
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
3312 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3313 } |
173 | 3314 dst = setcc_r(dst, CC_C, FLAG_C); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3315 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3316 dst = setcc_r(dst, CC_S, FLAG_N); |
173 | 3317 dst = setcc_r(dst, CC_O, FLAG_V); |
3318 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3319 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3320 break; |
173 | 3321 case M68K_NEGX: |
3322 dst = cycles(dst, BUS); | |
3323 if (dst_op.mode == MODE_REG_DIRECT) { | |
3324 if (dst_op.base == SCRATCH1) { | |
3325 dst = push_r(dst, SCRATCH2); | |
3326 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size); | |
3327 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3328 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size); | |
3329 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size); | |
3330 dst = pop_r(dst, SCRATCH2); | |
3331 } else { | |
3332 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3333 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3334 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size); | |
3335 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size); | |
3336 } | |
3337 } else { | |
3338 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
3339 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); | |
3340 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size); | |
3341 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size); | |
3342 } | |
3343 dst = setcc_r(dst, CC_C, FLAG_C); | |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3344 dst = jcc(dst, CC_Z, dst+4); |
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3345 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
173 | 3346 dst = setcc_r(dst, CC_S, FLAG_N); |
3347 dst = setcc_r(dst, CC_O, FLAG_V); | |
3348 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | |
3349 dst = m68k_save_result(inst, dst, opts); | |
3350 break; | |
3351 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3352 case M68K_NOP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3353 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3354 break; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3355 case M68K_NOT: |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3356 if (dst_op.mode == MODE_REG_DIRECT) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3357 dst = not_r(dst, dst_op.base, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3358 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3359 } else { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3360 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3361 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3362 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3363 |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3364 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3365 dst = setcc_r(dst, CC_Z, FLAG_Z); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3366 dst = setcc_r(dst, CC_S, FLAG_N); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3367 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3368 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3369 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3370 case M68K_OR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3371 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3372 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3373 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3374 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3375 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3376 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3377 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3378 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3379 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3380 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3381 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3382 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3383 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3384 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3385 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3386 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3387 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3388 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3389 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3390 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3391 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3392 break; |
106 | 3393 case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3394 case M68K_ORI_SR: |
106 | 3395 dst = cycles(dst, 20); |
3396 //TODO: If ANDI to SR, trap if not in supervisor mode | |
3397 if (inst->src.params.immed & 0x1) { | |
3398 dst = mov_ir(dst, 1, FLAG_C, SZ_B); | |
3399 } | |
3400 if (inst->src.params.immed & 0x2) { | |
3401 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
3402 } | |
3403 if (inst->src.params.immed & 0x4) { | |
3404 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
3405 } | |
3406 if (inst->src.params.immed & 0x8) { | |
3407 dst = mov_ir(dst, 1, FLAG_N, SZ_B); | |
3408 } | |
3409 if (inst->src.params.immed & 0x10) { | |
3410 dst = mov_irind(dst, 1, CONTEXT, SZ_B); | |
3411 } | |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3412 if (inst->op == M68K_ORI_SR) { |
106 | 3413 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3414 if (inst->src.params.immed & 0x700) { |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3415 dst = call(dst, opts->do_sync); |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3416 } |
106 | 3417 } |
3418 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3419 case M68K_RESET: |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
3420 dst = call(dst, opts->save_context); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3421 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3422 dst = call(dst, (uint8_t *)print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3423 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3424 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3425 case M68K_ROR: |
122 | 3426 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
3427 if (inst->src.addr_mode == MODE_UNUSED) { | |
3428 dst = cycles(dst, BUS); | |
3429 //Memory rotate | |
3430 if (inst->op == M68K_ROL) { | |
3431 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3432 } else { | |
3433 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3434 } | |
3435 dst = setcc_r(dst, CC_C, FLAG_C); | |
3436 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3437 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3438 dst = setcc_r(dst, CC_S, FLAG_N); | |
3439 dst = m68k_save_result(inst, dst, opts); | |
3440 } else { | |
3441 if (src_op.mode == MODE_IMMED) { | |
3442 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); | |
3443 if (dst_op.mode == MODE_REG_DIRECT) { | |
3444 if (inst->op == M68K_ROL) { | |
3445 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3446 } else { | |
3447 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
3448 } | |
3449 } else { | |
3450 if (inst->op == M68K_ROL) { | |
3451 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3452 } else { | |
3453 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
3454 } | |
3455 } | |
3456 dst = setcc_r(dst, CC_C, FLAG_C); | |
3457 } else { | |
3458 if (src_op.mode == MODE_REG_DIRECT) { | |
3459 if (src_op.base != SCRATCH1) { | |
3460 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); | |
3461 } | |
3462 } else { | |
3463 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | |
3464 } | |
3465 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | |
3466 zero_off = dst+1; | |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3467 dst = jcc(dst, CC_Z, dst+2); |
122 | 3468 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
3469 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | |
3470 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | |
3471 norm_off = dst+1; | |
3472 dst = jcc(dst, CC_L, dst+2); | |
442
1a48b31f5316
Fix carry flag on rotate when the register provided rotate bit count is exactly 32
Mike Pavone <pavone@retrodev.com>
parents:
440
diff
changeset
|
3473 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
122 | 3474 if (dst_op.mode == MODE_REG_DIRECT) { |
3475 if (inst->op == M68K_ROL) { | |
3476 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size); | |
3477 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
3478 } else { | |
3479 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size); | |
3480 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
3481 } | |
3482 } else { | |
3483 if (inst->op == M68K_ROL) { | |
3484 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3485 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3486 } else { | |
3487 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
3488 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
3489 } | |
3490 } | |
3491 *norm_off = dst - (norm_off+1); | |
3492 if (dst_op.mode == MODE_REG_DIRECT) { | |
3493 if (inst->op == M68K_ROL) { | |
3494 dst = rol_clr(dst, dst_op.base, inst->extra.size); | |
3495 } else { | |
3496 dst = ror_clr(dst, dst_op.base, inst->extra.size); | |
3497 } | |
3498 } else { | |
3499 if (inst->op == M68K_ROL) { | |
3500 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3501 } else { | |
3502 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
3503 } | |
3504 } | |
3505 dst = setcc_r(dst, CC_C, FLAG_C); | |
3506 end_off = dst + 1; | |
3507 dst = jmp(dst, dst+2); | |
3508 *zero_off = dst - (zero_off+1); | |
3509 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
3510 *end_off = dst - (end_off+1); | |
3511 } | |
3512 if (dst_op.mode == MODE_REG_DIRECT) { | |
3513 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
3514 } else { | |
3515 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); | |
3516 } | |
3517 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
3518 dst = setcc_r(dst, CC_S, FLAG_N); | |
3519 } | |
3520 break; | |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3521 case M68K_ROXL: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3522 case M68K_ROXR: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3523 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3524 if (inst->src.addr_mode == MODE_UNUSED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3525 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3526 //Memory rotate |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3527 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3528 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3529 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3530 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3531 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3532 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3533 dst = setcc_r(dst, CC_C, FLAG_C); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3534 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3535 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3536 dst = setcc_r(dst, CC_S, FLAG_N); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3537 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3538 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3539 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3540 if (src_op.mode == MODE_IMMED) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3541 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3542 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3543 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3544 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3545 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3546 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3547 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3548 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3549 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3550 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3551 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3552 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3553 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3554 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3555 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3556 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3557 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3558 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3559 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3560 if (src_op.base != SCRATCH1) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3561 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3562 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3563 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3564 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3565 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3566 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3567 zero_off = dst+1; |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3568 dst = jcc(dst, CC_Z, dst+2); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3569 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3570 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3571 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3572 norm_off = dst+1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3573 dst = jcc(dst, CC_L, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3574 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3575 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3576 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3577 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3578 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3579 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3580 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3581 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3582 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3583 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3584 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3585 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3586 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3587 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3588 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3589 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3590 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3591 } |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3592 dst = setcc_rind(dst, CC_C, CONTEXT); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3593 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3594 *norm_off = dst - (norm_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3595 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3596 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3597 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3598 dst = rcl_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3599 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3600 dst = rcr_clr(dst, dst_op.base, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3601 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3602 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3603 if (inst->op == M68K_ROXL) { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3604 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3605 } else { |
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3606 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3607 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3608 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3609 dst = setcc_r(dst, CC_C, FLAG_C); |
225
7348057e7a8c
Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Mike Pavone <pavone@retrodev.com>
parents:
223
diff
changeset
|
3610 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3611 end_off = dst + 1; |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3612 dst = jmp(dst, dst+2); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3613 *zero_off = dst - (zero_off+1); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3614 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3615 dst = mov_rindr(dst, CONTEXT, FLAG_C, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3616 *end_off = dst - (end_off+1); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3617 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3618 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3619 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3620 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3621 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3622 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3623 dst = setcc_r(dst, CC_Z, FLAG_Z); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3624 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3625 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3626 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3627 case M68K_RTE: |
170 | 3628 //TODO: Trap if not in system mode |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3629 //Read saved SR |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3630 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3631 dst = call(dst, opts->read_16); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3632 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3633 dst = call(dst, (uint8_t *)set_sr); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3634 //Read saved PC |
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3635 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3636 dst = call(dst, opts->read_32); |
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3637 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3638 //Check if we've switched to user mode and swap stack pointers if needed |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3639 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3640 end_off = dst+1; |
121
f848aad2abef
Fix logic for switching between USP and SSP
Mike Pavone <pavone@retrodev.com>
parents:
119
diff
changeset
|
3641 dst = jcc(dst, CC_C, dst+2); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3642 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3643 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3644 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3645 *end_off = dst - (end_off+1); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3646 //Get native address, sync components, recalculate integer points and jump to returned address |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
3647 dst = call(dst, opts->native_addr_and_sync); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3648 dst = jmp_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3649 break; |
170 | 3650 case M68K_RTR: |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3651 //Read saved CCR |
170 | 3652 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3653 dst = call(dst, opts->read_16); |
170 | 3654 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
3655 dst = call(dst, (uint8_t *)set_ccr); | |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3656 //Read saved PC |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3657 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3658 dst = call(dst, opts->read_32); |
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3659 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3660 //Get native address and jump to it |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
3661 dst = call(dst, opts->native_addr); |
170 | 3662 dst = jmp_r(dst, SCRATCH1); |
3663 break; | |
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3664 case M68K_SBCD: |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3665 if (src_op.base != SCRATCH2) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3666 if (src_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3667 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3668 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3669 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3670 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3671 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3672 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3673 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3674 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3675 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3676 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3677 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3678 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3679 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3680 dst = jcc(dst, CC_NC, dst+5); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3681 dst = sub_ir(dst, 1, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3682 dst = call(dst, (uint8_t *)bcd_sub); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3683 dst = mov_rr(dst, CH, FLAG_C, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3684 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3685 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3686 dst = jcc(dst, CC_Z, dst+4); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3687 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3688 if (dst_op.base != SCRATCH1) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3689 if (dst_op.mode == MODE_REG_DIRECT) { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3690 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3691 } else { |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3692 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3693 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3694 } |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3695 dst = m68k_save_result(inst, dst, opts); |
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3696 break; |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3697 case M68K_STOP: { |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3698 //TODO: Trap if not in system mode |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3699 //manual says 4 cycles, but it has to be at least 8 since it's a 2-word instruction |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3700 //possibly even 12 since that's how long MOVE to SR takes |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3701 dst = cycles(dst, BUS*2); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3702 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3703 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3704 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3705 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3706 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3707 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3708 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3709 //leave supervisor mode |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3710 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3711 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3712 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3713 } |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3714 uint8_t * loop_top = dst; |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3715 dst = call(dst, opts->do_sync); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3716 dst = cmp_rr(dst, LIMIT, CYCLES, SZ_D); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3717 uint8_t * normal_cycle_up = dst + 1; |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3718 dst = jcc(dst, CC_A, dst+2); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3719 dst = cycles(dst, BUS); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3720 uint8_t * after_cycle_up = dst + 1; |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3721 dst = jmp(dst, dst+2); |
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3722 *normal_cycle_up = dst - (normal_cycle_up + 1); |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3723 dst = mov_rr(dst, LIMIT, CYCLES, SZ_D); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3724 *after_cycle_up = dst - (after_cycle_up+1); |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3725 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3726 dst = jcc(dst, CC_C, loop_top); |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3727 break; |
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3728 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3729 case M68K_SUB: |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3730 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3731 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3732 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3733 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3734 dst = sub_rr(dst, src_op.base, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3735 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3736 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3737 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3738 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3739 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3740 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3741 if (dst_op.mode == MODE_REG_DIRECT) { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3742 dst = sub_ir(dst, src_op.disp, dst_op.base, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3743 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3744 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3745 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3746 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3747 if (inst->dst.addr_mode != MODE_AREG) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3748 dst = setcc_r(dst, CC_C, FLAG_C); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3749 dst = setcc_r(dst, CC_Z, FLAG_Z); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3750 dst = setcc_r(dst, CC_S, FLAG_N); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3751 dst = setcc_r(dst, CC_O, FLAG_V); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3752 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3753 } |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3754 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3755 break; |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3756 case M68K_SUBX: |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3757 dst = cycles(dst, BUS); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3758 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3759 if (src_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3760 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3761 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3762 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3763 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3764 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3765 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3766 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3767 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3768 if (dst_op.mode == MODE_REG_DIRECT) { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3769 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3770 } else { |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3771 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3772 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3773 } |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3774 dst = setcc_r(dst, CC_C, FLAG_C); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3775 dst = jcc(dst, CC_Z, dst+4); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3776 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3777 dst = setcc_r(dst, CC_S, FLAG_N); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3778 dst = setcc_r(dst, CC_O, FLAG_V); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3779 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3780 dst = m68k_save_result(inst, dst, opts); |
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3781 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3782 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3783 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3784 if (src_op.mode == MODE_REG_DIRECT) { |
129 | 3785 dst = rol_ir(dst, 16, src_op.base, SZ_D); |
443 | 3786 dst = cmp_ir(dst, 0, src_op.base, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3787 } else{ |
129 | 3788 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D); |
443 | 3789 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, SZ_D); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3790 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3791 |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3792 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3793 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3794 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3795 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3796 break; |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3797 //case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3798 case M68K_TRAP: |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3799 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
182
diff
changeset
|
3800 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3801 dst = jmp(dst, opts->trap); |
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3802 break; |
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
3803 //case M68K_TRAPV: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3804 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3805 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3806 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3807 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3808 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3809 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3810 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3811 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3812 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3813 dst = setcc_r(dst, CC_S, FLAG_N); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3814 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3815 break; |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3816 case M68K_UNLK: |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3817 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3818 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3819 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3820 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3821 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3822 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3823 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3824 dst = call(dst, opts->read_32); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3825 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3826 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3827 } else { |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3828 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3829 } |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
3830 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
3831 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3832 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3833 m68k_disasm(inst, disasm_buf); |
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3834 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op); |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
3835 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3836 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3837 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3838 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3839 |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3840 uint8_t m68k_is_terminal(m68kinst * inst) |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3841 { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3842 return inst->op == M68K_RTS || inst->op == M68K_RTE || inst->op == M68K_RTR || inst->op == M68K_JMP |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3843 || inst->op == M68K_TRAP || inst->op == M68K_ILLEGAL || inst->op == M68K_INVALID || inst->op == M68K_RESET |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3844 || (inst->op == M68K_BCC && inst->extra.cond == COND_TRUE); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3845 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3846 |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3847 void m68k_handle_deferred(m68k_context * context) |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3848 { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3849 x86_68k_options * opts = context->options; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3850 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3851 if (opts->deferred) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3852 translate_m68k_stream(opts->deferred->address, context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3853 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3854 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3855 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3856 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3857 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3858 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3859 x86_68k_options * opts = context->options; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3860 uint8_t * dst = opts->cur_code; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3861 uint8_t * dst_end = opts->code_end; |
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
3862 address &= 0xFFFFFF; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3863 if(get_native_address(opts->native_code_map, address)) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3864 return dst; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3865 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3866 char disbuf[1024]; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3867 uint16_t *encoded, *next; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3868 if ((address & 0xFFFFFF) < 0x400000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3869 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3870 } else if ((address & 0xFFFFFF) > 0xE00000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3871 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3872 } else { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3873 printf("attempt to translate non-memory address: %X\n", address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3874 exit(1); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3875 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3876 do { |
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3877 if (opts->address_log) { |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3878 fprintf(opts->address_log, "%X\n", address); |
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
3879 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3880 do { |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3881 if (dst_end-dst < MAX_NATIVE_SIZE) { |
102
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3882 if (dst_end-dst < 5) { |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3883 puts("out of code memory, not enough space for jmp to next chunk"); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3884 exit(1); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3885 } |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3886 size_t size = 1024*1024; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3887 opts->cur_code = alloc_code(&size); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3888 opts->code_end = opts->cur_code + size; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3889 jmp(dst, opts->cur_code); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3890 dst = opts->cur_code; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
3891 dst_end = opts->code_end; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3892 } |
159
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3893 if (address >= 0x400000 && address < 0xE00000) { |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3894 dst = xor_rr(dst, RDI, RDI, SZ_D); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3895 dst = call(dst, (uint8_t *)exit); |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3896 break; |
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
3897 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3898 uint8_t * existing = get_native_address(opts->native_code_map, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3899 if (existing) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3900 dst = jmp(dst, existing); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3901 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3902 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3903 next = m68k_decode(encoded, &instbuf, address); |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3904 if (instbuf.op == M68K_INVALID) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3905 instbuf.src.params.immed = *encoded; |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
3906 } |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3907 uint16_t m68k_size = (next-encoded)*2; |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3908 address += m68k_size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3909 encoded = next; |
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3910 //m68k_disasm(&instbuf, disbuf); |
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3911 //printf("%X: %s\n", instbuf.address, disbuf); |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3912 uint8_t * after = translate_m68k(dst, &instbuf, opts); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3913 map_native_address(context, instbuf.address, dst, m68k_size, after-dst); |
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
3914 dst = after; |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3915 } while(!m68k_is_terminal(&instbuf)); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
3916 process_deferred(&opts->deferred, context, (native_addr_func)get_native_from_context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3917 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3918 address = opts->deferred->address; |
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3919 if ((address & 0xFFFFFF) < 0x400000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3920 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3921 } else if ((address & 0xFFFFFF) > 0xE00000) { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3922 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3923 } else { |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3924 printf("attempt to translate non-memory address: %X\n", address); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3925 exit(1); |
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
3926 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3927 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3928 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3929 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3930 } while(encoded != NULL); |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3931 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3932 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3933 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3934 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3935 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address) |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3936 { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3937 address &= 0xFFFFFF; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3938 uint8_t * ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3939 if (!ret) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3940 translate_m68k_stream(address, context); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3941 ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3942 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3943 return ret; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3944 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
3945 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3946 void * m68k_retranslate_inst(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3947 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3948 x86_68k_options * opts = context->options; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3949 uint8_t orig_size = get_native_inst_size(opts, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3950 uint8_t * orig_start = get_native_address(context->native_code_map, address); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3951 uint32_t orig = address; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3952 address &= 0xFFFF; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3953 uint8_t * dst = opts->cur_code; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3954 uint8_t * dst_end = opts->code_end; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3955 uint16_t *after, *inst = context->mem_pointers[1] + address/2; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3956 m68kinst instbuf; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3957 after = m68k_decode(inst, &instbuf, orig); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3958 if (orig_size != MAX_NATIVE_SIZE) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3959 if (dst_end - dst < 128) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3960 size_t size = 1024*1024; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3961 dst = alloc_code(&size); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3962 opts->code_end = dst_end = dst + size; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3963 opts->cur_code = dst; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3964 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3965 deferred_addr * orig_deferred = opts->deferred; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3966 uint8_t * native_end = translate_m68k(dst, &instbuf, opts); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3967 uint8_t is_terminal = m68k_is_terminal(&instbuf); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3968 if ((native_end - dst) <= orig_size) { |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3969 uint8_t * native_next; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3970 if (!is_terminal) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3971 native_next = get_native_address(context->native_code_map, orig + (after-inst)*2); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3972 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3973 if (is_terminal || (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5))) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3974 remove_deferred_until(&opts->deferred, orig_deferred); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3975 native_end = translate_m68k(orig_start, &instbuf, opts); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3976 if (!is_terminal) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3977 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3978 while (native_end < orig_start + orig_size) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3979 *(native_end++) = 0x90; //NOP |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3980 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3981 } else { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3982 jmp(native_end, native_next); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3983 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3984 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3985 m68k_handle_deferred(context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3986 return orig_start; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3987 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3988 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3989 |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3990 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3991 opts->cur_code = dst+MAX_NATIVE_SIZE; |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3992 jmp(orig_start, dst); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3993 if (!m68k_is_terminal(&instbuf)) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3994 jmp(native_end, get_native_address_trans(context, orig + (after-inst)*2)); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3995 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3996 m68k_handle_deferred(context); |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
3997 return dst; |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3998 } else { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
3999 dst = translate_m68k(orig_start, &instbuf, opts); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4000 if (!m68k_is_terminal(&instbuf)) { |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4001 dst = jmp(dst, get_native_address_trans(context, orig + (after-inst)*2)); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4002 } |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4003 m68k_handle_deferred(context); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4004 return orig_start; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4005 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4006 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4007 |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4008 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4009 { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4010 uint32_t inst_start = get_instruction_start(context->native_code_map, address | 0xFF0000); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4011 if (inst_start) { |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4012 uint8_t * dst = get_native_address(context->native_code_map, inst_start); |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4013 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D); |
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4014 x86_68k_options * options = context->options; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4015 if (!options->retrans_stub) { |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4016 if (options->code_end - options->cur_code < 32) { |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4017 size_t size = 1024*1024; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4018 options->cur_code = alloc_code(&size); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4019 options->code_end = options->cur_code + size; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4020 } |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4021 uint8_t * rdst = options->retrans_stub = options->cur_code; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4022 rdst = call(rdst, options->save_context); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4023 rdst = push_r(rdst, CONTEXT); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4024 rdst = call(rdst, (uint8_t *)m68k_retranslate_inst); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4025 rdst = pop_r(rdst, CONTEXT); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4026 rdst = mov_rr(rdst, RAX, SCRATCH1, SZ_Q); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4027 rdst = call(rdst, options->load_context); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4028 rdst = jmp_r(rdst, SCRATCH1); |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4029 options->cur_code = rdst; |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4030 } |
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4031 dst = jmp(dst, options->retrans_stub); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4032 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4033 return context; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4034 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4035 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4036 void insert_breakpoint(m68k_context * context, uint32_t address, uint8_t * bp_handler) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4037 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4038 static uint8_t * bp_stub = NULL; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4039 uint8_t * native = get_native_address_trans(context, address); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4040 uint8_t * start_native = native; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4041 native = mov_ir(native, address, SCRATCH1, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4042 if (!bp_stub) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4043 x86_68k_options * opts = context->options; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4044 uint8_t * dst = opts->cur_code; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4045 uint8_t * dst_end = opts->code_end; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4046 if (dst_end - dst < 128) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4047 size_t size = 1024*1024; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4048 dst = alloc_code(&size); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4049 opts->code_end = dst_end = dst + size; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4050 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4051 bp_stub = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4052 native = call(native, bp_stub); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4053 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4054 //Calculate length of prologue |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4055 dst = check_cycles_int(dst, address, opts); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4056 int check_int_size = dst-bp_stub; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4057 dst = bp_stub; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4058 |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4059 //Save context and call breakpoint handler |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4060 dst = call(dst, opts->save_context); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4061 dst = push_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4062 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4063 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4064 dst = call(dst, bp_handler); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4065 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4066 //Restore context |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4067 dst = call(dst, opts->load_context); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4068 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4069 //do prologue stuff |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4070 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4071 uint8_t * jmp_off = dst+1; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4072 dst = jcc(dst, CC_NC, dst + 7); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4073 dst = call(dst, opts->handle_cycle_limit_int); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4074 *jmp_off = dst - (jmp_off+1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4075 //jump back to body of translated instruction |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4076 dst = pop_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4077 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4078 dst = jmp_r(dst, SCRATCH1); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4079 opts->cur_code = dst; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4080 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4081 native = call(native, bp_stub); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4082 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4083 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4084 |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4085 void remove_breakpoint(m68k_context * context, uint32_t address) |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4086 { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4087 uint8_t * native = get_native_address(context->native_code_map, address); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4088 check_cycles_int(native, address, context->options); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4089 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4090 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4091 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4092 { |
424
7e8e179116af
Add support for loading GST format savestates
Mike Pavone <pavone@retrodev.com>
parents:
423
diff
changeset
|
4093 uint8_t * addr = get_native_address_trans(context, address); |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4094 x86_68k_options * options = context->options; |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4095 options->start_context(addr, context); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4096 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4097 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4098 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4099 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4100 //TODO: Make this actually use the normal read functions |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4101 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4102 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4103 start_68k_context(context, address); |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4104 } |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4105 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4106 typedef enum { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4107 READ_16, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4108 READ_8, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4109 WRITE_16, |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4110 WRITE_8 |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4111 } ftype; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4112 |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4113 uint8_t * gen_mem_fun(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4114 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4115 uint8_t * dst = opts->cur_code; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4116 uint8_t * start = dst; |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4117 dst = check_cycles(dst, opts); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4118 dst = cycles(dst, BUS); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4119 dst = and_ir(dst, 0xFFFFFF, SCRATCH1, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4120 uint8_t *lb_jcc = NULL, *ub_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4121 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4122 uint8_t adr_reg = is_write ? SCRATCH2 : SCRATCH1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4123 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4124 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4125 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4126 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4127 if (memmap[chunk].start > 0) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4128 dst = cmp_ir(dst, memmap[chunk].start, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4129 lb_jcc = dst + 1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4130 dst = jcc(dst, CC_C, dst+2); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4131 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4132 if (memmap[chunk].end < 0x1000000) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4133 dst = cmp_ir(dst, memmap[chunk].end, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4134 ub_jcc = dst + 1; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4135 dst = jcc(dst, CC_NC, dst+2); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4136 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4137 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4138 if (memmap[chunk].mask != 0xFFFFFF) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4139 dst = and_ir(dst, memmap[chunk].mask, adr_reg, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4140 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4141 void * cfun; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4142 switch (fun_type) |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4143 { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4144 case READ_16: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4145 cfun = memmap[chunk].read_16; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4146 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4147 case READ_8: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4148 cfun = memmap[chunk].read_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4149 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4150 case WRITE_16: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4151 cfun = memmap[chunk].write_16; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4152 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4153 case WRITE_8: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4154 cfun = memmap[chunk].write_8; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4155 break; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4156 default: |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4157 cfun = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4158 } |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4159 if(memmap[chunk].buffer && memmap[chunk].flags & access_flag) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4160 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4161 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4162 dst = cmp_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4163 uint8_t * not_null = dst+1; |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4164 dst = jcc(dst, CC_NZ, dst+2); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4165 dst = call(dst, opts->save_context); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4166 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4167 //SCRATCH2 is RDI, so no need to move it there |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4168 dst = mov_rr(dst, SCRATCH1, RDX, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4169 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4170 dst = push_r(dst, CONTEXT); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4171 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4172 } |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4173 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4174 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4175 dst = jcc(dst, CC_NZ, dst+2); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4176 dst = call(dst, cfun); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4177 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4178 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4179 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4180 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4181 dst = call(dst, cfun); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4182 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4183 *no_adjust = dst - (no_adjust + 1); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4184 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4185 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4186 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4187 dst = pop_r(dst, CONTEXT); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4188 dst = mov_rr(dst, RAX, SCRATCH1, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4189 } |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4190 dst = jmp(dst, opts->load_context); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4191 |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4192 *not_null = dst - (not_null + 1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4193 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4194 if (size == SZ_B) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4195 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4196 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4197 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4198 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4199 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, size); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4200 |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4201 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4202 dst = mov_rindr(dst, SCRATCH1, SCRATCH1, size); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4203 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4204 } else { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4205 uint8_t tmp_size = size; |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4206 if (size == SZ_B) { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4207 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4208 dst = bt_ir(dst, 0, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4209 uint8_t * good_addr = dst + 1; |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4210 dst = jcc(dst, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, dst+2); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4211 if (!is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4212 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4213 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4214 dst = retn(dst); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4215 *good_addr = dst - (good_addr + 1); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4216 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4217 } else { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4218 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4219 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4220 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4221 tmp_size = SZ_B; |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4222 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4223 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4224 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4225 } |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4226 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4227 if ((int64_t)memmap[chunk].buffer <= 0x7FFFFFFF && (int64_t)memmap[chunk].buffer >= -2147483648) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4228 if (is_write) { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4229 dst = mov_rrdisp32(dst, SCRATCH1, SCRATCH2, (int64_t)memmap[chunk].buffer, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4230 } else { |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4231 dst = mov_rdisp32r(dst, SCRATCH1, (int64_t)memmap[chunk].buffer, SCRATCH1, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4232 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4233 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4234 if (is_write) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4235 dst = push_r(dst, SCRATCH1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4236 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH1, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4237 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_Q); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4238 dst = pop_r(dst, SCRATCH1); |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4239 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, tmp_size); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4240 } else { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4241 dst = mov_ir(dst, (int64_t)memmap[chunk].buffer, SCRATCH2, SZ_Q); |
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4242 dst = mov_rindexr(dst, SCRATCH2, SCRATCH1, 1, SCRATCH1, tmp_size); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4243 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4244 } |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4245 if (size != tmp_size && !is_write) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4246 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4247 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4248 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4249 } else { |
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4250 dst = or_ir(dst, 0xFF00, SCRATCH1, SZ_W); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4251 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4252 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4253 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4254 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4255 dst = mov_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4256 dst = shr_ir(dst, 11, SCRATCH1, SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4257 dst = bt_rrdisp32(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, ram_code_flags), SZ_D); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4258 uint8_t * not_code = dst+1; |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4259 dst = jcc(dst, CC_NC, dst+2); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4260 dst = call(dst, opts->save_context); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4261 dst = call(dst, (uint8_t *)m68k_handle_code_write); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4262 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4263 dst = call(dst, opts->load_context); |
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4264 *not_code = dst - (not_code+1); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4265 } |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4266 dst = retn(dst); |
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4267 } else if (cfun) { |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4268 dst = call(dst, opts->save_context); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4269 if (is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4270 //SCRATCH2 is RDI, so no need to move it there |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4271 dst = mov_rr(dst, SCRATCH1, RDX, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4272 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4273 dst = push_r(dst, CONTEXT); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4274 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4275 } |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4276 dst = test_ir(dst, 8, RSP, SZ_D); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4277 uint8_t *adjust_rsp = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4278 dst = jcc(dst, CC_NZ, dst+2); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4279 dst = call(dst, cfun); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4280 uint8_t *no_adjust = dst+1; |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4281 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4282 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4283 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4284 dst = call(dst, cfun); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4285 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4286 *no_adjust = dst - (no_adjust+1); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4287 if (is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4288 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4289 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4290 dst = pop_r(dst, CONTEXT); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4291 dst = mov_rr(dst, RAX, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4292 } |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4293 dst = jmp(dst, opts->load_context); |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4294 } else { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4295 //Not sure the best course of action here |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4296 if (!is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4297 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4298 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4299 dst = retn(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4300 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4301 if (lb_jcc) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4302 *lb_jcc = dst - (lb_jcc+1); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4303 lb_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4304 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4305 if (ub_jcc) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4306 *ub_jcc = dst - (ub_jcc+1); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4307 ub_jcc = NULL; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4308 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4309 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4310 if (!is_write) { |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4311 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4312 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4313 dst = retn(dst); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4314 opts->cur_code = dst; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4315 return start; |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4316 } |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4317 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4318 void init_x86_68k_opts(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4319 { |
440 | 4320 memset(opts, 0, sizeof(*opts)); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4321 for (int i = 0; i < 8; i++) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4322 opts->dregs[i] = opts->aregs[i] = -1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4323 opts->dregs[0] = R10; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4324 opts->dregs[1] = R11; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4325 opts->dregs[2] = R12; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4326 opts->dregs[3] = R8; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4327 opts->aregs[0] = R13; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4328 opts->aregs[1] = R14; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4329 opts->aregs[2] = R9; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4330 opts->aregs[7] = R15; |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4331 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4332 opts->flag_regs[0] = -1; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4333 opts->flag_regs[1] = RBX; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4334 opts->flag_regs[2] = RDX; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4335 opts->flag_regs[3] = BH; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4336 opts->flag_regs[4] = DH; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4337 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4338 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4339 opts->deferred = NULL; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4340 size_t size = 1024 * 1024; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4341 opts->cur_code = alloc_code(&size); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4342 opts->code_end = opts->cur_code + size; |
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4343 opts->ram_inst_sizes = malloc(sizeof(uint8_t *) * 64); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4344 memset(opts->ram_inst_sizes, 0, sizeof(uint8_t *) * 64); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4345 |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4346 uint8_t * dst = opts->cur_code; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4347 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4348 opts->save_context = dst; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4349 for (int i = 0; i < 5; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4350 if (opts->flag_regs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4351 dst = mov_rrdisp8(dst, opts->flag_regs[i], CONTEXT, offsetof(m68k_context, flags) + i, SZ_B); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4352 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4353 for (int i = 0; i < 8; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4354 { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4355 if (opts->dregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4356 dst = mov_rrdisp8(dst, opts->dregs[i], CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4357 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4358 if (opts->aregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4359 dst = mov_rrdisp8(dst, opts->aregs[i], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4360 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4361 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4362 dst = mov_rrdisp8(dst, CYCLES, CONTEXT, offsetof(m68k_context, current_cycle), SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4363 dst = retn(dst); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4364 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4365 opts->load_context = dst; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4366 for (int i = 0; i < 5; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4367 if (opts->flag_regs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4368 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + i, opts->flag_regs[i], SZ_B); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4369 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4370 for (int i = 0; i < 8; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4371 { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4372 if (opts->dregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4373 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, opts->dregs[i], SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4374 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4375 if (opts->aregs[i] >= 0) { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4376 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, opts->aregs[i], SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4377 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4378 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4379 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, current_cycle), CYCLES, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4380 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, target_cycle), LIMIT, SZ_D); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4381 dst = retn(dst); |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4382 |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4383 opts->start_context = (start_fun)dst; |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4384 //save callee save registers |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4385 dst = push_r(dst, RBP); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4386 dst = push_r(dst, R12); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4387 dst = push_r(dst, R13); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4388 dst = push_r(dst, R14); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4389 dst = push_r(dst, R15); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4390 dst = call(dst, opts->load_context); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4391 dst = call_r(dst, RDI); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4392 dst = call(dst, opts->save_context); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4393 //restore callee save registers |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4394 dst = pop_r(dst, R15); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4395 dst = pop_r(dst, R14); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4396 dst = pop_r(dst, R13); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4397 dst = pop_r(dst, R12); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4398 dst = pop_r(dst, RBP); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4399 dst = retn(dst); |
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4400 |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4401 opts->native_addr = dst; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4402 dst = call(dst, opts->save_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4403 dst = push_r(dst, CONTEXT); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4404 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); //move context to 1st arg reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4405 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); //move address to 2nd arg reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4406 dst = call(dst, (uint8_t *)get_native_address_trans); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4407 dst = mov_rr(dst, RAX, SCRATCH1, SZ_Q); //move result to scratch reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4408 dst = pop_r(dst, CONTEXT); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4409 dst = call(dst, opts->load_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4410 dst = retn(dst); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4411 |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4412 opts->native_addr_and_sync = dst; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4413 dst = call(dst, opts->save_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4414 dst = push_r(dst, SCRATCH1); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4415 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4416 dst = xor_rr(dst, RSI, RSI, SZ_D); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4417 dst = test_ir(dst, 8, RSP, SZ_Q); //check stack alignment |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4418 uint8_t * do_adjust_rsp = dst+1; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4419 dst = jcc(dst, CC_NZ, dst+2); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4420 dst = call(dst, (uint8_t *)sync_components); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4421 uint8_t * no_adjust_rsp = dst+1; |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4422 dst = jmp(dst, dst+2); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4423 *do_adjust_rsp = dst - (do_adjust_rsp+1); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4424 dst = sub_ir(dst, 8, RSP, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4425 dst = call(dst, (uint8_t *)sync_components); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4426 dst = add_ir(dst, 8, RSP, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4427 *no_adjust_rsp = dst - (no_adjust_rsp+1); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4428 dst = pop_r(dst, RSI); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4429 dst = push_r(dst, RAX); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4430 dst = mov_rr(dst, RAX, RDI, SZ_Q); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4431 dst = call(dst, (uint8_t *)get_native_address_trans); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4432 dst = mov_rr(dst, RAX, SCRATCH1, SZ_Q); //move result to scratch reg |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4433 dst = pop_r(dst, CONTEXT); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4434 dst = call(dst, opts->load_context); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4435 dst = retn(dst); |
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4436 |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4437 opts->handle_cycle_limit = dst; |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4438 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4439 uint8_t * skip_sync = dst+1; |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4440 dst = jcc(dst, CC_C, dst+2); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4441 opts->do_sync = dst; |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4442 dst = push_r(dst, SCRATCH1); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4443 dst = push_r(dst, SCRATCH2); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4444 dst = call(dst, opts->save_context); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4445 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4446 dst = xor_rr(dst, RSI, RSI, SZ_D); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4447 dst = test_ir(dst, 8, RSP, SZ_D); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4448 uint8_t *adjust_rsp = dst+1; |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4449 dst = jcc(dst, CC_NZ, dst+2); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4450 dst = call(dst, (uint8_t *)sync_components); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4451 uint8_t *no_adjust = dst+1; |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4452 dst = jmp(dst, dst+2); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4453 *adjust_rsp = dst - (adjust_rsp + 1); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4454 dst = sub_ir(dst, 8, RSP, SZ_Q); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4455 dst = call(dst, (uint8_t *)sync_components); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4456 dst = add_ir(dst, 8, RSP, SZ_Q); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4457 *no_adjust = dst - (no_adjust+1); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4458 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4459 dst = call(dst, opts->load_context); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4460 dst = pop_r(dst, SCRATCH2); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4461 dst = pop_r(dst, SCRATCH1); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4462 *skip_sync = dst - (skip_sync+1); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4463 dst = retn(dst); |
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4464 |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4465 opts->cur_code = dst; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4466 |
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4467 opts->read_16 = gen_mem_fun(opts, memmap, num_chunks, READ_16); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4468 opts->read_8 = gen_mem_fun(opts, memmap, num_chunks, READ_8); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4469 opts->write_16 = gen_mem_fun(opts, memmap, num_chunks, WRITE_16); |
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4470 opts->write_8 = gen_mem_fun(opts, memmap, num_chunks, WRITE_8); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4471 |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4472 dst = opts->cur_code; |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4473 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4474 opts->read_32 = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4475 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4476 dst = call(dst, opts->read_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4477 dst = mov_rr(dst, SCRATCH1, SCRATCH2, SZ_W); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4478 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4479 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4480 dst = add_ir(dst, 2, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4481 dst = call(dst, opts->read_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4482 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4483 dst = movzx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4484 dst = shl_ir(dst, 16, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4485 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4486 dst = retn(dst); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4487 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4488 opts->write_32_lowfirst = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4489 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4490 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4491 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4492 dst = call(dst, opts->write_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4493 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4494 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4495 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4496 dst = jmp(dst, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4497 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4498 opts->write_32_highfirst = dst; |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4499 dst = push_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4500 dst = push_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4501 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4502 dst = call(dst, opts->write_16); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4503 dst = pop_r(dst, SCRATCH2); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4504 dst = pop_r(dst, SCRATCH1); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4505 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4506 dst = jmp(dst, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4507 |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4508 opts->handle_cycle_limit_int = dst; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4509 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4510 uint8_t * do_int = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4511 dst = jcc(dst, CC_NC, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4512 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D); |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4513 skip_sync = dst+1; |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4514 dst = jcc(dst, CC_C, dst+2); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4515 dst = call(dst, opts->save_context); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4516 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4517 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4518 dst = test_ir(dst, 8, RSP, SZ_D); |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4519 adjust_rsp = dst+1; |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4520 dst = jcc(dst, CC_NZ, dst+2); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4521 dst = call(dst, (uint8_t *)sync_components); |
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4522 no_adjust = dst+1; |
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4523 dst = jmp(dst, dst+2); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4524 *adjust_rsp = dst - (adjust_rsp + 1); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4525 dst = sub_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4526 dst = call(dst, (uint8_t *)sync_components); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4527 dst = add_ir(dst, 8, RSP, SZ_Q); |
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4528 *no_adjust = dst - (no_adjust+1); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4529 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4530 dst = jmp(dst, opts->load_context); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4531 *skip_sync = dst - (skip_sync+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4532 dst = retn(dst); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4533 *do_int = dst - (do_int+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4534 //set target cycle to sync cycle |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4535 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), LIMIT, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4536 //swap USP and SSP if not already in supervisor mode |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4537 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4538 uint8_t *already_supervisor = dst+1; |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4539 dst = jcc(dst, CC_C, dst+2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4540 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4541 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4542 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4543 *already_supervisor = dst - (already_supervisor+1); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4544 //save PC |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4545 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4546 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4547 dst = call(dst, opts->write_32_lowfirst); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4548 //save status register |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4549 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4550 dst = call(dst, (uint8_t *)get_sr); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4551 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4552 dst = call(dst, opts->write_16); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4553 //update status register |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4554 dst = and_irdisp8(dst, 0xF8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4555 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4556 dst = or_ir(dst, 0x20, SCRATCH1, SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4557 dst = or_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, status), SZ_B); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4558 //calculate interrupt vector address |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4559 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4560 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, int_ack), SZ_W); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4561 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4562 dst = add_ir(dst, 0x60, SCRATCH1, SZ_D); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4563 dst = call(dst, opts->read_32); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4564 dst = call(dst, opts->native_addr_and_sync); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4565 dst = cycles(dst, 24); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4566 //discard function return address |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4567 dst = pop_r(dst, SCRATCH2); |
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4568 dst = jmp_r(dst, SCRATCH1); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4569 |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4570 opts->trap = dst; |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4571 dst = push_r(dst, SCRATCH2); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4572 //swap USP and SSP if not already in supervisor mode |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4573 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4574 already_supervisor = dst+1; |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4575 dst = jcc(dst, CC_C, dst+2); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4576 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4577 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4578 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4579 *already_supervisor = dst - (already_supervisor+1); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4580 //save PC |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4581 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4582 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4583 dst = call(dst, opts->write_32_lowfirst); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4584 //save status register |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4585 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4586 dst = call(dst, (uint8_t *)get_sr); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4587 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4588 dst = call(dst, opts->write_16); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4589 //set supervisor bit |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4590 dst = or_irdisp8(dst, 0x20, CONTEXT, offsetof(m68k_context, status), SZ_B); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4591 //calculate vector address |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4592 dst = pop_r(dst, SCRATCH1); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4593 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4594 dst = call(dst, opts->read_32); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4595 dst = call(dst, opts->native_addr_and_sync); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4596 dst = cycles(dst, 18); |
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4597 dst = jmp_r(dst, SCRATCH1); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4598 |
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4599 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4600 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4601 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4602 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4603 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4604 memset(context, 0, sizeof(m68k_context)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4605 context->native_code_map = native_code_map; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4606 context->options = opts; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
4607 context->int_cycle = 0xFFFFFFFF; |
167
f6c7fea1ecf7
Initialize status register to proper value on startup
Mike Pavone <pavone@retrodev.com>
parents:
165
diff
changeset
|
4608 context->status = 0x27; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4609 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4610 |