Mercurial > repos > blastem
annotate m68k_core_x86.c @ 2299:a1c9edf44c7e
Fix a place I missed a problem from the SDL2 upgrade
author | Michael Pavone <pavone@retrodev.com> |
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date | Thu, 09 Mar 2023 22:59:29 -0800 |
parents | 3b5fef896475 |
children | 959a3e9aaac5 |
rev | line source |
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Added copyright notice to source files and added GPL license text in COPYING
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1 /* |
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2 Copyright 2013 Michael Pavone |
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Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_x86.h" |
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7 #include "m68k_core.h" |
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Initial stab at separating the generic parts of the 68K core from the host-cpu specific parts.
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8 #include "m68k_internal.h" |
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Tweaks to make blastem compatible with m68k-tester
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9 #include "68kinst.h" |
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Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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10 #include "mem.h" |
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Rename x86_backend.h and x86_backend.c to backend.h and backend.c respectively
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11 #include "backend.h" |
792
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Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
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12 #include "util.h" |
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13 #include <stdio.h> |
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14 #include <stddef.h> |
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15 #include <stdlib.h> |
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16 #include <string.h> |
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17 |
546
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Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
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18 enum { |
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19 FLAG_X, |
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20 FLAG_N, |
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21 FLAG_Z, |
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22 FLAG_V, |
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23 FLAG_C |
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24 }; |
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25 |
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26 void set_flag(m68k_options * opts, uint8_t val, uint8_t flag) |
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27 { |
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28 if (opts->flag_regs[flag] >= 0) { |
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29 mov_ir(&opts->gen.code, val, opts->flag_regs[flag], SZ_B); |
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30 } else { |
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31 int8_t offset = offsetof(m68k_context, flags) + flag; |
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32 if (offset) { |
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33 mov_irdisp(&opts->gen.code, val, opts->gen.context_reg, offset, SZ_B); |
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34 } else { |
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35 mov_irind(&opts->gen.code, val, opts->gen.context_reg, SZ_B); |
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36 } |
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37 } |
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38 } |
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39 |
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40 void set_flag_cond(m68k_options *opts, uint8_t cond, uint8_t flag) |
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41 { |
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42 if (opts->flag_regs[flag] >= 0) { |
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43 setcc_r(&opts->gen.code, cond, opts->flag_regs[flag]); |
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44 } else { |
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45 int8_t offset = offsetof(m68k_context, flags) + flag; |
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46 if (offset) { |
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47 setcc_rdisp(&opts->gen.code, cond, opts->gen.context_reg, offset); |
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48 } else { |
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49 setcc_rind(&opts->gen.code, cond, opts->gen.context_reg); |
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50 } |
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51 } |
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52 } |
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53 |
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54 void check_flag(m68k_options *opts, uint8_t flag) |
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55 { |
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56 if (opts->flag_regs[flag] >= 0) { |
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57 cmp_ir(&opts->gen.code, 0, opts->flag_regs[flag], SZ_B); |
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58 } else { |
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59 cmp_irdisp(&opts->gen.code, 0, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, SZ_B); |
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60 } |
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61 } |
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62 |
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63 void flag_to_reg(m68k_options *opts, uint8_t flag, uint8_t reg) |
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64 { |
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65 if (opts->flag_regs[flag] >= 0) { |
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66 mov_rr(&opts->gen.code, opts->flag_regs[flag], reg, SZ_B); |
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67 } else { |
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68 int8_t offset = offsetof(m68k_context, flags) + flag; |
90aca661542b
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69 if (offset) { |
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70 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offset, reg, SZ_B); |
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71 } else { |
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72 mov_rindr(&opts->gen.code, opts->gen.context_reg, reg, SZ_B); |
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73 } |
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
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74 } |
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75 } |
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76 |
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77 void reg_to_flag(m68k_options *opts, uint8_t reg, uint8_t flag) |
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78 { |
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79 if (opts->flag_regs[flag] >= 0) { |
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80 mov_rr(&opts->gen.code, reg, opts->flag_regs[flag], SZ_B); |
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81 } else { |
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82 int8_t offset = offsetof(m68k_context, flags) + flag; |
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83 if (offset) { |
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84 mov_rrdisp(&opts->gen.code, reg, opts->gen.context_reg, offset, SZ_B); |
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85 } else { |
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86 mov_rrind(&opts->gen.code, reg, opts->gen.context_reg, SZ_B); |
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87 } |
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88 } |
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89 } |
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90 |
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91 void flag_to_flag(m68k_options *opts, uint8_t flag1, uint8_t flag2) |
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92 { |
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93 code_info *code = &opts->gen.code; |
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94 if (opts->flag_regs[flag1] >= 0 && opts->flag_regs[flag2] >= 0) { |
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95 mov_rr(code, opts->flag_regs[flag1], opts->flag_regs[flag2], SZ_B); |
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96 } else if(opts->flag_regs[flag1] >= 0) { |
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97 mov_rrdisp(code, opts->flag_regs[flag1], opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B); |
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98 } else if (opts->flag_regs[flag2] >= 0) { |
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99 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag1, opts->flag_regs[flag2], SZ_B); |
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100 } else { |
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101 push_r(code, opts->gen.scratch1); |
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102 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag1, opts->gen.scratch1, SZ_B); |
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103 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B); |
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104 pop_r(code, opts->gen.scratch1); |
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105 } |
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106 } |
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107 |
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108 void update_flags(m68k_options *opts, uint32_t update_mask) |
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109 { |
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110 uint8_t native_flags[] = {0, CC_S, CC_Z, CC_O, CC_C}; |
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111 for (int8_t flag = FLAG_C; flag >= FLAG_X; --flag) |
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112 { |
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113 if (update_mask & X0 << (flag*3)) { |
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114 set_flag(opts, 0, flag); |
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115 } else if(update_mask & X1 << (flag*3)) { |
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116 set_flag(opts, 1, flag); |
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117 } else if(update_mask & X << (flag*3)) { |
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118 if (flag == FLAG_X) { |
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119 if (opts->flag_regs[FLAG_C] >= 0 || !(update_mask & (C0|C1|C))) { |
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120 flag_to_flag(opts, FLAG_C, FLAG_X); |
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121 } else if(update_mask & C0) { |
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122 set_flag(opts, 0, flag); |
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123 } else if(update_mask & C1) { |
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124 set_flag(opts, 1, flag); |
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125 } else { |
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126 set_flag_cond(opts, CC_C, flag); |
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127 } |
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128 } else { |
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129 set_flag_cond(opts, native_flags[flag], flag); |
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130 } |
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131 } |
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132 } |
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133 } |
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134 |
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135 void flag_to_carry(m68k_options * opts, uint8_t flag) |
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136 { |
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137 if (opts->flag_regs[flag] >= 0) { |
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138 bt_ir(&opts->gen.code, 0, opts->flag_regs[flag], SZ_B); |
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139 } else { |
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140 bt_irdisp(&opts->gen.code, 0, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, SZ_B); |
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141 } |
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142 } |
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143 |
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144 void or_flag_to_reg(m68k_options *opts, uint8_t flag, uint8_t reg) |
546
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145 { |
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146 if (opts->flag_regs[flag] >= 0) { |
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147 or_rr(&opts->gen.code, opts->flag_regs[flag], reg, SZ_B); |
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148 } else { |
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149 or_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, reg, SZ_B); |
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150 } |
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151 } |
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152 |
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153 void xor_flag_to_reg(m68k_options *opts, uint8_t flag, uint8_t reg) |
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154 { |
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155 if (opts->flag_regs[flag] >= 0) { |
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156 xor_rr(&opts->gen.code, opts->flag_regs[flag], reg, SZ_B); |
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157 } else { |
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158 xor_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, reg, SZ_B); |
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159 } |
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160 } |
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161 |
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162 void xor_flag(m68k_options *opts, uint8_t val, uint8_t flag) |
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163 { |
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164 if (opts->flag_regs[flag] >= 0) { |
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165 xor_ir(&opts->gen.code, val, opts->flag_regs[flag], SZ_B); |
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166 } else { |
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167 xor_irdisp(&opts->gen.code, val, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, SZ_B); |
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168 } |
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169 } |
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170 |
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171 void cmp_flags(m68k_options *opts, uint8_t flag1, uint8_t flag2) |
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172 { |
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173 code_info *code = &opts->gen.code; |
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174 if (opts->flag_regs[flag1] >= 0 && opts->flag_regs[flag2] >= 0) { |
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175 cmp_rr(code, opts->flag_regs[flag1], opts->flag_regs[flag2], SZ_B); |
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176 } else if(opts->flag_regs[flag1] >= 0 || opts->flag_regs[flag2] >= 0) { |
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177 if (opts->flag_regs[flag2] >= 0) { |
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178 uint8_t tmp = flag1; |
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179 flag1 = flag2; |
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180 flag2 = tmp; |
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181 } |
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182 cmp_rrdisp(code, opts->flag_regs[flag1], opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B); |
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183 } else { |
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184 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag1, opts->gen.scratch1, SZ_B); |
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185 cmp_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B); |
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186 } |
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187 } |
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188 |
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189 void areg_to_native(m68k_options *opts, uint8_t reg, uint8_t native_reg) |
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190 { |
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191 if (opts->aregs[reg] >= 0) { |
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192 mov_rr(&opts->gen.code, opts->aregs[reg], native_reg, SZ_D); |
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193 } else { |
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194 mov_rdispr(&opts->gen.code, opts->gen.context_reg, areg_offset(reg), native_reg, SZ_D); |
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195 } |
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196 } |
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197 |
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198 void dreg_to_native(m68k_options *opts, uint8_t reg, uint8_t native_reg) |
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199 { |
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200 if (opts->dregs[reg] >= 0) { |
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201 mov_rr(&opts->gen.code, opts->dregs[reg], native_reg, SZ_D); |
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202 } else { |
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203 mov_rdispr(&opts->gen.code, opts->gen.context_reg, dreg_offset(reg), native_reg, SZ_D); |
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204 } |
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205 } |
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206 |
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207 void areg_to_native_sx(m68k_options *opts, uint8_t reg, uint8_t native_reg) |
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208 { |
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209 if (opts->aregs[reg] >= 0) { |
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210 movsx_rr(&opts->gen.code, opts->aregs[reg], native_reg, SZ_W, SZ_D); |
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211 } else { |
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212 movsx_rdispr(&opts->gen.code, opts->gen.context_reg, areg_offset(reg), native_reg, SZ_W, SZ_D); |
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213 } |
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214 } |
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215 |
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216 void dreg_to_native_sx(m68k_options *opts, uint8_t reg, uint8_t native_reg) |
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217 { |
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218 if (opts->dregs[reg] >= 0) { |
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219 movsx_rr(&opts->gen.code, opts->dregs[reg], native_reg, SZ_W, SZ_D); |
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220 } else { |
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221 movsx_rdispr(&opts->gen.code, opts->gen.context_reg, dreg_offset(reg), native_reg, SZ_W, SZ_D); |
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222 } |
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223 } |
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224 |
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225 void native_to_areg(m68k_options *opts, uint8_t native_reg, uint8_t reg) |
682 | 226 { |
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227 if (opts->aregs[reg] >= 0) { |
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228 mov_rr(&opts->gen.code, native_reg, opts->aregs[reg], SZ_D); |
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229 } else { |
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230 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, areg_offset(reg), SZ_D); |
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231 } |
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232 } |
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233 |
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234 void native_to_dreg(m68k_options *opts, uint8_t native_reg, uint8_t reg) |
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235 { |
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236 if (opts->dregs[reg] >= 0) { |
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237 mov_rr(&opts->gen.code, native_reg, opts->dregs[reg], SZ_D); |
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238 } else { |
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239 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, dreg_offset(reg), SZ_D); |
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240 } |
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241 } |
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242 |
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243 void ldi_areg(m68k_options *opts, int32_t value, uint8_t reg) |
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244 { |
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245 if (opts->aregs[reg] >= 0) { |
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246 mov_ir(&opts->gen.code, value, opts->aregs[reg], SZ_D); |
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247 } else { |
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248 mov_irdisp(&opts->gen.code, value, opts->gen.context_reg, areg_offset(reg), SZ_D); |
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249 } |
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250 } |
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251 |
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252 void ldi_native(m68k_options *opts, int32_t value, uint8_t reg) |
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253 { |
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254 mov_ir(&opts->gen.code, value, reg, SZ_D); |
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255 } |
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256 |
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257 void addi_native(m68k_options *opts, int32_t value, uint8_t reg) |
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258 { |
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259 add_ir(&opts->gen.code, value, reg, SZ_D); |
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261 |
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262 void subi_native(m68k_options *opts, int32_t value, uint8_t reg) |
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263 { |
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264 sub_ir(&opts->gen.code, value, reg, SZ_D); |
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265 } |
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266 |
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267 void push_native(m68k_options *opts, uint8_t reg) |
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268 { |
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269 push_r(&opts->gen.code, reg); |
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270 } |
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271 |
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272 void pop_native(m68k_options *opts, uint8_t reg) |
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273 { |
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274 pop_r(&opts->gen.code, reg); |
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275 } |
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276 |
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277 void sign_extend16_native(m68k_options *opts, uint8_t reg) |
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278 { |
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279 movsx_rr(&opts->gen.code, reg, reg, SZ_W, SZ_D); |
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280 } |
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281 |
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282 void addi_areg(m68k_options *opts, int32_t val, uint8_t reg) |
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283 { |
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284 if (opts->aregs[reg] >= 0) { |
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285 add_ir(&opts->gen.code, val, opts->aregs[reg], SZ_D); |
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286 } else { |
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287 add_irdisp(&opts->gen.code, val, opts->gen.context_reg, areg_offset(reg), SZ_D); |
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288 } |
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289 } |
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290 |
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291 void subi_areg(m68k_options *opts, int32_t val, uint8_t reg) |
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292 { |
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293 if (opts->aregs[reg] >= 0) { |
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294 sub_ir(&opts->gen.code, val, opts->aregs[reg], SZ_D); |
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295 } else { |
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296 sub_irdisp(&opts->gen.code, val, opts->gen.context_reg, areg_offset(reg), SZ_D); |
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297 } |
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298 } |
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299 |
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300 void add_areg_native(m68k_options *opts, uint8_t reg, uint8_t native_reg) |
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301 { |
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302 if (opts->aregs[reg] >= 0) { |
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303 add_rr(&opts->gen.code, opts->aregs[reg], native_reg, SZ_D); |
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304 } else { |
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305 add_rdispr(&opts->gen.code, opts->gen.context_reg, areg_offset(reg), native_reg, SZ_D); |
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306 } |
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307 } |
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308 |
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309 void add_dreg_native(m68k_options *opts, uint8_t reg, uint8_t native_reg) |
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310 { |
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311 if (opts->dregs[reg] >= 0) { |
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312 add_rr(&opts->gen.code, opts->dregs[reg], native_reg, SZ_D); |
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313 } else { |
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314 add_rdispr(&opts->gen.code, opts->gen.context_reg, dreg_offset(reg), native_reg, SZ_D); |
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315 } |
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316 } |
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317 |
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318 void calc_areg_displace(m68k_options *opts, m68k_op_info *op, uint8_t native_reg) |
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319 { |
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320 areg_to_native(opts, op->params.regs.pri, native_reg); |
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321 add_ir(&opts->gen.code, op->params.regs.displacement & 0x8000 ? op->params.regs.displacement | 0xFFFF0000 : op->params.regs.displacement, native_reg, SZ_D); |
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322 } |
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323 |
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324 void calc_index_disp8(m68k_options *opts, m68k_op_info *op, uint8_t native_reg) |
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325 { |
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326 uint8_t sec_reg = (op->params.regs.sec >> 1) & 0x7; |
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327 if (op->params.regs.sec & 1) { |
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328 if (op->params.regs.sec & 0x10) { |
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329 add_areg_native(opts, sec_reg, native_reg); |
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330 } else { |
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|
331 add_dreg_native(opts, sec_reg, native_reg); |
686
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Fix indentation that presumably got messed up in a merge
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parents:
682
diff
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|
332 } |
8cb61671777b
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parents:
682
diff
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|
333 } else { |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
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|
334 uint8_t other_reg = native_reg == opts->gen.scratch1 ? opts->gen.scratch2 : opts->gen.scratch1; |
1594525e2157
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parents:
571
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|
335 if (op->params.regs.sec & 0x10) { |
1594525e2157
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parents:
571
diff
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|
336 areg_to_native_sx(opts, sec_reg, other_reg); |
686
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parents:
682
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|
337 } else { |
574
1594525e2157
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parents:
571
diff
changeset
|
338 dreg_to_native_sx(opts, sec_reg, other_reg); |
686
8cb61671777b
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parents:
682
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|
339 } |
574
1594525e2157
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parents:
571
diff
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|
340 add_rr(&opts->gen.code, other_reg, native_reg, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
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parents:
682
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|
341 } |
574
1594525e2157
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parents:
571
diff
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|
342 if (op->params.regs.displacement) { |
1594525e2157
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parents:
571
diff
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|
343 add_ir(&opts->gen.code, op->params.regs.displacement, native_reg, SZ_D); |
686
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parents:
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|
344 } |
8cb61671777b
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parents:
682
diff
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|
345 } |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
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|
346 |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
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parents:
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diff
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|
347 void calc_areg_index_disp8(m68k_options *opts, m68k_op_info *op, uint8_t native_reg) |
686
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parents:
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348 { |
574
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|
349 areg_to_native(opts, op->params.regs.pri, native_reg); |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
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|
350 calc_index_disp8(opts, op, native_reg); |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
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parents:
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351 } |
1594525e2157
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parents:
571
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352 |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
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|
353 void m68k_check_cycles_int_latch(m68k_options *opts) |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
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354 { |
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parents:
1332
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|
355 code_info *code = &opts->gen.code; |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
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1332
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|
356 uint8_t cc; |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
357 if (opts->gen.limit < 0) { |
df6af7187b36
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Michael Pavone <pavone@retrodev.com>
parents:
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|
358 cmp_ir(code, 1, opts->gen.cycles, SZ_D); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
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|
359 cc = CC_NS; |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
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|
360 } else { |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
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1332
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|
361 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
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1332
diff
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|
362 cc = CC_A; |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
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1332
diff
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|
363 } |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
364 code_ptr jmp_off; |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
365 ALLOC_CODE_RETRY_POINT |
2269
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Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
366 jmp_off = code->cur+1; |
1363
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Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
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|
367 jcc(code, cc, jmp_off+1); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
368 call(code, opts->handle_int_latch); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
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|
369 CHECK_BRANCH_DEST(jmp_off) |
1363
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Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
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|
370 } |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
371 |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
372 uint8_t translate_m68k_op(m68kinst * inst, host_ea * ea, m68k_options * opts, uint8_t dst) |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
373 { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
374 code_info *code = &opts->gen.code; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
375 m68k_op_info *op = dst ? &inst->dst : &inst->src; |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
376 int8_t reg = native_reg(op, opts); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
377 uint8_t sec_reg; |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
378 uint8_t ret = 1; |
682 | 379 int32_t dec_amount, inc_amount; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 if (reg >= 0) { |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
381 ea->mode = MODE_REG_DIRECT; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
382 if (!dst && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
383 movsx_rr(code, reg, opts->gen.scratch1, SZ_W, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
384 ea->base = opts->gen.scratch1; |
1430
747c779fc137
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
Michael Pavone <pavone@retrodev.com>
parents:
1375
diff
changeset
|
385 #ifdef X86_32 |
747c779fc137
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
Michael Pavone <pavone@retrodev.com>
parents:
1375
diff
changeset
|
386 } else if (reg > RBX && inst->extra.size == OPSIZE_BYTE) { |
747c779fc137
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
Michael Pavone <pavone@retrodev.com>
parents:
1375
diff
changeset
|
387 mov_rr(code, reg, opts->gen.scratch1, SZ_D); |
747c779fc137
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
Michael Pavone <pavone@retrodev.com>
parents:
1375
diff
changeset
|
388 ea->base = opts->gen.scratch1; |
747c779fc137
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
Michael Pavone <pavone@retrodev.com>
parents:
1375
diff
changeset
|
389 #endif |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
390 } else { |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
391 ea->base = reg; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
392 } |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
393 return 0; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
395 switch (op->addr_mode) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
396 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
397 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
398 case MODE_AREG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
399 //We only get one memory parameter, so if the dst operand is a register in memory, |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
400 //we need to copy this to a temp register first if we're translating the src operand |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
401 if (dst || native_reg(&(inst->dst), opts) >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
402 || inst->op == M68K_EXG) { |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
403 |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
404 ea->mode = MODE_REG_DISPLACE8; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
405 ea->base = opts->gen.context_reg; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
406 ea->disp = reg_offset(op); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
407 } else { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
408 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
409 movsx_rdispr(code, opts->gen.context_reg, reg_offset(op), opts->gen.scratch1, SZ_W, SZ_D); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
410 } else { |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
411 mov_rdispr(code, opts->gen.context_reg, reg_offset(op), opts->gen.scratch1, inst->extra.size); |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
412 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
413 ea->mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
414 ea->base = opts->gen.scratch1; |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
415 //we're explicitly handling the areg dest here, so we exit immediately |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
416 return 0; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
417 } |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
418 ret = 0; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
419 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
420 case MODE_AREG_PREDEC: |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
421 if (dst && inst->src.addr_mode == MODE_AREG_PREDEC) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
422 push_r(code, opts->gen.scratch1); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
423 } |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
424 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (op->params.regs.pri == 7 ? 2 :1)); |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
425 if (!dst || ( |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
426 inst->op != M68K_MOVE && inst->op != M68K_MOVEM |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
427 && inst->op != M68K_SUBX && inst->op != M68K_ADDX |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
428 && inst->op != M68K_ABCD && inst->op != M68K_SBCD |
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
429 )) { |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
430 cycles(&opts->gen, PREDEC_PENALTY); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
431 } |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
432 subi_areg(opts, dec_amount, op->params.regs.pri); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
433 case MODE_AREG_INDIRECT: |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
434 case MODE_AREG_POSTINC: |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
435 areg_to_native(opts, op->params.regs.pri, opts->gen.scratch1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
436 m68k_read_size(opts, inst->extra.size); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
437 |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
438 if (dst) { |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
439 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
440 //restore src operand to opts->gen.scratch2 |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
441 pop_r(code, opts->gen.scratch2); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
442 } else { |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
443 //save reg value in opts->gen.scratch2 so we can use it to save the result in memory later |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
444 areg_to_native(opts, op->params.regs.pri, opts->gen.scratch2); |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
445 } |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
446 } |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
447 |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
448 if (op->addr_mode == MODE_AREG_POSTINC) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
449 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (op->params.regs.pri == 7 ? 2 : 1)); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
450 addi_areg(opts, inc_amount, op->params.regs.pri); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
451 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
452 ea->mode = MODE_REG_DIRECT; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
453 ea->base = (!dst && inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? opts->gen.scratch2 : opts->gen.scratch1; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
454 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
455 case MODE_AREG_DISPLACE: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
456 cycles(&opts->gen, BUS); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
457 calc_areg_displace(opts, op, opts->gen.scratch1); |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
458 if (dst) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
459 push_r(code, opts->gen.scratch1); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
460 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
461 m68k_read_size(opts, inst->extra.size); |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
462 if (dst) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
463 pop_r(code, opts->gen.scratch2); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
464 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
465 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
466 ea->mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
467 ea->base = opts->gen.scratch1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
468 break; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
469 case MODE_AREG_INDEX_DISP8: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
470 cycles(&opts->gen, 6); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
471 calc_areg_index_disp8(opts, op, opts->gen.scratch1); |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
472 if (dst) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
473 push_r(code, opts->gen.scratch1); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
474 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
475 m68k_read_size(opts, inst->extra.size); |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
476 if (dst) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
477 pop_r(code, opts->gen.scratch2); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
478 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
479 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
480 ea->mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
481 ea->base = opts->gen.scratch1; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
482 break; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
483 case MODE_PC_DISPLACE: |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
484 cycles(&opts->gen, BUS); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
485 mov_ir(code, op->params.regs.displacement + inst->address+2, opts->gen.scratch1, SZ_D); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
486 if (dst) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
487 push_r(code, opts->gen.scratch1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
488 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
489 m68k_read_size(opts, inst->extra.size); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
490 if (dst) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
491 pop_r(code, opts->gen.scratch2); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
492 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
493 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
494 ea->mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
495 ea->base = opts->gen.scratch1; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
496 break; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
497 case MODE_PC_INDEX_DISP8: |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
498 cycles(&opts->gen, 6); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
499 mov_ir(code, inst->address+2, opts->gen.scratch1, SZ_D); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
500 calc_index_disp8(opts, op, opts->gen.scratch1); |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
501 if (dst) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
502 push_r(code, opts->gen.scratch1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
503 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
504 m68k_read_size(opts, inst->extra.size); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
505 if (dst) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
506 pop_r(code, opts->gen.scratch2); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
507 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
508 |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
509 ea->mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
510 ea->base = opts->gen.scratch1; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
511 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
512 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
513 case MODE_ABSOLUTE_SHORT: |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
514 cycles(&opts->gen, op->addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
515 mov_ir(code, op->params.immed, opts->gen.scratch1, SZ_D); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
516 if (dst) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
517 push_r(code, opts->gen.scratch1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
518 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
519 m68k_read_size(opts, inst->extra.size); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
520 if (dst) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
521 pop_r(code, opts->gen.scratch2); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
522 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
523 |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
524 ea->mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
525 ea->base = opts->gen.scratch1; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
526 break; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
527 case MODE_IMMEDIATE: |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
528 case MODE_IMMEDIATE_WORD: |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
529 if (inst->variant != VAR_QUICK) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
530 cycles(&opts->gen, (inst->extra.size == OPSIZE_LONG && op->addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
531 } |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
532 ea->mode = MODE_IMMED; |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
533 ea->disp = op->params.immed; |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
534 //sign extend value when the destination is an address register |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
535 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
536 ea->disp |= 0xFFFF0000; |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
537 } |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
538 return inst->variant != VAR_QUICK; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
539 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
540 m68k_disasm(inst, disasm_buf); |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
541 fatal_error("%X: %s\naddress mode %d not implemented (%s)\n", inst->address, disasm_buf, op->addr_mode, dst ? "dst" : "src"); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
542 } |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
543 if (!dst && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
544 if (ea->mode == MODE_REG_DIRECT) { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
545 movsx_rr(code, ea->base, opts->gen.scratch1, SZ_W, SZ_D); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
546 } else { |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
547 movsx_rdispr(code, ea->base, ea->disp, opts->gen.scratch1, SZ_W, SZ_D); |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
548 ea->mode = MODE_REG_DIRECT; |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
549 } |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
550 ea->base = opts->gen.scratch1; |
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
551 } |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
552 return ret; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
553 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
554 |
687
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
555 void check_user_mode_swap_ssp_usp(m68k_options *opts) |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
556 { |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
557 code_info * code = &opts->gen.code; |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
558 //Check if we've switched to user mode and swap stack pointers if needed |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
559 bt_irdisp(code, 5, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
560 code_ptr end_off = code->cur + 1; |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
561 jcc(code, CC_C, code->cur + 2); |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
562 swap_ssp_usp(opts); |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
563 *end_off = code->cur - (end_off + 1); |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
564 } |
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
565 |
569
9b7fcf748be0
Rename x86_68k_options and m68k_to_x86.h to m68k_options and m68k_core.h respectively
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
566 void translate_m68k_move(m68k_options * opts, m68kinst * inst) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
567 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
568 code_info *code = &opts->gen.code; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
569 int8_t reg, flags_reg, sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
570 uint8_t dir = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
571 int32_t offset; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
572 int32_t inc_amount, dec_amount; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
573 host_ea src; |
1370
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
574 uint8_t needs_int_latch = translate_m68k_op(inst, &src, opts, 0); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
575 reg = native_reg(&(inst->dst), opts); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
576 |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
577 if (inst->dst.addr_mode != MODE_AREG) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
578 if (src.mode == MODE_REG_DIRECT) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
579 flags_reg = src.base; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
580 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
581 if (reg >= 0) { |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
582 flags_reg = reg; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
583 } else { |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
584 if(src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
585 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
586 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
587 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
588 } |
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
589 src.mode = MODE_REG_DIRECT; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
590 flags_reg = src.base = opts->gen.scratch1; |
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
591 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
592 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
593 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
594 uint8_t size = inst->extra.size; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
595 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
596 { |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
597 case MODE_AREG: |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
598 size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
599 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
600 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
601 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
602 mov_rr(code, src.base, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
603 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
604 mov_rdispr(code, src.base, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
605 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
606 mov_ir(code, src.disp, reg, size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
607 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
608 } else if(src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
609 mov_rrdisp(code, src.base, opts->gen.context_reg, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
610 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
611 mov_irdisp(code, src.disp, opts->gen.context_reg, reg_offset(&(inst->dst)), size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
612 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
613 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
614 case MODE_AREG_PREDEC: |
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
615 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
616 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
617 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
618 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
619 if (src.base != opts->gen.scratch1) { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
620 mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
621 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
622 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
623 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
624 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
625 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
626 } |
610
314373222b1a
Decrement address register after fetching source in move with -(ax) dest to avoid bug when src is the dst addres reg
Michael Pavone <pavone@retrodev.com>
parents:
605
diff
changeset
|
627 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
314373222b1a
Decrement address register after fetching source in move with -(ax) dest to avoid bug when src is the dst addres reg
Michael Pavone <pavone@retrodev.com>
parents:
605
diff
changeset
|
628 subi_areg(opts, dec_amount, inst->dst.params.regs.pri); |
314373222b1a
Decrement address register after fetching source in move with -(ax) dest to avoid bug when src is the dst addres reg
Michael Pavone <pavone@retrodev.com>
parents:
605
diff
changeset
|
629 } |
314373222b1a
Decrement address register after fetching source in move with -(ax) dest to avoid bug when src is the dst addres reg
Michael Pavone <pavone@retrodev.com>
parents:
605
diff
changeset
|
630 areg_to_native(opts, inst->dst.params.regs.pri, opts->gen.scratch2); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
631 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
632 case MODE_AREG_DISPLACE: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
633 cycles(&opts->gen, BUS); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
634 calc_areg_displace(opts, &inst->dst, opts->gen.scratch2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
635 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
636 if (src.base != opts->gen.scratch1) { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
637 mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
638 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
639 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
640 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
641 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
642 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
643 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
644 break; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
645 case MODE_AREG_INDEX_DISP8: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
646 cycles(&opts->gen, 6);//TODO: Check to make sure this is correct |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
647 //calc_areg_index_disp8 will clober scratch1 when a 16-bit index is used |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
648 if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) { |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
649 push_r(code, opts->gen.scratch1); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
650 } |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
651 calc_areg_index_disp8(opts, &inst->dst, opts->gen.scratch2); |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
652 if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) { |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
653 pop_r(code, opts->gen.scratch1); |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
654 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
655 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
656 if (src.base != opts->gen.scratch1) { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
657 mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
658 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
659 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
660 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
661 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
662 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
663 } |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
664 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
665 case MODE_PC_DISPLACE: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
666 cycles(&opts->gen, BUS); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
667 mov_ir(code, inst->dst.params.regs.displacement + inst->address+2, opts->gen.scratch2, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
668 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
669 if (src.base != opts->gen.scratch1) { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
670 mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
671 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
672 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
673 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
674 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
675 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
676 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
677 break; |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
678 case MODE_PC_INDEX_DISP8: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
679 cycles(&opts->gen, 6);//TODO: Check to make sure this is correct |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
680 mov_ir(code, inst->address, opts->gen.scratch2, SZ_D); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
681 if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) { |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
682 push_r(code, opts->gen.scratch1); |
689
858e31f977ae
A couple more indentation fixes
Michael Pavone <pavone@retrodev.com>
parents:
688
diff
changeset
|
683 } |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
684 calc_index_disp8(opts, &inst->dst, opts->gen.scratch2); |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
685 if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) { |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
686 pop_r(code, opts->gen.scratch1); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
687 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
688 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
689 if (src.base != opts->gen.scratch1) { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
690 mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
691 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
692 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
693 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
694 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
695 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
696 } |
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
697 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
698 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
699 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
700 if (src.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
701 if (src.base != opts->gen.scratch1) { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
702 mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
703 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
704 } else if (src.mode == MODE_REG_DISPLACE8) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
705 mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
706 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
707 mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
708 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
709 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
710 cycles(&opts->gen, BUS*2); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
711 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
712 cycles(&opts->gen, BUS); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
713 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
714 mov_ir(code, inst->dst.params.immed, opts->gen.scratch2, SZ_D); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
715 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
716 default: |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
717 m68k_disasm(inst, disasm_buf); |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
718 fatal_error("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
720 |
576
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
721 if (inst->dst.addr_mode != MODE_AREG) { |
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
722 cmp_ir(code, 0, flags_reg, inst->extra.size); |
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
723 update_flags(opts, N|Z|V0|C0); |
689
858e31f977ae
A couple more indentation fixes
Michael Pavone <pavone@retrodev.com>
parents:
688
diff
changeset
|
724 } |
576
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
725 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
1370
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
726 if (inst->extra.size == OPSIZE_LONG) { |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
727 //We want the int latch to occur between the two writes, |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
728 //but that's a pain to do without refactoring how 32-bit writes work |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
729 //workaround it by temporarily increasing the cycle count before the check |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
730 cycles(&opts->gen, BUS); |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
731 } |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
732 m68k_check_cycles_int_latch(opts); |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
733 if (inst->extra.size == OPSIZE_LONG) { |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
734 //and then backing out that extra increment here before the write happens |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
735 cycles(&opts->gen, -BUS); |
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
736 } |
979
771875b5f519
Fix order of writes for move.l with a predec destination
Michael Pavone <pavone@retrodev.com>
parents:
976
diff
changeset
|
737 m68k_write_size(opts, inst->extra.size, inst->dst.addr_mode == MODE_AREG_PREDEC); |
576
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
738 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
739 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
740 addi_areg(opts, inc_amount, inst->dst.params.regs.pri); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
741 } |
1375
b68732dcbf00
Avoid splitting m68k_check_cycles_int_latch code across memory chunks since it expects a byte-sized jump offset. Avoid an unnecessary m68k_check_cycles_int_latch for register to register moves
Michael Pavone <pavone@retrodev.com>
parents:
1370
diff
changeset
|
742 } else if (needs_int_latch) { |
1370
eaca4443e831
Fix interrupt latency for move.l with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1363
diff
changeset
|
743 m68k_check_cycles_int_latch(opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
744 } |
576
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
745 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
746 //add cycles for prefetch |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
747 cycles(&opts->gen, BUS); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
748 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
749 |
569
9b7fcf748be0
Rename x86_68k_options and m68k_to_x86.h to m68k_options and m68k_core.h respectively
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
750 void translate_m68k_ext(m68k_options * opts, m68kinst * inst) |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
751 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
752 code_info *code = &opts->gen.code; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
753 host_ea dst_op; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
754 uint8_t dst_size = inst->extra.size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
755 inst->extra.size--; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
756 translate_m68k_op(inst, &dst_op, opts, 1); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
757 if (dst_op.mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
758 movsx_rr(code, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
759 cmp_ir(code, 0, dst_op.base, dst_size); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
760 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
761 movsx_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, inst->extra.size, dst_size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
762 cmp_ir(code, 0, opts->gen.scratch1, dst_size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
763 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, dst_size); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
764 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
765 inst->extra.size = dst_size; |
576
a6f2db4df70d
Small refactor to flag handling in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
574
diff
changeset
|
766 update_flags(opts, N|V0|C0|Z); |
1584
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
767 cycles(&opts->gen, BUS); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
768 //M68K EXT only operates on registers so no need for a call to save result here |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
769 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
770 |
569
9b7fcf748be0
Rename x86_68k_options and m68k_to_x86.h to m68k_options and m68k_core.h respectively
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
771 uint8_t m68k_eval_cond(m68k_options * opts, uint8_t cc) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
772 { |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
773 uint8_t cond = CC_NZ; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
774 switch (cc) |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
775 { |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
776 case COND_HIGH: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
777 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
778 case COND_LOW_SAME: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
779 flag_to_reg(opts, FLAG_Z, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
780 or_flag_to_reg(opts, FLAG_C, opts->gen.scratch1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
781 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
782 case COND_CARRY_CLR: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
783 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
784 case COND_CARRY_SET: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
785 check_flag(opts, FLAG_C); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
786 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
787 case COND_NOT_EQ: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
788 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
789 case COND_EQ: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
790 check_flag(opts, FLAG_Z); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
791 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
792 case COND_OVERF_CLR: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
793 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
794 case COND_OVERF_SET: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
795 check_flag(opts, FLAG_V); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
796 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
797 case COND_PLUS: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
798 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
799 case COND_MINUS: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
800 check_flag(opts, FLAG_N); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
801 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
802 case COND_GREATER_EQ: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
803 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
804 case COND_LESS: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
805 cmp_flags(opts, FLAG_N, FLAG_V); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
806 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
807 case COND_GREATER: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
808 cond = CC_Z; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
809 case COND_LESS_EQ: |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
810 flag_to_reg(opts, FLAG_V, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
811 xor_flag_to_reg(opts, FLAG_N, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
812 or_flag_to_reg(opts, FLAG_Z, opts->gen.scratch1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
813 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
814 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
815 return cond; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
816 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
817 |
569
9b7fcf748be0
Rename x86_68k_options and m68k_to_x86.h to m68k_options and m68k_core.h respectively
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
818 void translate_m68k_bcc(m68k_options * opts, m68kinst * inst) |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
819 { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
820 code_info *code = &opts->gen.code; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
821 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
822 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
823 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
824 if (inst->extra.cond == COND_TRUE) { |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
825 cycles(&opts->gen, 10); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
826 jump_m68k_abs(opts, after + disp); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
827 } else { |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
828 uint8_t cond = m68k_eval_cond(opts, inst->extra.cond); |
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
829 code_ptr do_branch = code->cur + 1; |
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
830 jcc(code, cond, do_branch); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
831 |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
832 cycles(&opts->gen, inst->variant == VAR_BYTE ? 8 : 12); |
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
833 code_ptr done = code->cur + 1; |
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
834 jmp(code, done); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
835 |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
836 *do_branch = code->cur - (do_branch + 1); |
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
837 cycles(&opts->gen, 10); |
726
7367b14ac01c
Don't attempt to translate or map code at odd addresses. This fixes a bug that shows up when playing College Footbal USA 96
Michael Pavone <pavone@retrodev.com>
parents:
698
diff
changeset
|
838 code_ptr dest_addr = get_native_address(opts, after + disp); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
839 if (!dest_addr) { |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
840 opts->gen.deferred = defer_address(opts->gen.deferred, after + disp, code->cur + 1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
841 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
842 dest_addr = code->cur + 256; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
843 } |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
844 jmp(code, dest_addr); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
845 |
1332
87bbc4bec958
Fix timing for branch not taken case in the M68K BCC intruction
Michael Pavone <pavone@retrodev.com>
parents:
1329
diff
changeset
|
846 *done = code->cur - (done + 1); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
847 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
848 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
849 |
569
9b7fcf748be0
Rename x86_68k_options and m68k_to_x86.h to m68k_options and m68k_core.h respectively
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
850 void translate_m68k_scc(m68k_options * opts, m68kinst * inst) |
112 | 851 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
852 code_info *code = &opts->gen.code; |
112 | 853 uint8_t cond = inst->extra.cond; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
854 host_ea dst_op; |
112 | 855 inst->extra.size = OPSIZE_BYTE; |
571
c90fc522e7e3
Refactor translat_m68k_src and translate_m68k_dst into a single function
Michael Pavone <pavone@retrodev.com>
parents:
570
diff
changeset
|
856 translate_m68k_op(inst, &dst_op, opts, 1); |
112 | 857 if (cond == COND_TRUE || cond == COND_FALSE) { |
2224
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
858 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && cond == COND_TRUE) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
859 cycles(&opts->gen, 6); |
112 | 860 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
861 cycles(&opts->gen, BUS); |
112 | 862 } |
863 if (dst_op.mode == MODE_REG_DIRECT) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
864 mov_ir(code, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B); |
112 | 865 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
866 mov_irdisp(code, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 867 } |
868 } else { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
869 uint8_t cc = m68k_eval_cond(opts, cond); |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
870 code_ptr true_off; |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
871 ALLOC_CODE_RETRY_POINT |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
872 true_off = code->cur + 1; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
873 jcc(code, cc, code->cur+2); |
8e395210f50f
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874 cycles(&opts->gen, BUS); |
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875 if (dst_op.mode == MODE_REG_DIRECT) { |
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876 mov_ir(code, 0, dst_op.base, SZ_B); |
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877 } else { |
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878 mov_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
112 | 879 } |
567
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880 code_ptr end_off = code->cur+1; |
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881 jmp(code, code->cur+2); |
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882 CHECK_BRANCH_DEST(true_off); |
1989
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Fix cycle timing of a number of 68K instructions
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883 cycles(&opts->gen, inst->dst.addr_mode == MODE_REG ? 6 : 4); |
179
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Fix scc to set reg to 0xFF rather than 1 when the condition is true
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884 if (dst_op.mode == MODE_REG_DIRECT) { |
567
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885 mov_ir(code, 0xFF, dst_op.base, SZ_B); |
112 | 886 } else { |
567
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887 mov_irdisp(code, 0xFF, dst_op.base, dst_op.disp, SZ_B); |
112 | 888 } |
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889 CHECK_BRANCH_DEST(end_off); |
112 | 890 } |
567
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891 m68k_save_result(inst, opts); |
112 | 892 } |
893 | |
569
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894 void translate_m68k_dbcc(m68k_options * opts, m68kinst * inst) |
46
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895 { |
567
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896 code_info *code = &opts->gen.code; |
46
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897 //best case duration |
567
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898 cycles(&opts->gen, 10); |
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
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899 code_ptr skip_loc = NULL; |
46
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900 //TODO: Check if COND_TRUE technically valid here even though |
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901 //it's basically a slow NOP |
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902 ALLOC_CODE_RETRY_VAR; |
46
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903 if (inst->extra.cond != COND_FALSE) { |
567
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904 uint8_t cond = m68k_eval_cond(opts, inst->extra.cond); |
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905 ALLOC_CODE_RETRY_POINT_NO_VAR |
567
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906 skip_loc = code->cur + 1; |
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907 jcc(code, cond, code->cur + 2); |
46
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908 } |
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909 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
567
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910 sub_ir(code, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
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911 cmp_ir(code, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
46
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912 } else { |
567
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913 sub_irdisp(code, 1, opts->gen.context_reg, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
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914 cmp_irdisp(code, -1, opts->gen.context_reg, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
46
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915 } |
567
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916 code_ptr loop_end_loc = code->cur + 1; |
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917 jcc(code, CC_Z, code->cur + 2); |
46
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918 uint32_t after = inst->address + 2; |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
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|
919 jump_m68k_abs(opts, after + inst->src.params.immed); |
567
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920 *loop_end_loc = code->cur - (loop_end_loc+1); |
46
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921 if (skip_loc) { |
567
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922 cycles(&opts->gen, 2); |
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923 CHECK_BRANCH_DEST(skip_loc); |
567
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924 cycles(&opts->gen, 2); |
46
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925 } else { |
567
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926 cycles(&opts->gen, 4); |
46
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927 } |
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928 } |
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929 |
569
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|
930 void translate_m68k_movep(m68k_options * opts, m68kinst * inst) |
172 | 931 { |
567
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932 code_info *code = &opts->gen.code; |
172 | 933 int8_t reg; |
567
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|
934 cycles(&opts->gen, BUS*2); |
172 | 935 if (inst->src.addr_mode == MODE_REG) { |
574
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More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
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936 calc_areg_displace(opts, &inst->dst, opts->gen.scratch2); |
172 | 937 reg = native_reg(&(inst->src), opts); |
938 if (inst->extra.size == OPSIZE_LONG) { | |
939 if (reg >= 0) { | |
567
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940 mov_rr(code, reg, opts->gen.scratch1, SZ_D); |
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941 shr_ir(code, 24, opts->gen.scratch1, SZ_D); |
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|
942 push_r(code, opts->gen.scratch2); |
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943 call(code, opts->write_8); |
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Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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944 pop_r(code, opts->gen.scratch2); |
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945 mov_rr(code, reg, opts->gen.scratch1, SZ_D); |
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|
946 shr_ir(code, 16, opts->gen.scratch1, SZ_D); |
447
e730fc040169
Fix performance regression from stop instruction work
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diff
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|
947 |
172 | 948 } else { |
567
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949 mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src))+3, opts->gen.scratch1, SZ_B); |
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950 push_r(code, opts->gen.scratch2); |
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951 call(code, opts->write_8); |
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952 pop_r(code, opts->gen.scratch2); |
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953 mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src))+2, opts->gen.scratch1, SZ_B); |
172 | 954 } |
567
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955 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
8e395210f50f
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changeset
|
956 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
957 call(code, opts->write_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
958 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
959 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
172 | 960 } |
961 if (reg >= 0) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
962 mov_rr(code, reg, opts->gen.scratch1, SZ_W); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
963 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
964 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
965 call(code, opts->write_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
966 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
967 mov_rr(code, reg, opts->gen.scratch1, SZ_W); |
172 | 968 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
969 mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src))+1, opts->gen.scratch1, SZ_B); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
970 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
971 call(code, opts->write_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
972 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
973 mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src)), opts->gen.scratch1, SZ_B); |
172 | 974 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
975 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
976 call(code, opts->write_8); |
172 | 977 } else { |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
978 calc_areg_displace(opts, &inst->src, opts->gen.scratch1); |
172 | 979 reg = native_reg(&(inst->dst), opts); |
980 if (inst->extra.size == OPSIZE_LONG) { | |
981 if (reg >= 0) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
982 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
983 call(code, opts->read_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
984 shl_ir(code, 24, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
985 mov_rr(code, opts->gen.scratch1, reg, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
986 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
987 add_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
988 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
989 call(code, opts->read_8); |
1026
7267bc1ab547
Fix bug in 68K movep.l when the destination is a register mapped to a host register
Michael Pavone <pavone@retrodev.com>
parents:
996
diff
changeset
|
990 movzx_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B, SZ_W); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
991 shl_ir(code, 16, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
992 or_rr(code, opts->gen.scratch1, reg, SZ_D); |
172 | 993 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
994 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
995 call(code, opts->read_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
996 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, reg_offset(&(inst->dst))+3, SZ_B); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
997 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
998 add_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
999 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1000 call(code, opts->read_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1001 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, reg_offset(&(inst->dst))+2, SZ_B); |
172 | 1002 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1003 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1004 add_ir(code, 2, opts->gen.scratch1, SZ_D); |
172 | 1005 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1006 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1007 call(code, opts->read_8); |
172 | 1008 if (reg >= 0) { |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
1009 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1010 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1011 mov_rr(code, opts->gen.scratch1, reg, SZ_W); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1012 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1013 add_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1014 call(code, opts->read_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1015 mov_rr(code, opts->gen.scratch1, reg, SZ_B); |
172 | 1016 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1017 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, reg_offset(&(inst->dst))+1, SZ_B); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1018 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1019 add_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1020 call(code, opts->read_8); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1021 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, reg_offset(&(inst->dst)), SZ_B); |
172 | 1022 } |
1023 } | |
1024 } | |
1025 | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1026 typedef void (*shift_ir_t)(code_info *code, uint8_t val, uint8_t dst, uint8_t size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1027 typedef void (*shift_irdisp_t)(code_info *code, uint8_t val, uint8_t dst_base, int32_t disp, uint8_t size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1028 typedef void (*shift_clr_t)(code_info *code, uint8_t dst, uint8_t size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1029 typedef void (*shift_clrdisp_t)(code_info *code, uint8_t dst_base, int32_t disp, uint8_t size); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1030 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1031 void translate_shift(m68k_options * opts, m68kinst * inst, host_ea *src_op, host_ea * dst_op, shift_ir_t shift_ir, shift_irdisp_t shift_irdisp, shift_clr_t shift_clr, shift_clrdisp_t shift_clrdisp, shift_ir_t special, shift_irdisp_t special_disp) |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
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49
diff
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|
1032 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1033 code_info *code = &opts->gen.code; |
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1034 code_ptr end_off = NULL; |
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1035 code_ptr nz_off = NULL; |
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1036 code_ptr z_off = NULL; |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1037 ALLOC_CODE_RETRY_VAR; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1038 if (inst->src.addr_mode == MODE_UNUSED) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1039 cycles(&opts->gen, BUS); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1040 //Memory shift |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1041 shift_ir(code, 1, dst_op->base, SZ_W); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1042 } else { |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1043 ALLOC_CODE_RETRY_POINT_NO_VAR |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1044 if (src_op->mode == MODE_IMMED) { |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
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|
1045 cycles(&opts->gen, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + 2 * src_op->disp); |
207 | 1046 if (src_op->disp != 1 && inst->op == M68K_ASL) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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558
diff
changeset
|
1047 set_flag(opts, 0, FLAG_V); |
207 | 1048 for (int i = 0; i < src_op->disp; i++) { |
1049 if (dst_op->mode == MODE_REG_DIRECT) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1050 shift_ir(code, 1, dst_op->base, inst->extra.size); |
207 | 1051 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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|
1052 shift_irdisp(code, 1, dst_op->base, dst_op->disp, inst->extra.size); |
207 | 1053 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1054 code_ptr after_flag_set = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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|
1055 jcc(code, CC_NO, code->cur + 2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1056 set_flag(opts, 1, FLAG_V); |
2268
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Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
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2240
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|
1057 CHECK_BRANCH_DEST(after_flag_set); |
207 | 1058 } |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
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|
1059 } else { |
207 | 1060 if (dst_op->mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1061 shift_ir(code, src_op->disp, dst_op->base, inst->extra.size); |
207 | 1062 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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|
1063 shift_irdisp(code, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
207 | 1064 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
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|
1065 set_flag_cond(opts, CC_O, FLAG_V); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
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49
diff
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|
1066 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
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|
1067 } else { |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
1068 cycles(&opts->gen, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1069 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
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|
1070 if (src_op->mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1071 mov_rr(code, src_op->base, RCX, SZ_B); |
51
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Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1072 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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changeset
|
1073 mov_rdispr(code, src_op->base, src_op->disp, RCX, SZ_B); |
51
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Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
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|
1074 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
1075 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
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|
1076 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1077 and_ir(code, 63, RCX, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1078 nz_off = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1079 jcc(code, CC_NZ, code->cur + 2); |
207 | 1080 //Flag behavior for shift count of 0 is different for x86 than 68K |
1081 if (dst_op->mode == MODE_REG_DIRECT) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1082 cmp_ir(code, 0, dst_op->base, inst->extra.size); |
207 | 1083 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1084 cmp_irdisp(code, 0, dst_op->base, dst_op->disp, inst->extra.size); |
207 | 1085 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1086 set_flag_cond(opts, CC_Z, FLAG_Z); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1087 set_flag_cond(opts, CC_S, FLAG_N); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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changeset
|
1088 set_flag(opts, 0, FLAG_C); |
207 | 1089 //For other instructions, this flag will be set below |
1090 if (inst->op == M68K_ASL) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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|
1091 set_flag(opts, 0, FLAG_V); |
207 | 1092 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1093 z_off = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1094 jmp(code, code->cur + 2); |
2268
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Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
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2240
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changeset
|
1095 CHECK_BRANCH_DEST(nz_off); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1096 //add 2 cycles for every bit shifted |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
1097 mov_ir(code, 2 * opts->gen.clock_divider, opts->gen.scratch2, SZ_D); |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
1098 imul_rr(code, RCX, opts->gen.scratch2, SZ_D); |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
1099 add_rr(code, opts->gen.scratch2, opts->gen.cycles, SZ_D); |
207 | 1100 if (inst->op == M68K_ASL) { |
1101 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB | |
1102 //Easiest way to deal with this is to shift one bit at a time | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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558
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changeset
|
1103 set_flag(opts, 0, FLAG_V); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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558
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changeset
|
1104 code_ptr loop_start = code->cur; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
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49
diff
changeset
|
1105 if (dst_op->mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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changeset
|
1106 shift_ir(code, 1, dst_op->base, inst->extra.size); |
51
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Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
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diff
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|
1107 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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changeset
|
1108 shift_irdisp(code, 1, dst_op->base, dst_op->disp, inst->extra.size); |
51
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Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
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|
1109 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
1110 code_ptr after_flag_set = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
1111 jcc(code, CC_NO, code->cur + 2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
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changeset
|
1112 set_flag(opts, 1, FLAG_V); |
2268
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Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
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|
1113 CHECK_BRANCH_DEST(after_flag_set); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1114 loop(code, loop_start); |
207 | 1115 } else { |
1116 //x86 shifts modulo 32 for operand sizes less than 64-bits | |
1117 //but M68K shifts modulo 64, so we need to check for large shifts here | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1118 cmp_ir(code, 32, RCX, SZ_B); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1119 code_ptr norm_shift_off = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1120 jcc(code, CC_L, code->cur + 2); |
207 | 1121 if (special) { |
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1122 code_ptr after_flag_set = NULL; |
207 | 1123 if (inst->extra.size == OPSIZE_LONG) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1124 code_ptr neq_32_off = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1125 jcc(code, CC_NZ, code->cur + 2); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
1126 |
207 | 1127 //set the carry bit to the lsb |
1128 if (dst_op->mode == MODE_REG_DIRECT) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1129 special(code, 1, dst_op->base, SZ_D); |
207 | 1130 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1131 special_disp(code, 1, dst_op->base, dst_op->disp, SZ_D); |
207 | 1132 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1133 set_flag_cond(opts, CC_C, FLAG_C); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1134 after_flag_set = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1135 jmp(code, code->cur + 2); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1136 CHECK_BRANCH_DEST(neq_32_off); |
207 | 1137 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1138 set_flag(opts, 0, FLAG_C); |
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1139 if (after_flag_set) { |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1140 CHECK_BRANCH_DEST(after_flag_set); |
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1141 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1142 set_flag(opts, 1, FLAG_Z); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1143 set_flag(opts, 0, FLAG_N); |
207 | 1144 if (dst_op->mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1145 xor_rr(code, dst_op->base, dst_op->base, inst->extra.size); |
207 | 1146 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1147 mov_irdisp(code, 0, dst_op->base, dst_op->disp, inst->extra.size); |
207 | 1148 } |
1149 } else { | |
1150 if (dst_op->mode == MODE_REG_DIRECT) { | |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1151 shift_ir(code, 31, dst_op->base, inst->extra.size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1152 shift_ir(code, 1, dst_op->base, inst->extra.size); |
207 | 1153 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1154 shift_irdisp(code, 31, dst_op->base, dst_op->disp, inst->extra.size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1155 shift_irdisp(code, 1, dst_op->base, dst_op->disp, inst->extra.size); |
207 | 1156 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
1157 |
207 | 1158 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1159 end_off = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1160 jmp(code, code->cur + 2); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1161 CHECK_BRANCH_DEST(norm_shift_off); |
207 | 1162 if (dst_op->mode == MODE_REG_DIRECT) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1163 shift_clr(code, dst_op->base, inst->extra.size); |
207 | 1164 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1165 shift_clrdisp(code, dst_op->base, dst_op->disp, inst->extra.size); |
207 | 1166 } |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1167 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1168 } |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
1169 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1170 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1171 if (!special && end_off) { |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1172 CHECK_BRANCH_DEST(end_off); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1173 } |
583
819921b76b4b
Use update_flags instead of individual set_flag calls in a few places
Michael Pavone <pavone@retrodev.com>
parents:
582
diff
changeset
|
1174 update_flags(opts, C|Z|N); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1175 if (special && end_off) { |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1176 CHECK_BRANCH_DEST(end_off); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1177 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1178 //set X flag to same as C flag |
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1179 if (opts->flag_regs[FLAG_C] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1180 flag_to_flag(opts, FLAG_C, FLAG_X); |
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1181 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1182 set_flag_cond(opts, CC_C, FLAG_X); |
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1183 } |
207 | 1184 if (z_off) { |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1185 CHECK_BRANCH_DEST(z_off); |
207 | 1186 } |
219
8d3c16071559
Fix overflow flag behavior for lsl/lsr/asr
Mike Pavone <pavone@retrodev.com>
parents:
218
diff
changeset
|
1187 if (inst->op != M68K_ASL) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1188 set_flag(opts, 0, FLAG_V); |
207 | 1189 } |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1190 if (inst->src.addr_mode == MODE_UNUSED) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
1191 m68k_save_result(inst, opts); |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1192 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1193 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1194 |
1082
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1195 void translate_m68k_reset(m68k_options *opts, m68kinst *inst) |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1196 { |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1197 code_info *code = &opts->gen.code; |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1198 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, reset_handler), opts->gen.scratch1, SZ_PTR); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1199 cmp_ir(code, 0, opts->gen.scratch1, SZ_PTR); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1200 code_ptr no_reset_handler = code->cur + 1; |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1201 jcc(code, CC_Z, code->cur+2); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1202 call(code, opts->gen.save_context); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1203 call_args_r(code, opts->gen.scratch1, 1, opts->gen.context_reg); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1204 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1205 call(code, opts->gen.load_context); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1206 *no_reset_handler = code->cur - (no_reset_handler + 1); |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1207 //RESET instructions take a long time to give peripherals time to reset themselves |
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1208 cycles(&opts->gen, 132); |
1082
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1209 } |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
1210 |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1211 void op_ir(code_info *code, m68kinst *inst, int32_t val, uint8_t dst, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1212 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1213 switch (inst->op) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1214 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1215 case M68K_ADD: add_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1216 case M68K_ADDX: adc_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1217 case M68K_AND: and_ir(code, val, dst, size); break; |
581
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1218 case M68K_BTST: bt_ir(code, val, dst, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1219 case M68K_BSET: bts_ir(code, val, dst, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1220 case M68K_BCLR: btr_ir(code, val, dst, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1221 case M68K_BCHG: btc_ir(code, val, dst, size); break; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1222 case M68K_CMP: cmp_ir(code, val, dst, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1223 case M68K_EOR: xor_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1224 case M68K_OR: or_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1225 case M68K_ROL: rol_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1226 case M68K_ROR: ror_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1227 case M68K_ROXL: rcl_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1228 case M68K_ROXR: rcr_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1229 case M68K_SUB: sub_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1230 case M68K_SUBX: sbb_ir(code, val, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1231 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1232 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1233 |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1234 void op_irdisp(code_info *code, m68kinst *inst, int32_t val, uint8_t dst, int32_t disp, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1235 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1236 switch (inst->op) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1237 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1238 case M68K_ADD: add_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1239 case M68K_ADDX: adc_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1240 case M68K_AND: and_irdisp(code, val, dst, disp, size); break; |
581
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1241 case M68K_BTST: bt_irdisp(code, val, dst, disp, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1242 case M68K_BSET: bts_irdisp(code, val, dst, disp, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1243 case M68K_BCLR: btr_irdisp(code, val, dst, disp, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1244 case M68K_BCHG: btc_irdisp(code, val, dst, disp, size); break; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1245 case M68K_CMP: cmp_irdisp(code, val, dst, disp, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1246 case M68K_EOR: xor_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1247 case M68K_OR: or_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1248 case M68K_ROL: rol_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1249 case M68K_ROR: ror_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1250 case M68K_ROXL: rcl_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1251 case M68K_ROXR: rcr_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1252 case M68K_SUB: sub_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1253 case M68K_SUBX: sbb_irdisp(code, val, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1254 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1255 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1256 |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1257 void op_rr(code_info *code, m68kinst *inst, uint8_t src, uint8_t dst, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1258 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1259 switch (inst->op) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1260 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1261 case M68K_ADD: add_rr(code, src, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1262 case M68K_ADDX: adc_rr(code, src, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1263 case M68K_AND: and_rr(code, src, dst, size); break; |
581
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1264 case M68K_BTST: bt_rr(code, src, dst, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1265 case M68K_BSET: bts_rr(code, src, dst, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1266 case M68K_BCLR: btr_rr(code, src, dst, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1267 case M68K_BCHG: btc_rr(code, src, dst, size); break; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1268 case M68K_CMP: cmp_rr(code, src, dst, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1269 case M68K_EOR: xor_rr(code, src, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1270 case M68K_OR: or_rr(code, src, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1271 case M68K_SUB: sub_rr(code, src, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1272 case M68K_SUBX: sbb_rr(code, src, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1273 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1274 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1275 |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1276 void op_rrdisp(code_info *code, m68kinst *inst, uint8_t src, uint8_t dst, int32_t disp, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1277 { |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1278 switch(inst->op) |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1279 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1280 case M68K_ADD: add_rrdisp(code, src, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1281 case M68K_ADDX: adc_rrdisp(code, src, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1282 case M68K_AND: and_rrdisp(code, src, dst, disp, size); break; |
581
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1283 case M68K_BTST: bt_rrdisp(code, src, dst, disp, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1284 case M68K_BSET: bts_rrdisp(code, src, dst, disp, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1285 case M68K_BCLR: btr_rrdisp(code, src, dst, disp, size); break; |
9f40aa5243c2
Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
Michael Pavone <pavone@retrodev.com>
parents:
580
diff
changeset
|
1286 case M68K_BCHG: btc_rrdisp(code, src, dst, disp, size); break; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1287 case M68K_CMP: cmp_rrdisp(code, src, dst, disp, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1288 case M68K_EOR: xor_rrdisp(code, src, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1289 case M68K_OR: or_rrdisp(code, src, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1290 case M68K_SUB: sub_rrdisp(code, src, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1291 case M68K_SUBX: sbb_rrdisp(code, src, dst, disp, size); break; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1292 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1293 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1294 |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1295 void op_rdispr(code_info *code, m68kinst *inst, uint8_t src, int32_t disp, uint8_t dst, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1296 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1297 switch (inst->op) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1298 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1299 case M68K_ADD: add_rdispr(code, src, disp, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1300 case M68K_ADDX: adc_rdispr(code, src, disp, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1301 case M68K_AND: and_rdispr(code, src, disp, dst, size); break; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1302 case M68K_CMP: cmp_rdispr(code, src, disp, dst, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1303 case M68K_EOR: xor_rdispr(code, src, disp, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1304 case M68K_OR: or_rdispr(code, src, disp, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1305 case M68K_SUB: sub_rdispr(code, src, disp, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1306 case M68K_SUBX: sbb_rdispr(code, src, disp, dst, size); break; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1307 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1308 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1309 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1310 void translate_m68k_arith(m68k_options *opts, m68kinst * inst, uint32_t flag_mask, host_ea *src_op, host_ea *dst_op) |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1311 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1312 code_info *code = &opts->gen.code; |
1219
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1313 uint8_t size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1314 |
1219
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1315 uint32_t numcycles; |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1316 if ((inst->op == M68K_ADDX || inst->op == M68K_SUBX) && inst->src.addr_mode != MODE_REG) { |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1317 numcycles = 4; |
1219
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1318 } else if (size == OPSIZE_LONG) { |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1319 if (inst->op == M68K_CMP) { |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1320 numcycles = inst->src.addr_mode > MODE_AREG && inst->dst.addr_mode > MODE_AREG ? 4 : 6; |
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1321 } else if (inst->dst.addr_mode == MODE_REG) { |
1219
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1322 numcycles = inst->src.addr_mode <= MODE_AREG || inst->src.addr_mode == MODE_IMMEDIATE ? 8 : 6; |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1323 } else if (inst->dst.addr_mode == MODE_AREG) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1324 numcycles = numcycles = inst->src.addr_mode <= MODE_AREG || inst->src.addr_mode == MODE_IMMEDIATE |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1325 || inst->extra.size == OPSIZE_WORD ? 8 : 6; |
1219
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1326 } else { |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1327 numcycles = 4; |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1328 } |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1329 } else { |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1330 numcycles = 4; |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1331 } |
4399044adbef
Fix timing for instructions using BINARY_IMPL
Michael Pavone <pavone@retrodev.com>
parents:
1216
diff
changeset
|
1332 cycles(&opts->gen, numcycles); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1333 |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1334 if (inst->op == M68K_ADDX || inst->op == M68K_SUBX) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1335 flag_to_carry(opts, FLAG_X); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1336 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1337 |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1338 if (src_op->mode == MODE_REG_DIRECT) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1339 if (dst_op->mode == MODE_REG_DIRECT) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1340 op_rr(code, inst, src_op->base, dst_op->base, size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1341 } else { |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1342 op_rrdisp(code, inst, src_op->base, dst_op->base, dst_op->disp, size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1343 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1344 } else if (src_op->mode == MODE_REG_DISPLACE8) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1345 op_rdispr(code, inst, src_op->base, src_op->disp, dst_op->base, size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1346 } else { |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1347 if (dst_op->mode == MODE_REG_DIRECT) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1348 op_ir(code, inst, src_op->disp, dst_op->base, size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1349 } else { |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1350 op_irdisp(code, inst, src_op->disp, dst_op->base, dst_op->disp, size); |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1351 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1352 } |
580
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1353 if (inst->dst.addr_mode != MODE_AREG || inst->op == M68K_CMP) { |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1354 update_flags(opts, flag_mask); |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1355 if (inst->op == M68K_ADDX || inst->op == M68K_SUBX) { |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
1356 code_ptr after_flag_set; |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1357 ALLOC_CODE_RETRY_POINT |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
1358 after_flag_set = code->cur + 1; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1359 jcc(code, CC_Z, code->cur + 2); |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1360 set_flag(opts, 0, FLAG_Z); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1361 CHECK_BRANCH_DEST(after_flag_set); |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1362 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1363 } |
580
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1364 if (inst->op != M68K_CMP) { |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1365 m68k_save_result(inst, opts); |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1366 } |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1367 } |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1368 |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1369 void translate_m68k_cmp(m68k_options * opts, m68kinst * inst) |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1370 { |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1371 code_info *code = &opts->gen.code; |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1372 uint8_t size = inst->extra.size; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1373 host_ea src_op, dst_op; |
580
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1374 translate_m68k_op(inst, &src_op, opts, 0); |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1375 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1376 push_r(code, opts->gen.scratch1); |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1377 translate_m68k_op(inst, &dst_op, opts, 1); |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1378 pop_r(code, opts->gen.scratch2); |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1379 src_op.base = opts->gen.scratch2; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1380 } else { |
580
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1381 translate_m68k_op(inst, &dst_op, opts, 1); |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1382 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) { |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1383 size = OPSIZE_LONG; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1384 } |
580
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1385 } |
5157bc966c1a
Refactor translate_m68k_cmp to use translate_m68k_arith
Michael Pavone <pavone@retrodev.com>
parents:
579
diff
changeset
|
1386 translate_m68k_arith(opts, inst, N|Z|V|C, &src_op, &dst_op); |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1387 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1388 |
837 | 1389 void translate_m68k_tas(m68k_options *opts, m68kinst *inst) |
1390 { | |
1391 code_info *code = &opts->gen.code; | |
1392 host_ea op; | |
1393 translate_m68k_op(inst, &op, opts, 1); | |
1394 if (op.mode == MODE_REG_DIRECT) { | |
1395 cmp_ir(code, 0, op.base, SZ_B); | |
1396 } else { | |
1397 cmp_irdisp(code, 0, op.base, op.disp, SZ_B); | |
1398 } | |
1399 update_flags(opts, N|Z|V0|C0); | |
1400 if (inst->dst.addr_mode == MODE_REG) { | |
1401 cycles(&opts->gen, BUS); | |
1402 if (op.mode == MODE_REG_DIRECT) { | |
1403 bts_ir(code, 7, op.base, SZ_B); | |
1404 } else { | |
1405 bts_irdisp(code, 7, op.base, op.disp, SZ_B); | |
1406 } | |
1407 } else { | |
1408 if (opts->gen.flags & M68K_OPT_BROKEN_READ_MODIFY) { | |
1409 //2 cycles for processing | |
1410 //4 for failed writeback | |
1411 //4 for prefetch | |
1412 cycles(&opts->gen, BUS * 2 + 2); | |
1413 } else { | |
1414 cycles(&opts->gen, 2); | |
1415 bts_ir(code, 7, op.base, SZ_B); | |
1416 m68k_save_result(inst, opts); | |
1417 cycles(&opts->gen, BUS); | |
1418 } | |
1419 } | |
1420 } | |
1421 | |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1422 void op_r(code_info *code, m68kinst *inst, uint8_t dst, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1423 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1424 switch(inst->op) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1425 { |
1584
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1426 case M68K_CLR: xor_rr(code, dst, dst, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1427 case M68K_NEG: neg_r(code, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1428 case M68K_NOT: not_r(code, dst, size); cmp_ir(code, 0, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1429 case M68K_ROL: rol_clr(code, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1430 case M68K_ROR: ror_clr(code, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1431 case M68K_ROXL: rcl_clr(code, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1432 case M68K_ROXR: rcr_clr(code, dst, size); break; |
578
ec1365fb2954
Use translate_m68k_unary for SWAP in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
577
diff
changeset
|
1433 case M68K_SWAP: rol_ir(code, 16, dst, SZ_D); cmp_ir(code, 0, dst, SZ_D); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1434 case M68K_TST: cmp_ir(code, 0, dst, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1435 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1436 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1437 |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1438 void op_rdisp(code_info *code, m68kinst *inst, uint8_t dst, int32_t disp, uint8_t size) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1439 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1440 switch(inst->op) |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1441 { |
1584
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1442 case M68K_CLR: mov_irdisp(code, 0, dst, disp, size); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1443 case M68K_NEG: neg_rdisp(code, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1444 case M68K_NOT: not_rdisp(code, dst, disp, size); cmp_irdisp(code, 0, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1445 case M68K_ROL: rol_clrdisp(code, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1446 case M68K_ROR: ror_clrdisp(code, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1447 case M68K_ROXL: rcl_clrdisp(code, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1448 case M68K_ROXR: rcr_clrdisp(code, dst, disp, size); break; |
578
ec1365fb2954
Use translate_m68k_unary for SWAP in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
577
diff
changeset
|
1449 case M68K_SWAP: rol_irdisp(code, 16, dst, disp, SZ_D); cmp_irdisp(code, 0, dst, disp, SZ_D); break; |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1450 case M68K_TST: cmp_irdisp(code, 0, dst, disp, size); break; |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1451 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1452 } |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1453 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1454 void translate_m68k_unary(m68k_options *opts, m68kinst *inst, uint32_t flag_mask, host_ea *dst_op) |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1455 { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1456 code_info *code = &opts->gen.code; |
1584
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1457 uint32_t num_cycles = BUS; |
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1458 if (inst->extra.size == OPSIZE_LONG && (inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG)) { |
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1459 num_cycles += 2; |
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1460 } |
e01adbe1a75b
Fix instruction timing for a number of instructions with only a single operand
Michael Pavone <pavone@retrodev.com>
parents:
1510
diff
changeset
|
1461 cycles(&opts->gen, num_cycles); |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1462 if (dst_op->mode == MODE_REG_DIRECT) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1463 op_r(code, inst, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1464 } else { |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1465 op_rdisp(code, inst, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1466 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1467 update_flags(opts, flag_mask); |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1468 m68k_save_result(inst, opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1469 } |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
1470 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1471 void translate_m68k_abcd_sbcd(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1472 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1473 code_info *code = &opts->gen.code; |
834 | 1474 if (inst->op == M68K_NBCD) { |
1475 if (dst_op->base != opts->gen.scratch2) { | |
1476 if (dst_op->mode == MODE_REG_DIRECT) { | |
1477 mov_rr(code, dst_op->base, opts->gen.scratch2, SZ_B); | |
1478 } else { | |
1479 mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch2, SZ_B); | |
1480 } | |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
1481 } |
834 | 1482 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B); |
1483 } else { | |
1484 if (src_op->base != opts->gen.scratch2) { | |
1485 if (src_op->mode == MODE_REG_DIRECT) { | |
1486 mov_rr(code, src_op->base, opts->gen.scratch2, SZ_B); | |
1487 } else { | |
1488 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch2, SZ_B); | |
1489 } | |
1490 } | |
1491 if (dst_op->base != opts->gen.scratch1) { | |
1492 if (dst_op->mode == MODE_REG_DIRECT) { | |
1493 mov_rr(code, dst_op->base, opts->gen.scratch1, SZ_B); | |
1494 } else { | |
1495 mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch1, SZ_B); | |
1496 } | |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1497 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1498 } |
1461
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1499 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG && inst->dst.addr_mode != MODE_AREG_PREDEC) { |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1500 //destination is in memory so we need to preserve scratch2 for the write at the end |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1501 push_r(code, opts->gen.scratch2); |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1502 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1503 |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1504 //reg to reg takes 6 cycles, mem to mem is 4 cycles + all the operand fetch/writing (including 2 cycle predec penalty for first operand) |
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
1505 cycles(&opts->gen, inst->dst.addr_mode != MODE_REG ? BUS : BUS + 2); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1506 uint8_t other_reg; |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1507 //WARNING: This may need adjustment if register assignments change |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1508 if (opts->gen.scratch2 > RBX) { |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1509 other_reg = RAX; |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1510 xchg_rr(code, opts->gen.scratch2, RAX, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1511 } else { |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1512 other_reg = opts->gen.scratch2; |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1513 } |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1514 mov_rr(code, opts->gen.scratch1, opts->gen.scratch1 + (AH-RAX), SZ_B); |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1515 mov_rr(code, other_reg, other_reg + (AH-RAX), SZ_B); |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1516 and_ir(code, 0xF, opts->gen.scratch1 + (AH-RAX), SZ_B); |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1517 and_ir(code, 0xF, other_reg + (AH-RAX), SZ_B); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1518 //do op on low nibble so we can determine if an adjustment is necessary |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1519 flag_to_carry(opts, FLAG_X); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1520 if (inst->op == M68K_ABCD) { |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1521 adc_rr(code, other_reg + (AH-RAX), opts->gen.scratch1 + (AH-RAX), SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1522 } else { |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1523 sbb_rr(code, other_reg + (AH-RAX), opts->gen.scratch1 + (AH-RAX), SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1524 } |
1297
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1525 cmp_ir(code, inst->op == M68K_SBCD ? 0x10 : 0xA, opts->gen.scratch1 + (AH-RAX), SZ_B); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1526 mov_ir(code, 0xA0, other_reg + (AH-RAX), SZ_B); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1527 code_ptr no_adjust = code->cur+1; |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1528 //add correction factor if necessary |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1529 jcc(code, CC_B, no_adjust); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1530 mov_ir(code, 6, opts->gen.scratch1 + (AH-RAX), SZ_B); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1531 mov_ir(code, inst->op == M68K_ABCD ? 0x9A : 0xA6, other_reg + (AH-RAX), SZ_B); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1532 code_ptr after_adjust = code->cur+1; |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1533 jmp(code, after_adjust); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1534 |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1535 *no_adjust = code->cur - (no_adjust+1); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1536 xor_rr(code, opts->gen.scratch1 + (AH-RAX), opts->gen.scratch1 + (AH-RAX), SZ_B); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1537 *after_adjust = code->cur - (after_adjust+1); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1538 |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1539 //do op on full byte |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1540 flag_to_carry(opts, FLAG_X); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1541 if (inst->op == M68K_ABCD) { |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1542 adc_rr(code, other_reg, opts->gen.scratch1, SZ_B); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1543 } else { |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1544 sbb_rr(code, other_reg, opts->gen.scratch1, SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1545 } |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1546 set_flag(opts, 0, FLAG_C); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1547 //determine if we need a correction on the upper nibble |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1548 code_ptr def_adjust = code->cur+1; |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1549 jcc(code, CC_C, def_adjust); |
1297
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1550 if (inst->op == M68K_SBCD) { |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1551 no_adjust = code->cur+1; |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1552 jmp(code, no_adjust); |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1553 } else { |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1554 cmp_rr(code, other_reg + (AH-RAX), opts->gen.scratch1, SZ_B); |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1555 no_adjust = code->cur+1; |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1556 jcc(code, CC_B, no_adjust); |
71b1a080b30c
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Michael Pavone <pavone@retrodev.com>
parents:
1284
diff
changeset
|
1557 } |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1558 *def_adjust = code->cur - (def_adjust + 1); |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1559 set_flag(opts, 1, FLAG_C); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1560 or_ir(code, 0x60, opts->gen.scratch1 + (AH-RAX), SZ_B); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1561 *no_adjust = code->cur - (no_adjust+1); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1562 if (inst->op == M68K_ABCD) { |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1563 add_rr(code, opts->gen.scratch1 + (AH-RAX), opts->gen.scratch1, SZ_B); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1564 } else { |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1565 sub_rr(code, opts->gen.scratch1 + (AH-RAX), opts->gen.scratch1, SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1566 } |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1567 code_ptr no_ensure_carry = code->cur+1; |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1568 jcc(code, CC_NC, no_ensure_carry); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1569 set_flag(opts, 1, FLAG_C); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1570 *no_ensure_carry = code->cur - (no_ensure_carry+1); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1571 //restore RAX if necessary |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1572 if (opts->gen.scratch2 > RBX) { |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1573 mov_rr(code, opts->gen.scratch2, RAX, SZ_D); |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1574 } |
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1575 //V flag is set based on the result of the addition/subtraction of the |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1576 //result and the correction factor |
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1577 set_flag_cond(opts, CC_O, FLAG_V); |
833
841e44c5af83
Fix for abcd/sbcd. Hopefully got it 100% right this time.
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
1578 |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1579 flag_to_flag(opts, FLAG_C, FLAG_X); |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
1580 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1581 cmp_ir(code, 0, opts->gen.scratch1, SZ_B); |
612
5a6ff0d76032
Removed bcd_add and bcd_sub from runtime.S and generated the logic inline with the rest of abcd and sbcd translation. Fixed some edge cases and undefined flag behavior in the process
Michael Pavone <pavone@retrodev.com>
parents:
611
diff
changeset
|
1582 set_flag_cond(opts, CC_S, FLAG_N); |
733
fbda8e865dae
Fix crash bug in 32-bit build for certain secnarios with bcd instructions
Michael Pavone <pavone@retrodev.com>
parents:
732
diff
changeset
|
1583 code_ptr no_setz = code->cur+1; |
fbda8e865dae
Fix crash bug in 32-bit build for certain secnarios with bcd instructions
Michael Pavone <pavone@retrodev.com>
parents:
732
diff
changeset
|
1584 jcc(code, CC_Z, no_setz); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1585 set_flag(opts, 0, FLAG_Z); |
733
fbda8e865dae
Fix crash bug in 32-bit build for certain secnarios with bcd instructions
Michael Pavone <pavone@retrodev.com>
parents:
732
diff
changeset
|
1586 *no_setz = code->cur - (no_setz + 1); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1587 if (dst_op->base != opts->gen.scratch1) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1588 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1589 mov_rr(code, opts->gen.scratch1, dst_op->base, SZ_B); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1590 } else { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1591 mov_rrdisp(code, opts->gen.scratch1, dst_op->base, dst_op->disp, SZ_B); |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1592 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1593 } |
1461
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1594 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG && inst->dst.addr_mode != MODE_AREG_PREDEC) { |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1595 //destination is in memory so we need to restore scratch2 for the write at the end |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1596 pop_r(code, opts->gen.scratch2); |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
1597 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1598 m68k_save_result(inst, opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1599 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1600 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1601 void translate_m68k_sl(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1602 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1603 translate_shift(opts, inst, src_op, dst_op, shl_ir, shl_irdisp, shl_clr, shl_clrdisp, shr_ir, shr_irdisp); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1604 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1605 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1606 void translate_m68k_asr(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1607 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1608 translate_shift(opts, inst, src_op, dst_op, sar_ir, sar_irdisp, sar_clr, sar_clrdisp, NULL, NULL); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1609 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1610 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1611 void translate_m68k_lsr(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1612 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1613 translate_shift(opts, inst, src_op, dst_op, shr_ir, shr_irdisp, shr_clr, shr_clrdisp, shl_ir, shl_irdisp); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1614 } |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1615 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1616 void translate_m68k_bit(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1617 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1618 code_info *code = &opts->gen.code; |
2224
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1619 cycles(&opts->gen, inst->extra.size == OPSIZE_BYTE ? (dst_op->mode == MODE_IMMED ? 6 : 4) : ( |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1620 inst->op == M68K_BCLR ? 8 : 6) |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1621 ); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1622 if (src_op->mode == MODE_IMMED) { |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1623 if (inst->extra.size == OPSIZE_BYTE) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1624 src_op->disp &= 0x7; |
2224
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1625 } else if (inst->op != M68K_BTST && src_op->disp > 15) { |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1626 //bit operations that need to save the result have a 2 cycle penalty when operating on the upper word |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1627 cycles(&opts->gen, 2); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1628 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1629 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1630 op_ir(code, inst, src_op->disp, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1631 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1632 op_irdisp(code, inst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1633 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1634 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1635 if (src_op->mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op->base != opts->gen.scratch1 && src_op->base != opts->gen.scratch2)) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1636 if (dst_op->base == opts->gen.scratch1) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1637 push_r(code, opts->gen.scratch2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1638 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1639 mov_rr(code, src_op->base, opts->gen.scratch2, SZ_B); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1640 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1641 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch2, SZ_B); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1642 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1643 src_op->base = opts->gen.scratch2; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1644 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1645 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1646 mov_rr(code, src_op->base, opts->gen.scratch1, SZ_B); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1647 } else { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1648 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_B); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1649 } |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1650 src_op->base = opts->gen.scratch1; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1651 } |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
1652 } |
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
1653 uint8_t size = inst->extra.size; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1654 if (dst_op->mode == MODE_REG_DISPLACE8) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1655 if (src_op->base != opts->gen.scratch1 && src_op->base != opts->gen.scratch2) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1656 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1657 mov_rr(code, src_op->base, opts->gen.scratch1, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1658 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1659 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1660 src_op->mode = MODE_REG_DIRECT; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1661 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1662 src_op->base = opts->gen.scratch1; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1663 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1664 //b### with register destination is modulo 32 |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1665 //x86 with a memory destination isn't modulo anything |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1666 //so use an and here to force the value to be modulo 32 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1667 and_ir(code, 31, opts->gen.scratch1, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1668 } else if(inst->dst.addr_mode != MODE_REG) { |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1669 //b### with memory destination is modulo 8 |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1670 //x86-64 doesn't support 8-bit bit operations |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1671 //so we fake it by forcing the bit number to be modulo 8 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1672 and_ir(code, 7, src_op->base, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1673 size = SZ_D; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1674 } |
2224
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1675 if (inst->op != M68K_BTST && inst->extra.size != OPSIZE_BYTE) { |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1676 //bit operations that need to save the result have a 2 cycle penalty when operating on the upper word |
2240
8e8db9141209
Fix crash regression in m68k bit instruction implementation
Michael Pavone <pavone@retrodev.com>
parents:
2232
diff
changeset
|
1677 cmp_ir(code, 16, src_op->base, SZ_B); |
2224
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1678 code_ptr jmp_off = code->cur + 1; |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1679 jcc(code, CC_C, jmp_off + 1); |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1680 cycles(&opts->gen, 2); |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1681 *jmp_off = code->cur - (jmp_off + 1); |
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1682 } |
976
8cdd4ddedd9a
Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
Michael Pavone <pavone@retrodev.com>
parents:
908
diff
changeset
|
1683 if (dst_op->mode == MODE_IMMED) { |
8cdd4ddedd9a
Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
Michael Pavone <pavone@retrodev.com>
parents:
908
diff
changeset
|
1684 dst_op->base = src_op->base == opts->gen.scratch1 ? opts->gen.scratch2 : opts->gen.scratch1; |
8cdd4ddedd9a
Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
Michael Pavone <pavone@retrodev.com>
parents:
908
diff
changeset
|
1685 mov_ir(code, dst_op->disp, dst_op->base, SZ_B); |
8cdd4ddedd9a
Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
Michael Pavone <pavone@retrodev.com>
parents:
908
diff
changeset
|
1686 dst_op->mode = MODE_REG_DIRECT; |
8cdd4ddedd9a
Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
Michael Pavone <pavone@retrodev.com>
parents:
908
diff
changeset
|
1687 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1688 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1689 op_rr(code, inst, src_op->base, dst_op->base, size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1690 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1691 op_rrdisp(code, inst, src_op->base, dst_op->base, dst_op->disp, size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1692 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1693 if (src_op->base == opts->gen.scratch2) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1694 pop_r(code, opts->gen.scratch2); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1695 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1696 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1697 //x86 sets the carry flag to the value of the bit tested |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1698 //68K sets the zero flag to the complement of the bit tested |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1699 set_flag_cond(opts, CC_NC, FLAG_Z); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1700 if (inst->op != M68K_BTST) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1701 m68k_save_result(inst, opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1702 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1703 } |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1704 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1705 void translate_m68k_chk(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
1706 { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1707 code_info *code = &opts->gen.code; |
2225
e22137f0aca4
Fix some 68K exception processing cycle times
Michael Pavone <pavone@retrodev.com>
parents:
2224
diff
changeset
|
1708 cycles(&opts->gen, 4); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1709 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1710 cmp_ir(code, 0, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1711 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1712 cmp_irdisp(code, 0, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1713 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1714 uint32_t isize; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1715 switch(inst->src.addr_mode) |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1716 { |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1717 case MODE_AREG_DISPLACE: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1718 case MODE_AREG_INDEX_DISP8: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1719 case MODE_ABSOLUTE_SHORT: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1720 case MODE_PC_INDEX_DISP8: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1721 case MODE_PC_DISPLACE: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1722 case MODE_IMMEDIATE: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1723 isize = 4; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1724 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1725 case MODE_ABSOLUTE: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1726 isize = 6; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1727 break; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1728 default: |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1729 isize = 2; |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1730 } |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
1731 code_ptr passed; |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1732 ALLOC_CODE_RETRY_POINT |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
1733 passed = code->cur + 1; |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1734 jcc(code, CC_GE, code->cur + 2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1735 set_flag(opts, 1, FLAG_N); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1736 mov_ir(code, VECTOR_CHK, opts->gen.scratch2, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1737 mov_ir(code, inst->address+isize, opts->gen.scratch1, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1738 jmp(code, opts->trap); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1739 CHECK_BRANCH_DEST(passed); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1740 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1741 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1742 cmp_rr(code, src_op->base, dst_op->base, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1743 } else if(src_op->mode == MODE_REG_DISPLACE8) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1744 cmp_rdispr(code, src_op->base, src_op->disp, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1745 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1746 cmp_ir(code, src_op->disp, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1747 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1748 } else if(dst_op->mode == MODE_REG_DISPLACE8) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1749 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1750 cmp_rrdisp(code, src_op->base, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1751 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1752 cmp_irdisp(code, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
171 | 1753 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1754 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1755 passed = code->cur + 1; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1756 jcc(code, CC_LE, code->cur + 2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1757 set_flag(opts, 0, FLAG_N); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1758 mov_ir(code, VECTOR_CHK, opts->gen.scratch2, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1759 mov_ir(code, inst->address+isize, opts->gen.scratch1, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1760 jmp(code, opts->trap); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1761 CHECK_BRANCH_DEST(passed); |
2225
e22137f0aca4
Fix some 68K exception processing cycle times
Michael Pavone <pavone@retrodev.com>
parents:
2224
diff
changeset
|
1762 cycles(&opts->gen, 6); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1763 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1764 |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1765 static uint32_t divu(uint32_t dividend, m68k_context *context, uint32_t divisor_shift) |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1766 { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1767 uint16_t quotient = 0; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1768 uint8_t force = 0; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1769 uint16_t bit = 0; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1770 uint32_t cycles = 6; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1771 for (int i = 0; i < 16; i++) |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1772 { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1773 force = dividend >> 31; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1774 quotient = quotient << 1 | bit; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1775 dividend = dividend << 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1776 |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1777 if (force || dividend >= divisor_shift) { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1778 dividend -= divisor_shift; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1779 cycles += force ? 4 : 6; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1780 bit = 1; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1781 } else { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1782 bit = 0; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1783 cycles += 8; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1784 } |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1785 } |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1786 cycles += force ? 6 : bit ? 4 : 2; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1787 context->current_cycle += cycles * context->options->gen.clock_divider; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1788 quotient = quotient << 1 | bit; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1789 return dividend | quotient; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1790 } |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1791 |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1792 static uint32_t divs(uint32_t dividend, m68k_context *context, uint32_t divisor_shift) |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1793 { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1794 uint32_t orig_divisor = divisor_shift, orig_dividend = dividend; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1795 if (divisor_shift & 0x80000000) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1796 divisor_shift = 0 - divisor_shift; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1797 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1798 |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1799 uint32_t cycles = 12; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1800 if (dividend & 0x80000000) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1801 //dvs10 |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1802 dividend = 0 - dividend; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1803 cycles += 2; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1804 } |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1805 if (divisor_shift <= dividend) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1806 context->flags[FLAG_V] = 1; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1807 context->flags[FLAG_N] = 1; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1808 context->flags[FLAG_Z] = 0; |
2224
d8b0244101c4
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Michael Pavone <pavone@retrodev.com>
parents:
2103
diff
changeset
|
1809 cycles += 4; |
1284
82838d4c84d9
Minor fix to timing of "early" overflow case in divs when the dividend is negative
Michael Pavone <pavone@retrodev.com>
parents:
1282
diff
changeset
|
1810 context->current_cycle += cycles * context->options->gen.clock_divider; |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1811 return orig_dividend; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1812 } |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1813 uint16_t quotient = 0; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1814 uint16_t bit = 0; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1815 for (int i = 0; i < 15; i++) |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1816 { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1817 quotient = quotient << 1 | bit; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1818 dividend = dividend << 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1819 |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1820 if (dividend >= divisor_shift) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1821 dividend -= divisor_shift; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1822 cycles += 6; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1823 bit = 1; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1824 } else { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1825 bit = 0; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1826 cycles += 8; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1827 } |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1828 } |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1829 quotient = quotient << 1 | bit; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1830 dividend = dividend << 1; |
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Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1831 if (dividend >= divisor_shift) { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1832 dividend -= divisor_shift; |
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Michael Pavone <pavone@retrodev.com>
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1276
diff
changeset
|
1833 quotient = quotient << 1 | 1; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1834 } else { |
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Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1835 quotient = quotient << 1; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1836 } |
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Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1837 cycles += 4; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1838 |
1282
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|
1839 context->flags[FLAG_V] = 0; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1840 if (orig_divisor & 0x80000000) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1841 cycles += 16; //was 10 |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1842 if (orig_dividend & 0x80000000) { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1843 if (quotient & 0x8000) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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1276
diff
changeset
|
1844 context->flags[FLAG_V] = 1; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1845 context->flags[FLAG_N] = 1; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1846 context->flags[FLAG_Z] = 0; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1847 context->current_cycle += cycles * context->options->gen.clock_divider; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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1276
diff
changeset
|
1848 return orig_dividend; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1849 } else { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1850 dividend = -dividend; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1851 } |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1852 } else { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1853 quotient = -quotient; |
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Michael Pavone <pavone@retrodev.com>
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1276
diff
changeset
|
1854 if (quotient && !(quotient & 0x8000)) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1855 context->flags[FLAG_V] = 1; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1856 } |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1857 } |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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|
1858 } else if (orig_dividend & 0x80000000) { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1859 cycles += 18; // was 12 |
c5821f9de325
Cycle accurate implementation of divs
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changeset
|
1860 quotient = -quotient; |
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changeset
|
1861 if (quotient && !(quotient & 0x8000)) { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1862 context->flags[FLAG_V] = 1; |
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Cycle accurate implementation of divs
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diff
changeset
|
1863 } else { |
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Cycle accurate implementation of divs
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diff
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|
1864 dividend = -dividend; |
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Cycle accurate implementation of divs
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parents:
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diff
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|
1865 } |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1866 } else { |
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Cycle accurate implementation of divs
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parents:
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diff
changeset
|
1867 cycles += 14; //was 10 |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1868 if (quotient & 0x8000) { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1869 context->flags[FLAG_V] = 1; |
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Cycle accurate implementation of divs
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diff
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|
1870 } |
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Cycle accurate implementation of divs
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diff
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|
1871 } |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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changeset
|
1872 if (context->flags[FLAG_V]) { |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1873 context->flags[FLAG_N] = 1; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1874 context->flags[FLAG_Z] = 0; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1875 context->current_cycle += cycles * context->options->gen.clock_divider; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1876 return orig_dividend; |
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Cycle accurate implementation of divs
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diff
changeset
|
1877 } |
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Cycle accurate implementation of divs
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parents:
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diff
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|
1878 context->flags[FLAG_N] = (quotient & 0x8000) ? 1 : 0; |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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|
1879 context->flags[FLAG_Z] = quotient == 0; |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
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|
1880 //V was cleared above, C is cleared by the generated machine code |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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|
1881 context->current_cycle += cycles * context->options->gen.clock_divider; |
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Cycle accurate implementation of divs
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diff
changeset
|
1882 return dividend | quotient; |
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Cycle accurate implementation of divs
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parents:
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diff
changeset
|
1883 } |
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Cycle accurate implementation of divs
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diff
changeset
|
1884 |
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Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1885 void translate_m68k_div(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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1228
diff
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|
1886 { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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1228
diff
changeset
|
1887 code_info *code = &opts->gen.code; |
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Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1888 set_flag(opts, 0, FLAG_C); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
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|
1889 if (dst_op->mode == MODE_REG_DIRECT) { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1890 mov_rr(code, dst_op->base, opts->gen.scratch2, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1891 } else { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1892 mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch2, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1893 } |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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|
1894 if (src_op->mode == MODE_IMMED) { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
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|
1895 mov_ir(code, src_op->disp << 16, opts->gen.scratch1, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
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|
1896 } else { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1897 if (src_op->mode == MODE_REG_DISPLACE8) { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1898 movzx_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_W, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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changeset
|
1899 } else if (src_op->base != opts->gen.scratch1) { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
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|
1900 movzx_rr(code, src_op->base, opts->gen.scratch1, SZ_W, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1901 } |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1902 shl_ir(code, 16, opts->gen.scratch1, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1903 } |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1904 cmp_ir(code, 0, opts->gen.scratch1, SZ_D); |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
1905 code_ptr not_zero; |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1906 ALLOC_CODE_RETRY_POINT |
2269
6677afe78a6f
Hopefully make older versions of gcc happy
Michael Pavone <pavone@retrodev.com>
parents:
2268
diff
changeset
|
1907 not_zero = code->cur+1; |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1908 jcc(code, CC_NZ, not_zero); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1909 |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1910 //TODO: Check that opts->trap includes the cycles conumed by the first trap0 microinstruction |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1911 cycles(&opts->gen, 4); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1912 uint32_t isize = 2; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1913 switch(inst->src.addr_mode) |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1914 { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1915 case MODE_AREG_DISPLACE: |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1916 case MODE_AREG_INDEX_DISP8: |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1917 case MODE_ABSOLUTE_SHORT: |
1466
f2ee46d08b01
Push correct PC onto stack on divide by zero for pc-relative case
Michael Pavone <pavone@retrodev.com>
parents:
1465
diff
changeset
|
1918 case MODE_PC_DISPLACE: |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1919 case MODE_PC_INDEX_DISP8: |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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diff
changeset
|
1920 case MODE_IMMEDIATE: |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1921 isize = 4; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1922 break; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1923 case MODE_ABSOLUTE: |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1924 isize = 6; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1925 break; |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1926 } |
1276
2d8b9d40f5ea
Fix undefined flags on overflow and divide by zero for divu based on hardware test. Fix saving result of divu when destination is not stored in a host register
Michael Pavone <pavone@retrodev.com>
parents:
1274
diff
changeset
|
1927 //zero seems to clear all flags |
2d8b9d40f5ea
Fix undefined flags on overflow and divide by zero for divu based on hardware test. Fix saving result of divu when destination is not stored in a host register
Michael Pavone <pavone@retrodev.com>
parents:
1274
diff
changeset
|
1928 update_flags(opts, N0|Z0|V0); |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1929 mov_ir(code, VECTOR_INT_DIV_ZERO, opts->gen.scratch2, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
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diff
changeset
|
1930 mov_ir(code, inst->address+isize, opts->gen.scratch1, SZ_D); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
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parents:
1228
diff
changeset
|
1931 jmp(code, opts->trap); |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1932 CHECK_BRANCH_DEST(not_zero); |
1282
c5821f9de325
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diff
changeset
|
1933 code_ptr end = NULL; |
c5821f9de325
Cycle accurate implementation of divs
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1276
diff
changeset
|
1934 if (inst->op == M68K_DIVU) { |
c5821f9de325
Cycle accurate implementation of divs
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1276
diff
changeset
|
1935 //initial overflow check needs to be done in the C code for divs |
c5821f9de325
Cycle accurate implementation of divs
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1276
diff
changeset
|
1936 //but can be done before dumping state to mem in divu as an optimization |
c5821f9de325
Cycle accurate implementation of divs
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1276
diff
changeset
|
1937 cmp_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_D); |
c5821f9de325
Cycle accurate implementation of divs
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parents:
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diff
changeset
|
1938 code_ptr not_overflow = code->cur+1; |
c5821f9de325
Cycle accurate implementation of divs
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parents:
1276
diff
changeset
|
1939 jcc(code, CC_C, not_overflow); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1940 |
1282
c5821f9de325
Cycle accurate implementation of divs
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1276
diff
changeset
|
1941 //overflow seems to always set the N and clear Z |
c5821f9de325
Cycle accurate implementation of divs
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parents:
1276
diff
changeset
|
1942 update_flags(opts, N1|Z0|V1); |
c5821f9de325
Cycle accurate implementation of divs
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parents:
1276
diff
changeset
|
1943 cycles(&opts->gen, 10); |
c5821f9de325
Cycle accurate implementation of divs
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parents:
1276
diff
changeset
|
1944 end = code->cur+1; |
c5821f9de325
Cycle accurate implementation of divs
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parents:
1276
diff
changeset
|
1945 jmp(code, end); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1946 |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1947 CHECK_BRANCH_DEST(not_overflow); |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1948 } |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1949 call(code, opts->gen.save_context); |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1950 push_r(code, opts->gen.context_reg); |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1951 //TODO: inline the functionality of divudivs/ so we don't need to dump context to memory |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1952 call_args(code, (code_ptr)(inst->op == M68K_DIVU ? divu : divs), 3, opts->gen.scratch2, opts->gen.context_reg, opts->gen.scratch1); |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1953 pop_r(code, opts->gen.context_reg); |
1274
779920729249
Forgot to update flags in the "good" case of the new divu code
Michael Pavone <pavone@retrodev.com>
parents:
1262
diff
changeset
|
1954 mov_rr(code, RAX, opts->gen.scratch1, SZ_D); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1955 |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1956 call(code, opts->gen.load_context); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1957 |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1958 if (inst->op == M68K_DIVU) { |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1959 cmp_ir(code, 0, opts->gen.scratch1, SZ_W); |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1960 update_flags(opts, V0|Z|N); |
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1961 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
1962 |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1963 if (dst_op->mode == MODE_REG_DIRECT) { |
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1964 mov_rr(code, opts->gen.scratch1, dst_op->base, SZ_D); |
1274
779920729249
Forgot to update flags in the "good" case of the new divu code
Michael Pavone <pavone@retrodev.com>
parents:
1262
diff
changeset
|
1965 } else { |
1276
2d8b9d40f5ea
Fix undefined flags on overflow and divide by zero for divu based on hardware test. Fix saving result of divu when destination is not stored in a host register
Michael Pavone <pavone@retrodev.com>
parents:
1274
diff
changeset
|
1966 mov_rrdisp(code, opts->gen.scratch1, dst_op->base, dst_op->disp, SZ_D); |
1262
462d9770d467
Cycle accurate divu and undefined flags for overflow case
Michael Pavone <pavone@retrodev.com>
parents:
1228
diff
changeset
|
1967 } |
1282
c5821f9de325
Cycle accurate implementation of divs
Michael Pavone <pavone@retrodev.com>
parents:
1276
diff
changeset
|
1968 if (end) { |
2268
5b308c7b098c
Avoid code mem allocation bomb when a div instruction gets rewritten
Michael Pavone <pavone@retrodev.com>
parents:
2240
diff
changeset
|
1969 CHECK_BRANCH_DEST(end); |
611
744b305965f7
Fix divide by zero exception return address when div instruction is bigger than 1 word
Michael Pavone <pavone@retrodev.com>
parents:
610
diff
changeset
|
1970 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1971 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1972 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1973 void translate_m68k_exg(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1974 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1975 code_info *code = &opts->gen.code; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1976 cycles(&opts->gen, 6); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1977 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1978 mov_rr(code, dst_op->base, opts->gen.scratch2, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1979 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1980 mov_rr(code, src_op->base, dst_op->base, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1981 mov_rr(code, opts->gen.scratch2, src_op->base, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1982 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1983 mov_rdispr(code, src_op->base, src_op->disp, dst_op->base, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1984 mov_rrdisp(code, opts->gen.scratch2, src_op->base, src_op->disp, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1985 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1986 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1987 mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch2, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1988 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1989 mov_rrdisp(code, src_op->base, dst_op->base, dst_op->disp, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1990 mov_rr(code, opts->gen.scratch2, src_op->base, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1991 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1992 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1993 mov_rrdisp(code, opts->gen.scratch1, dst_op->base, dst_op->disp, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1994 mov_rrdisp(code, opts->gen.scratch2, src_op->base, src_op->disp, SZ_D); |
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1995 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1996 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
1997 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
1998 |
1216
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
1999 |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2000 |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2001 static uint32_t mulu_cycles(uint16_t value) |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2002 { |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2003 //4 for prefetch, 2-cycles per bit x 16, 2 for cleanup |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2004 uint32_t cycles = 38; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2005 uint16_t a = (value & 0b1010101010101010) >> 1; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2006 uint16_t b = value & 0b0101010101010101; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2007 value = a + b; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2008 a = (value & 0b1100110011001100) >> 2; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2009 b = value & 0b0011001100110011; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2010 value = a + b; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2011 a = (value & 0b1111000011110000) >> 4; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2012 b = value & 0b0000111100001111; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2013 value = a + b; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2014 a = (value & 0b1111111100000000) >> 8; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2015 b = value & 0b0000000011111111; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2016 value = a + b; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2017 return cycles + 2*value; |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2018 } |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2019 |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2020 static uint32_t muls_cycles(uint16_t value) |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2021 { |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2022 //muls timing is essentially the same as muls, but it's based on the number of 0/1 |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2023 //transitions rather than the number of 1 bits. xoring the value with itself shifted |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2024 //by one effectively sets one bit for every transition |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2025 return mulu_cycles((value << 1) ^ value); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2026 } |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2027 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2028 void translate_m68k_mul(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2029 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2030 code_info *code = &opts->gen.code; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2031 if (src_op->mode == MODE_IMMED) { |
1216
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2032 cycles(&opts->gen, inst->op == M68K_MULU ? mulu_cycles(src_op->disp) : muls_cycles(src_op->disp)); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2033 mov_ir(code, inst->op == M68K_MULU ? (src_op->disp & 0xFFFF) : ((src_op->disp & 0x8000) ? src_op->disp | 0xFFFF0000 : src_op->disp), opts->gen.scratch1, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2034 } else if (src_op->mode == MODE_REG_DIRECT) { |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2035 if (inst->op == M68K_MULS) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2036 movsx_rr(code, src_op->base, opts->gen.scratch1, SZ_W, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2037 } else { |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2038 movzx_rr(code, src_op->base, opts->gen.scratch1, SZ_W, SZ_D); |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2039 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2040 } else { |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2041 if (inst->op == M68K_MULS) { |
682 | 2042 movsx_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_W, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2043 } else { |
682 | 2044 movzx_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_W, SZ_D); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2045 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2046 } |
1216
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2047 if (src_op->mode != MODE_IMMED) { |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2048 //TODO: Inline cycle calculation so we don't need to save/restore a bunch of registers |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2049 //save context to memory and call the relevant C function for calculating the cycle count |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2050 call(code, opts->gen.save_context); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2051 push_r(code, opts->gen.scratch1); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2052 push_r(code, opts->gen.context_reg); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2053 call_args(code, (code_ptr)(inst->op == M68K_MULS ? muls_cycles : mulu_cycles), 1, opts->gen.scratch1); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2054 pop_r(code, opts->gen.context_reg); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2055 //turn 68K cycles into master clock cycles and add to the current cycle count |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2056 imul_irr(code, opts->gen.clock_divider, RAX, RAX, SZ_D); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2057 add_rrdisp(code, RAX, opts->gen.context_reg, offsetof(m68k_context, current_cycle), SZ_D); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2058 //restore context and scratch1 |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2059 call(code, opts->gen.load_context); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2060 pop_r(code, opts->gen.scratch1); |
0649cd8ca097
Cycle accurate MULU/MULS emulation
Michael Pavone <pavone@retrodev.com>
parents:
1192
diff
changeset
|
2061 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2062 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2063 uint8_t dst_reg; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2064 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2065 dst_reg = dst_op->base; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2066 if (inst->op == M68K_MULS) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2067 movsx_rr(code, dst_reg, dst_reg, SZ_W, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2068 } else { |
682 | 2069 movzx_rr(code, dst_reg, dst_reg, SZ_W, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2070 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2071 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2072 dst_reg = opts->gen.scratch2; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2073 if (inst->op == M68K_MULS) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2074 movsx_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch2, SZ_W, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2075 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2076 movzx_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch2, SZ_W, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2077 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2078 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2079 imul_rr(code, opts->gen.scratch1, dst_reg, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2080 if (dst_op->mode == MODE_REG_DISPLACE8) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2081 mov_rrdisp(code, dst_reg, dst_op->base, dst_op->disp, SZ_D); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2082 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2083 cmp_ir(code, 0, dst_reg, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2084 update_flags(opts, N|Z|V0|C0); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2085 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2086 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2087 void translate_m68k_negx(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2088 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2089 code_info *code = &opts->gen.code; |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
2090 cycles(&opts->gen, inst->extra.size == OPSIZE_LONG && inst->dst.addr_mode == MODE_REG ? BUS+2 : BUS); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2091 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2092 if (dst_op->base == opts->gen.scratch1) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2093 push_r(code, opts->gen.scratch2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2094 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2095 flag_to_carry(opts, FLAG_X); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2096 sbb_rr(code, dst_op->base, opts->gen.scratch2, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2097 mov_rr(code, opts->gen.scratch2, dst_op->base, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2098 pop_r(code, opts->gen.scratch2); |
173 | 2099 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2100 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, inst->extra.size); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2101 flag_to_carry(opts, FLAG_X); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2102 sbb_rr(code, dst_op->base, opts->gen.scratch1, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2103 mov_rr(code, opts->gen.scratch1, dst_op->base, inst->extra.size); |
106 | 2104 } |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2105 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2106 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2107 flag_to_carry(opts, FLAG_X); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2108 sbb_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch1, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2109 mov_rrdisp(code, opts->gen.scratch1, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2110 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2111 set_flag_cond(opts, CC_C, FLAG_C); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2112 code_ptr after_flag_set = code->cur + 1; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2113 jcc(code, CC_Z, code->cur + 2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2114 set_flag(opts, 0, FLAG_Z); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2115 *after_flag_set = code->cur - (after_flag_set+1); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2116 set_flag_cond(opts, CC_S, FLAG_N); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2117 set_flag_cond(opts, CC_O, FLAG_V); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2118 if (opts->flag_regs[FLAG_C] >= 0) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2119 flag_to_flag(opts, FLAG_C, FLAG_X); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2120 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2121 set_flag_cond(opts, CC_C, FLAG_X); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2122 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2123 m68k_save_result(inst, opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2124 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2125 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2126 void translate_m68k_rot(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2127 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2128 code_info *code = &opts->gen.code; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2129 int32_t init_flags = C|V0; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2130 if (inst->src.addr_mode == MODE_UNUSED) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2131 cycles(&opts->gen, BUS); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2132 //Memory rotate |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2133 if (inst->op == M68K_ROXR || inst->op == M68K_ROXL) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2134 flag_to_carry(opts, FLAG_X); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2135 init_flags |= X; |
106 | 2136 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2137 op_ir(code, inst, 1, dst_op->base, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2138 update_flags(opts, init_flags); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2139 cmp_ir(code, 0, dst_op->base, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2140 update_flags(opts, Z|N); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2141 m68k_save_result(inst, opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2142 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2143 if (src_op->mode == MODE_IMMED) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2144 cycles(&opts->gen, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op->disp*2); |
577
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
2145 if (inst->op == M68K_ROXR || inst->op == M68K_ROXL) { |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
2146 flag_to_carry(opts, FLAG_X); |
0f367276a80c
Refactor a bunch of the arithmetic instructions in the 68K core to reduce duplicate code
Michael Pavone <pavone@retrodev.com>
parents:
576
diff
changeset
|
2147 init_flags |= X; |
122 | 2148 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2149 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2150 op_ir(code, inst, src_op->disp, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2151 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2152 op_irdisp(code, inst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2153 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2154 update_flags(opts, init_flags); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2155 } else { |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
2156 cycles(&opts->gen, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2157 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2158 if (src_op->base != opts->gen.scratch1) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2159 mov_rr(code, src_op->base, opts->gen.scratch1, SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2160 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2161 } else { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2162 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2163 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2164 and_ir(code, 63, opts->gen.scratch1, SZ_D); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2165 code_ptr zero_off = code->cur + 1; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2166 jcc(code, CC_Z, code->cur + 2); |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2167 //add 2 cycles for every bit shifted |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2168 mov_ir(code, 2 * opts->gen.clock_divider, opts->gen.scratch2, SZ_D); |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2169 imul_rr(code, RCX, opts->gen.scratch2, SZ_D); |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2170 add_rr(code, opts->gen.scratch2, opts->gen.cycles, SZ_D); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2171 cmp_ir(code, 32, opts->gen.scratch1, SZ_B); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2172 code_ptr norm_off = code->cur + 1; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2173 jcc(code, CC_L, code->cur + 2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2174 if (inst->op == M68K_ROXR || inst->op == M68K_ROXL) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2175 flag_to_carry(opts, FLAG_X); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2176 init_flags |= X; |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2177 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2178 sub_ir(code, 32, opts->gen.scratch1, SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2179 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2180 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2181 op_ir(code, inst, 31, dst_op->base, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2182 op_ir(code, inst, 1, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2183 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2184 op_irdisp(code, inst, 31, dst_op->base, dst_op->disp, inst->extra.size); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2185 op_irdisp(code, inst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2186 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2187 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2188 if (inst->op == M68K_ROXR || inst->op == M68K_ROXL) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2189 set_flag_cond(opts, CC_C, FLAG_X); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2190 sub_ir(code, 32, opts->gen.scratch1, SZ_B); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2191 *norm_off = code->cur - (norm_off+1); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2192 flag_to_carry(opts, FLAG_X); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2193 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2194 *norm_off = code->cur - (norm_off+1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2195 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2196 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2197 op_r(code, inst, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2198 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2199 op_rdisp(code, inst, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2200 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2201 update_flags(opts, init_flags); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2202 code_ptr end_off = code->cur + 1; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2203 jmp(code, code->cur + 2); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2204 *zero_off = code->cur - (zero_off+1); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2205 if (inst->op == M68K_ROXR || inst->op == M68K_ROXL) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2206 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2207 flag_to_flag(opts, FLAG_X, FLAG_C); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2208 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2209 set_flag(opts, 0, FLAG_C); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2210 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2211 *end_off = code->cur - (end_off+1); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2212 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2213 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2214 cmp_ir(code, 0, dst_op->base, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2215 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2216 cmp_irdisp(code, 0, dst_op->base, dst_op->disp, inst->extra.size); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2217 } |
682 | 2218 update_flags(opts, Z|N); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2219 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2220 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2221 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2222 #define BIT_SUPERVISOR 5 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2223 |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2224 void m68k_trap_if_not_supervisor(m68k_options *opts, m68kinst *inst) |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2225 { |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2226 code_info *code = &opts->gen.code; |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2227 //check supervisor bit in SR and trap if not in supervisor mode |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2228 bt_irdisp(code, BIT_SUPERVISOR, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2229 code_ptr in_sup_mode = code->cur + 1; |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2230 jcc(code, CC_C, code->cur + 2); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2231 |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2232 ldi_native(opts, VECTOR_PRIV_VIOLATION, opts->gen.scratch2); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2233 ldi_native(opts, inst->address, opts->gen.scratch1); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2234 jmp(code, opts->trap); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2235 |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2236 *in_sup_mode = code->cur - (in_sup_mode + 1); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2237 } |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2238 |
584
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2239 void translate_m68k_andi_ori_ccr_sr(m68k_options *opts, m68kinst *inst) |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2240 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2241 code_info *code = &opts->gen.code; |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2242 if (inst->op == M68K_ANDI_SR || inst->op == M68K_ORI_SR) { |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2243 m68k_trap_if_not_supervisor(opts, inst); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2244 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2245 cycles(&opts->gen, 20); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2246 uint32_t flag_mask = 0; |
584
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2247 uint32_t base_flag = inst->op == M68K_ANDI_SR || inst->op == M68K_ANDI_CCR ? X0 : X1; |
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2248 for (int i = 0; i < 5; i++) |
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2249 { |
757
483f7e7926a6
More clang warning cleanup
Michael Pavone <pavone@retrodev.com>
parents:
751
diff
changeset
|
2250 if ((base_flag == X0) ^ ((inst->src.params.immed & 1 << i) > 0)) |
584
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2251 { |
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2252 flag_mask |= base_flag << ((4 - i) * 3); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2253 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2254 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2255 update_flags(opts, flag_mask); |
584
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2256 if (inst->op == M68K_ANDI_SR || inst->op == M68K_ORI_SR) { |
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2257 if (inst->op == M68K_ANDI_SR) { |
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2258 and_irdisp(code, inst->src.params.immed >> 8, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2259 } else { |
584
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2260 or_irdisp(code, inst->src.params.immed >> 8, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2261 } |
605
49d9928353be
Fix a bug in ori to SR that was swapping USP and SSP inappropriately
Michael Pavone <pavone@retrodev.com>
parents:
601
diff
changeset
|
2262 if (inst->op == M68K_ANDI_SR && !(inst->src.params.immed & (1 << (BIT_SUPERVISOR + 8)))) { |
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
2263 //leave supervisor mode |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
2264 swap_ssp_usp(opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2265 } |
584
b6713c1b6f55
Combine andi ccr/sr and ori ccr/sr.
Michael Pavone <pavone@retrodev.com>
parents:
583
diff
changeset
|
2266 if ((inst->op == M68K_ANDI_SR && (inst->src.params.immed & 0x700) != 0x700) |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
2267 || (inst->op == M68K_ORI_SR && inst->src.params.immed & 0x8700)) { |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2268 if (inst->op == M68K_ANDI_SR) { |
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2269 //set int pending flag in case we trigger an interrupt as a result of the mask change |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
2270 mov_irdisp(code, INT_PENDING_SR_CHANGE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2271 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2272 call(code, opts->do_sync); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2273 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2274 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2275 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2276 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2277 void translate_m68k_eori_ccr_sr(m68k_options *opts, m68kinst *inst) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2278 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2279 code_info *code = &opts->gen.code; |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2280 if (inst->op == M68K_EORI_SR) { |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2281 m68k_trap_if_not_supervisor(opts, inst); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2282 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2283 cycles(&opts->gen, 20); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2284 if (inst->src.params.immed & 0x1) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2285 xor_flag(opts, 1, FLAG_C); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2286 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2287 if (inst->src.params.immed & 0x2) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2288 xor_flag(opts, 1, FLAG_V); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2289 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2290 if (inst->src.params.immed & 0x4) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2291 xor_flag(opts, 1, FLAG_Z); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2292 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2293 if (inst->src.params.immed & 0x8) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2294 xor_flag(opts, 1, FLAG_N); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2295 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2296 if (inst->src.params.immed & 0x10) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2297 xor_flag(opts, 1, FLAG_X); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2298 } |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2299 if (inst->op == M68K_EORI_SR) { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2300 xor_irdisp(code, inst->src.params.immed >> 8, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
1304
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
2301 if (inst->src.params.immed & 0x8700) { |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2302 //set int pending flag in case we trigger an interrupt as a result of the mask change |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
2303 mov_irdisp(code, INT_PENDING_SR_CHANGE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2304 call(code, opts->do_sync); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2305 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2306 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2307 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2308 |
586
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2309 void set_all_flags(m68k_options *opts, uint8_t flags) |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2310 { |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2311 uint32_t flag_mask = flags & 0x10 ? X1 : X0; |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2312 flag_mask |= flags & 0x8 ? N1 : N0; |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2313 flag_mask |= flags & 0x4 ? Z1 : Z0; |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2314 flag_mask |= flags & 0x2 ? V1 : V0; |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2315 flag_mask |= flags & 0x1 ? C1 : C0; |
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2316 update_flags(opts, flag_mask); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2317 } |
586
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2318 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2319 void translate_m68k_move_ccr_sr(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2320 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2321 code_info *code = &opts->gen.code; |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2322 if (inst->op == M68K_MOVE_SR) { |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2323 m68k_trap_if_not_supervisor(opts, inst); |
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2324 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2325 if (src_op->mode == MODE_IMMED) { |
586
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2326 set_all_flags(opts, src_op->disp); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2327 if (inst->op == M68K_MOVE_SR) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2328 mov_irdisp(code, (src_op->disp >> 8), opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2329 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2330 //leave supervisor mode |
585
82aadd5d103a
Use swap_ssp_usp in translate_m68k_move_ccr_sr
Michael Pavone <pavone@retrodev.com>
parents:
584
diff
changeset
|
2331 swap_ssp_usp(opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2332 } |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2333 if (((src_op->disp >> 8) & 7) < 7) { |
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2334 //set int pending flag in case we trigger an interrupt as a result of the mask change |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
2335 mov_irdisp(code, INT_PENDING_SR_CHANGE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2336 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2337 call(code, opts->do_sync); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2338 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2339 cycles(&opts->gen, 12); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2340 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2341 if (src_op->base != opts->gen.scratch1) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2342 if (src_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2343 mov_rr(code, src_op->base, opts->gen.scratch1, SZ_W); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2344 } else { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2345 mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch1, SZ_W); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2346 } |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2347 } |
698
0a86e81fa87d
Fixed a missed call to do_sync when updating SR in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
690
diff
changeset
|
2348 if (inst->op == M68K_MOVE_SR) { |
0a86e81fa87d
Fixed a missed call to do_sync when updating SR in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
690
diff
changeset
|
2349 call(code, opts->set_sr); |
0a86e81fa87d
Fixed a missed call to do_sync when updating SR in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
690
diff
changeset
|
2350 call(code, opts->do_sync); |
0a86e81fa87d
Fixed a missed call to do_sync when updating SR in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
690
diff
changeset
|
2351 } else { |
0a86e81fa87d
Fixed a missed call to do_sync when updating SR in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
690
diff
changeset
|
2352 call(code, opts->set_ccr); |
0a86e81fa87d
Fixed a missed call to do_sync when updating SR in 68K core
Michael Pavone <pavone@retrodev.com>
parents:
690
diff
changeset
|
2353 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2354 cycles(&opts->gen, 12); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2355 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2356 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2357 |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2358 void translate_m68k_stop(m68k_options *opts, m68kinst *inst) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2359 { |
990
33a46d35b913
Implement privelege violation exceptions
Michael Pavone <pavone@retrodev.com>
parents:
989
diff
changeset
|
2360 m68k_trap_if_not_supervisor(opts, inst); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2361 //manual says 4 cycles, but it has to be at least 8 since it's a 2-word instruction |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2362 //possibly even 12 since that's how long MOVE to SR takes |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2363 //On further thought prefetch + the fact that this stops the CPU may make |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2364 //Motorola's accounting make sense here |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2365 code_info *code = &opts->gen.code; |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2366 cycles(&opts->gen, BUS*2); |
586
aa35ccb90aa9
Minor refactor to translate_m68k_move_ccr_sr and translate_m68k_stop to reduce code duplication
Michael Pavone <pavone@retrodev.com>
parents:
585
diff
changeset
|
2367 set_all_flags(opts, inst->src.params.immed); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2368 mov_irdisp(code, (inst->src.params.immed >> 8), opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2369 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2370 //leave supervisor mode |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2371 swap_ssp_usp(opts); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2372 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2373 code_ptr loop_top = code->cur; |
985
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2374 call(code, opts->do_sync); |
1510
5eb954b76e65
Fix silly bug in STOP implementation that caused excessive CPU usage
Michael Pavone <pavone@retrodev.com>
parents:
1466
diff
changeset
|
2375 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D); |
985
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2376 code_ptr normal_cycle_up = code->cur + 1; |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2377 jcc(code, CC_A, code->cur + 2); |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2378 cycles(&opts->gen, BUS); |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2379 code_ptr after_cycle_up = code->cur + 1; |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2380 jmp(code, code->cur + 2); |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2381 *normal_cycle_up = code->cur - (normal_cycle_up + 1); |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2382 mov_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D); |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2383 *after_cycle_up = code->cur - (after_cycle_up+1); |
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2384 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_cycle), opts->gen.cycles, SZ_D); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2385 jcc(code, CC_C, loop_top); |
985
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2386 //set int pending flag so interrupt fires immediately after stop is done |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
2387 mov_irdisp(code, INT_PENDING_SR_CHANGE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2388 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2389 |
839 | 2390 void translate_m68k_trapv(m68k_options *opts, m68kinst *inst) |
2391 { | |
2392 code_info *code = &opts->gen.code; | |
2393 flag_to_carry(opts, FLAG_V); | |
2394 code_ptr no_trap = code->cur + 1; | |
2395 jcc(code, CC_NC, no_trap); | |
2396 ldi_native(opts, VECTOR_TRAPV, opts->gen.scratch2); | |
2397 ldi_native(opts, inst->address+2, opts->gen.scratch1); | |
2398 jmp(code, opts->trap); | |
2399 *no_trap = code->cur - (no_trap + 1); | |
2226
d15c68157288
Fix implementation ot 68K trapv instruction
Michael Pavone <pavone@retrodev.com>
parents:
2225
diff
changeset
|
2400 cycles(&opts->gen, BUS); |
839 | 2401 } |
2402 | |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2403 void translate_m68k_odd(m68k_options *opts, m68kinst *inst) |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2404 { |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2405 code_info *code = &opts->gen.code; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2406 //swap USP and SSP if not already in supervisor mode |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2407 check_user_mode_swap_ssp_usp(opts); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2408 //save PC |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2409 subi_areg(opts, 4, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2410 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2411 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, last_prefetch_address), opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2412 call(code, opts->write_32_lowfirst); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2413 //save status register |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2414 subi_areg(opts, 2, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2415 call(code, opts->get_sr); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2416 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2417 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2418 //save instruction register |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2419 subi_areg(opts, 2, 7); |
989
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2420 //calculate IR |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2421 push_r(code, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2422 call(code, opts->gen.save_context); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2423 call_args_abi(code, (code_ptr)m68k_get_ir, 1, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2424 mov_rr(code, RAX, opts->gen.scratch1, SZ_W); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2425 pop_r(code, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2426 push_r(code, RAX); //save it for use in the "info" word |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2427 call(code, opts->gen.load_context); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2428 //write it to the stack |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2429 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2430 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2431 //save access address |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2432 subi_areg(opts, 4, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2433 mov_ir(code, inst->address, opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2434 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2435 call(code, opts->write_32_lowfirst); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2436 //save FC, I/N and R/W word' |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2437 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_W); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2438 //FC3 is basically the same as the supervisor bit |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2439 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2440 shr_ir(code, 3, opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2441 and_ir(code, 4, opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2442 //set FC1 to one to indicate instruction fetch, and R/W to indicate read |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2443 or_ir(code, 0x12, opts->gen.scratch1, SZ_B); |
989
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2444 //set undefined bits to IR value |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2445 pop_r(code, opts->gen.scratch2); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2446 and_ir(code, 0xFFE0, opts->gen.scratch2, SZ_W); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2447 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2448 subi_areg(opts, 2, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2449 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2450 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2451 //set supervisor bit |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2452 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2453 //load vector address |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2454 mov_ir(code, 4 * VECTOR_ADDRESS_ERROR, opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2455 call(code, opts->read_32); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2456 call(code, opts->native_addr_and_sync); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2457 cycles(&opts->gen, 18); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2458 jmp_r(code, opts->gen.scratch1); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2459 } |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2460 |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2461 void translate_m68k_move_from_sr(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2462 { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2463 code_info *code = &opts->gen.code; |
1989
0d87116630c7
Fix cycle timing of a number of 68K instructions
Michael Pavone <pavone@retrodev.com>
parents:
1942
diff
changeset
|
2464 cycles(&opts->gen, inst->dst.addr_mode == MODE_REG ? BUS+2 : BUS); |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2465 call(code, opts->get_sr); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2466 if (dst_op->mode == MODE_REG_DIRECT) { |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2467 mov_rr(code, opts->gen.scratch1, dst_op->base, SZ_W); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2468 } else { |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2469 mov_rrdisp(code, opts->gen.scratch1, dst_op->base, dst_op->disp, SZ_W); |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2470 } |
582
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2471 m68k_save_result(inst, opts); |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2472 } |
c05fcbfe1b1a
Refactored translate_m68k so that it contains no host-cpu specific code and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
581
diff
changeset
|
2473 |
1082
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2474 void m68k_out_of_bounds_execution(uint32_t address) |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2475 { |
1082
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2476 fatal_error("M68K attempted to execute code at unmapped or I/O address %X\n", address); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2477 } |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2478 |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2479 void translate_out_of_bounds(m68k_options *opts, uint32_t address) |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2480 { |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2481 code_info *code = &opts->gen.code; |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2482 check_cycles_int(&opts->gen, address); |
1082
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2483 mov_ir(code, address, opts->gen.scratch1, SZ_D); |
2ec5e6eaf81d
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Michael Pavone <pavone@retrodev.com>
parents:
1026
diff
changeset
|
2484 call_args(code, (code_ptr)m68k_out_of_bounds_execution, 1, opts->gen.scratch1); |
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2485 } |
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2486 |
981
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
979
diff
changeset
|
2487 void m68k_set_last_prefetch(m68k_options *opts, uint32_t address) |
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
979
diff
changeset
|
2488 { |
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
979
diff
changeset
|
2489 mov_irdisp(&opts->gen.code, address, opts->gen.context_reg, offsetof(m68k_context, last_prefetch_address), SZ_D); |
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
979
diff
changeset
|
2490 } |
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
979
diff
changeset
|
2491 |
587
55c5b0f913ce
Made m68k_retranslate_inst host-cpu generic and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
586
diff
changeset
|
2492 void nop_fill_or_jmp_next(code_info *code, code_ptr old_end, code_ptr next_inst) |
55c5b0f913ce
Made m68k_retranslate_inst host-cpu generic and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
586
diff
changeset
|
2493 { |
55c5b0f913ce
Made m68k_retranslate_inst host-cpu generic and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
586
diff
changeset
|
2494 if (next_inst == old_end && next_inst - code->cur < 2) { |
55c5b0f913ce
Made m68k_retranslate_inst host-cpu generic and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
586
diff
changeset
|
2495 while (code->cur < old_end) { |
55c5b0f913ce
Made m68k_retranslate_inst host-cpu generic and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
586
diff
changeset
|
2496 *(code->cur++) = 0x90; //NOP |
686
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2497 } |
8cb61671777b
Fix indentation that presumably got messed up in a merge
Michael Pavone <pavone@retrodev.com>
parents:
682
diff
changeset
|
2498 } else { |
587
55c5b0f913ce
Made m68k_retranslate_inst host-cpu generic and moved it to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
586
diff
changeset
|
2499 jmp(code, next_inst); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2500 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2501 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2502 |
1192
e0fc8967d380
Inefficient fix for overlapping instruction problem that was causing issues with Outrunners
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
2503 #define M68K_MAX_INST_SIZE (2*(1+2+2)) |
e0fc8967d380
Inefficient fix for overlapping instruction problem that was causing issues with Outrunners
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
2504 |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2505 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2506 { |
985
751280fb4494
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2507 m68k_options * options = context->options; |
1130
8f14767661fa
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
1111
diff
changeset
|
2508 uint32_t inst_start = get_instruction_start(options, address); |
1192
e0fc8967d380
Inefficient fix for overlapping instruction problem that was causing issues with Outrunners
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
2509 while (inst_start && (address - inst_start) < M68K_MAX_INST_SIZE) { |
726
7367b14ac01c
Don't attempt to translate or map code at odd addresses. This fixes a bug that shows up when playing College Footbal USA 96
Michael Pavone <pavone@retrodev.com>
parents:
698
diff
changeset
|
2510 code_ptr dst = get_native_address(context->options, inst_start); |
1465
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1461
diff
changeset
|
2511 patch_for_retranslate(&options->gen, dst, options->retrans_stub); |
1192
e0fc8967d380
Inefficient fix for overlapping instruction problem that was causing issues with Outrunners
Michael Pavone <pavone@retrodev.com>
parents:
1130
diff
changeset
|
2512 inst_start = get_instruction_start(options, inst_start - 2); |
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2513 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2514 return context; |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2515 } |
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
2516 |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2517 void m68k_invalidate_code_range(m68k_context *context, uint32_t start, uint32_t end) |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2518 { |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2519 m68k_options *opts = context->options; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2520 native_map_slot *native_code_map = opts->gen.native_code_map; |
2103
522d04e2adcd
Fix regression in booting games with Japanese Mega CD BIOS
Michael Pavone <pavone@retrodev.com>
parents:
2101
diff
changeset
|
2521 if (start > M68K_MAX_INST_SIZE - 2) { |
522d04e2adcd
Fix regression in booting games with Japanese Mega CD BIOS
Michael Pavone <pavone@retrodev.com>
parents:
2101
diff
changeset
|
2522 start -= M68K_MAX_INST_SIZE - 2; |
522d04e2adcd
Fix regression in booting games with Japanese Mega CD BIOS
Michael Pavone <pavone@retrodev.com>
parents:
2101
diff
changeset
|
2523 } else { |
522d04e2adcd
Fix regression in booting games with Japanese Mega CD BIOS
Michael Pavone <pavone@retrodev.com>
parents:
2101
diff
changeset
|
2524 start = 0; |
522d04e2adcd
Fix regression in booting games with Japanese Mega CD BIOS
Michael Pavone <pavone@retrodev.com>
parents:
2101
diff
changeset
|
2525 } |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2526 memmap_chunk const *mem_chunk = find_map_chunk(start, &opts->gen, 0, NULL); |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2527 if (mem_chunk) { |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2528 //calculate the lowest alias for this address |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2529 start = mem_chunk->start + ((start - mem_chunk->start) & mem_chunk->mask); |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2530 } |
2279
3b5fef896475
Fix edge case in m68k_invalidate_code_range that caused problems when loading save states
Michael Pavone <pavone@retrodev.com>
parents:
2269
diff
changeset
|
2531 mem_chunk = find_map_chunk(end - 1, &opts->gen, 0, NULL); |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2532 if (mem_chunk) { |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2533 //calculate the lowest alias for this address |
2279
3b5fef896475
Fix edge case in m68k_invalidate_code_range that caused problems when loading save states
Michael Pavone <pavone@retrodev.com>
parents:
2269
diff
changeset
|
2534 end = mem_chunk->start + ((end - 1 - mem_chunk->start) & mem_chunk->mask) + 1; |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2535 } |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2536 uint32_t start_chunk = start / NATIVE_CHUNK_SIZE, end_chunk = end / NATIVE_CHUNK_SIZE; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2537 for (uint32_t chunk = start_chunk; chunk <= end_chunk; chunk++) |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2538 { |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2539 if (native_code_map[chunk].base) { |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2540 uint32_t start_offset = chunk == start_chunk ? start % NATIVE_CHUNK_SIZE : 0; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2541 uint32_t end_offset = chunk == end_chunk ? end % NATIVE_CHUNK_SIZE : NATIVE_CHUNK_SIZE; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2542 for (uint32_t offset = start_offset; offset < end_offset; offset++) |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2543 { |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2544 if (native_code_map[chunk].offsets[offset] != INVALID_OFFSET && native_code_map[chunk].offsets[offset] != EXTENSION_WORD) { |
1465
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1461
diff
changeset
|
2545 patch_for_retranslate(&opts->gen, native_code_map[chunk].base + native_code_map[chunk].offsets[offset], opts->retrans_stub); |
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1461
diff
changeset
|
2546 /*code_info code; |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2547 code.cur = native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2548 code.last = code.cur + 32; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2549 code.stack_off = 0; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2550 mov_ir(&code, chunk * NATIVE_CHUNK_SIZE + offset, opts->gen.scratch2, SZ_D); |
1465
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1461
diff
changeset
|
2551 jmp(&code, opts->retrans_stub);*/ |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2552 } |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2553 } |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2554 } |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2555 } |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2556 } |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
2557 |
1329
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2558 void m68k_breakpoint_patch(m68k_context *context, uint32_t address, m68k_debug_handler bp_handler, code_ptr native_addr) |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2559 { |
569
9b7fcf748be0
Rename x86_68k_options and m68k_to_x86.h to m68k_options and m68k_core.h respectively
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
2560 m68k_options * opts = context->options; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2561 code_info native; |
1329
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2562 native.cur = native_addr ? native_addr : get_native_address(context->options, address); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2563 |
1329
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2564 if (!native.cur) { |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2565 return; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2566 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2567 |
1329
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2568 if (*native.cur != opts->prologue_start) { |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2569 //instruction has already been patched, probably for retranslation |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2570 return; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2571 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2572 native.last = native.cur + 128; |
908
20e30ca7e8a2
Fix problem in 68K debugger caused by stack alignment change
Michael Pavone <pavone@retrodev.com>
parents:
902
diff
changeset
|
2573 native.stack_off = 0; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2574 code_ptr start_native = native.cur; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2575 mov_ir(&native, address, opts->gen.scratch1, SZ_D); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2576 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2577 |
1329
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
2578 call(&native, opts->bp_stub); |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2579 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2580 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2581 void init_m68k_opts(m68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun sync_components) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2582 { |
440 | 2583 memset(opts, 0, sizeof(*opts)); |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
2584 opts->gen.memmap = memmap; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
2585 opts->gen.memmap_chunks = num_chunks; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
588
diff
changeset
|
2586 opts->gen.address_size = SZ_D; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
588
diff
changeset
|
2587 opts->gen.address_mask = 0xFFFFFF; |
596
9853bcce4729
Set the byte_swap flag in the M68K core so gen_mem_fun correctly inserts xor instructions for byte access functions
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2588 opts->gen.byte_swap = 1; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
588
diff
changeset
|
2589 opts->gen.max_address = 0x1000000; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
588
diff
changeset
|
2590 opts->gen.bus_cycles = BUS; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2591 opts->gen.clock_divider = clock_divider; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
588
diff
changeset
|
2592 opts->gen.mem_ptr_off = offsetof(m68k_context, mem_pointers); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
588
diff
changeset
|
2593 opts->gen.ram_flags_off = offsetof(m68k_context, ram_code_flags); |
620
9d6fed6501ba
Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents:
612
diff
changeset
|
2594 opts->gen.ram_flags_shift = 11; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2595 for (int i = 0; i < 8; i++) |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2596 { |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2597 opts->dregs[i] = opts->aregs[i] = -1; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2598 } |
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2599 #ifdef X86_64 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2600 opts->dregs[0] = R10; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2601 opts->dregs[1] = R11; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2602 opts->dregs[2] = R12; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
2603 opts->dregs[3] = R8; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2604 opts->aregs[0] = R13; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2605 opts->aregs[1] = R14; |
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
2606 opts->aregs[2] = R9; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2607 opts->aregs[7] = R15; |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2608 |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2609 opts->flag_regs[0] = -1; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2610 opts->flag_regs[1] = RBX; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2611 opts->flag_regs[2] = RDX; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2612 opts->flag_regs[3] = BH; |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2613 opts->flag_regs[4] = DH; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2614 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2615 opts->gen.scratch2 = RDI; |
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2616 #else |
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2617 opts->dregs[0] = RDX; |
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2618 opts->aregs[7] = RDI; |
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2619 |
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2620 for (int i = 0; i < 5; i++) |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2621 { |
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2622 opts->flag_regs[i] = -1; |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2623 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2624 opts->gen.scratch2 = RBX; |
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2625 #endif |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2626 opts->gen.context_reg = RSI; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2627 opts->gen.cycles = RAX; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2628 opts->gen.limit = RBP; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2629 opts->gen.scratch1 = RCX; |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2630 opts->gen.align_error_mask = 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2631 opts->sync_components = sync_components; |
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2632 |
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2633 |
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2634 opts->gen.native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2635 memset(opts->gen.native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2636 opts->gen.deferred = NULL; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
689
diff
changeset
|
2637 |
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
689
diff
changeset
|
2638 uint32_t inst_size_size = sizeof(uint8_t *) * ram_size(&opts->gen) / 1024; |
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
689
diff
changeset
|
2639 opts->gen.ram_inst_sizes = malloc(inst_size_size); |
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
689
diff
changeset
|
2640 memset(opts->gen.ram_inst_sizes, 0, inst_size_size); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2641 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2642 code_info *code = &opts->gen.code; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2643 init_code_info(code); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2644 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2645 opts->gen.save_context = code->cur; |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2646 for (int i = 0; i < 5; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2647 if (opts->flag_regs[i] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2648 mov_rrdisp(code, opts->flag_regs[i], opts->gen.context_reg, offsetof(m68k_context, flags) + i, SZ_B); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2649 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2650 for (int i = 0; i < 8; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2651 { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2652 if (opts->dregs[i] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2653 mov_rrdisp(code, opts->dregs[i], opts->gen.context_reg, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, SZ_D); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2654 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2655 if (opts->aregs[i] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2656 mov_rrdisp(code, opts->aregs[i], opts->gen.context_reg, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, SZ_D); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2657 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2658 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2659 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(m68k_context, current_cycle), SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2660 retn(code); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2661 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2662 opts->gen.load_context = code->cur; |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2663 for (int i = 0; i < 5; i++) |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
689
diff
changeset
|
2664 { |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2665 if (opts->flag_regs[i] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2666 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + i, opts->flag_regs[i], SZ_B); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2667 } |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
689
diff
changeset
|
2668 } |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2669 for (int i = 0; i < 8; i++) |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2670 { |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2671 if (opts->dregs[i] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2672 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, opts->dregs[i], SZ_D); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2673 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2674 if (opts->aregs[i] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2675 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, opts->aregs[i], SZ_D); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2676 } |
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2677 } |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2678 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, current_cycle), opts->gen.cycles, SZ_D); |
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2679 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, target_cycle), opts->gen.limit, SZ_D); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2680 retn(code); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2681 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2682 opts->start_context = (start_fun)code->cur; |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
657
diff
changeset
|
2683 save_callee_save_regs(code); |
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
2684 #ifdef X86_64 |
1828
37afb9cf58be
Get 64-bit builds working for Windows target
Michael Pavone <pavone@retrodev.com>
parents:
1585
diff
changeset
|
2685 if (opts->gen.scratch2 != FIRST_ARG_REG) { |
37afb9cf58be
Get 64-bit builds working for Windows target
Michael Pavone <pavone@retrodev.com>
parents:
1585
diff
changeset
|
2686 mov_rr(code, FIRST_ARG_REG, opts->gen.scratch2, SZ_PTR); |
37afb9cf58be
Get 64-bit builds working for Windows target
Michael Pavone <pavone@retrodev.com>
parents:
1585
diff
changeset
|
2687 } |
37afb9cf58be
Get 64-bit builds working for Windows target
Michael Pavone <pavone@retrodev.com>
parents:
1585
diff
changeset
|
2688 if (opts->gen.context_reg != SECOND_ARG_REG) { |
37afb9cf58be
Get 64-bit builds working for Windows target
Michael Pavone <pavone@retrodev.com>
parents:
1585
diff
changeset
|
2689 mov_rr(code, SECOND_ARG_REG, opts->gen.context_reg, SZ_PTR); |
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
2690 } |
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
2691 #else |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2692 mov_rdispr(code, RSP, 20, opts->gen.scratch2, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2693 mov_rdispr(code, RSP, 24, opts->gen.context_reg, SZ_D); |
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
2694 #endif |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2695 call(code, opts->gen.load_context); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2696 call_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2697 call(code, opts->gen.save_context); |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
657
diff
changeset
|
2698 restore_callee_save_regs(code); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2699 retn(code); |
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
2700 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2701 opts->native_addr = code->cur; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2702 call(code, opts->gen.save_context); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2703 push_r(code, opts->gen.context_reg); |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2704 call_args(code, (code_ptr)get_native_address_trans, 2, opts->gen.context_reg, opts->gen.scratch1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2705 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR); //move result to scratch reg |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2706 pop_r(code, opts->gen.context_reg); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2707 call(code, opts->gen.load_context); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2708 retn(code); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2709 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2710 opts->native_addr_and_sync = code->cur; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2711 call(code, opts->gen.save_context); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2712 push_r(code, opts->gen.scratch1); |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2713 |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2714 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_D); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2715 call_args_abi(code, (code_ptr)opts->sync_components, 2, opts->gen.context_reg, opts->gen.scratch1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2716 pop_r(code, RSI); //restore saved address from opts->gen.scratch1 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2717 push_r(code, RAX); //save context pointer for later |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2718 call_args(code, (code_ptr)get_native_address_trans, 2, RAX, RSI); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2719 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR); //move result to scratch reg |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2720 pop_r(code, opts->gen.context_reg); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2721 call(code, opts->gen.load_context); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2722 retn(code); |
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2723 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2724 opts->gen.handle_cycle_limit = code->cur; |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2725 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, sync_cycle), opts->gen.cycles, SZ_D); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2726 code_ptr skip_sync = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2727 jcc(code, CC_C, code->cur + 2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2728 opts->do_sync = code->cur; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2729 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2730 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2731 call(code, opts->gen.save_context); |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
2732 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_D); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2733 call_args_abi(code, (code_ptr)opts->sync_components, 2, opts->gen.context_reg, opts->gen.scratch1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2734 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2735 call(code, opts->gen.load_context); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2736 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2737 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2738 *skip_sync = code->cur - (skip_sync+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2739 retn(code); |
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
2740 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
2741 opts->gen.handle_code_write = (code_ptr)m68k_handle_code_write; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2742 |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2743 check_alloc_code(code, 256); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2744 opts->gen.handle_align_error_write = code->cur; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2745 code->cur += 256; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2746 check_alloc_code(code, 256); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2747 opts->gen.handle_align_error_read = code->cur; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2748 code->cur += 256; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2749 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
2750 opts->read_16 = gen_mem_fun(&opts->gen, memmap, num_chunks, READ_16, NULL); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
2751 opts->read_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, READ_8, NULL); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
2752 opts->write_16 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_16, NULL); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
2753 opts->write_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_8, NULL); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2754 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2755 opts->read_32 = code->cur; |
2101
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2756 if (opts->gen.align_error_mask) { |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2757 test_ir(code, opts->gen.align_error_mask, opts->gen.scratch1, SZ_D); |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2758 jcc(code, CC_NZ, opts->gen.handle_align_error_read); |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2759 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2760 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2761 call(code, opts->read_16); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2762 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_W); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2763 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2764 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2765 add_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2766 call(code, opts->read_16); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2767 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2768 movzx_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_W, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2769 shl_ir(code, 16, opts->gen.scratch2, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2770 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2771 retn(code); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2772 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2773 opts->write_32_lowfirst = code->cur; |
2101
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2774 if (opts->gen.align_error_mask) { |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2775 test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D); |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2776 jcc(code, CC_NZ, opts->gen.handle_align_error_write); |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2777 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2778 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2779 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2780 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2781 call(code, opts->write_16); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2782 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2783 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2784 shr_ir(code, 16, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2785 jmp(code, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2786 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2787 opts->write_32_highfirst = code->cur; |
2101
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2788 if (opts->gen.align_error_mask) { |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2789 test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D); |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2790 jcc(code, CC_NZ, opts->gen.handle_align_error_write); |
17ecd28ddc8a
Fix handling of address error for 32-bit accesses
Michael Pavone <pavone@retrodev.com>
parents:
2086
diff
changeset
|
2791 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2792 push_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2793 push_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2794 shr_ir(code, 16, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2795 call(code, opts->write_16); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2796 pop_r(code, opts->gen.scratch2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2797 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2798 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2799 jmp(code, opts->write_16); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2800 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2801 opts->get_sr = code->cur; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2802 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2803 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2804 if (opts->flag_regs[FLAG_X] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2805 mov_rr(code, opts->flag_regs[FLAG_X], opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2806 } else { |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2807 int8_t offset = offsetof(m68k_context, flags); |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2808 if (offset) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2809 mov_rdispr(code, opts->gen.context_reg, offset, opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2810 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2811 mov_rindr(code, opts->gen.context_reg, opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2812 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2813 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2814 for (int flag = FLAG_N; flag <= FLAG_C; flag++) |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2815 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2816 shl_ir(code, 1, opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2817 if (opts->flag_regs[flag] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2818 or_rr(code, opts->flag_regs[flag], opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2819 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2820 or_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2821 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2822 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2823 retn(code); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2824 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2825 opts->set_sr = code->cur; |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2826 for (int flag = FLAG_C; flag >= FLAG_X; flag--) |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2827 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2828 rcr_ir(code, 1, opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2829 if (opts->flag_regs[flag] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2830 setcc_r(code, CC_C, opts->flag_regs[flag]); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2831 } else { |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2832 int8_t offset = offsetof(m68k_context, flags) + flag; |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2833 if (offset) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2834 setcc_rdisp(code, CC_C, opts->gen.context_reg, offset); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2835 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2836 setcc_rind(code, CC_C, opts->gen.context_reg); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2837 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2838 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2839 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2840 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2841 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
2842 //set int pending flag in case we trigger an interrupt as a result of the mask change |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
2843 mov_irdisp(code, INT_PENDING_SR_CHANGE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2844 retn(code); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2845 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2846 opts->set_ccr = code->cur; |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2847 for (int flag = FLAG_C; flag >= FLAG_X; flag--) |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2848 { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2849 rcr_ir(code, 1, opts->gen.scratch1, SZ_B); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2850 if (opts->flag_regs[flag] >= 0) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2851 setcc_r(code, CC_C, opts->flag_regs[flag]); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2852 } else { |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2853 int8_t offset = offsetof(m68k_context, flags) + flag; |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2854 if (offset) { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2855 setcc_rdisp(code, CC_C, opts->gen.context_reg, offset); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2856 } else { |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2857 setcc_rind(code, CC_C, opts->gen.context_reg); |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2858 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2859 } |
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2860 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2861 retn(code); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2862 |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2863 code_info tmp_code = *code; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2864 code->cur = opts->gen.handle_align_error_write; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2865 code->last = code->cur + 256; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2866 //unwind the stack one functinon call |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2867 add_ir(code, 16, RSP, SZ_PTR); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2868 //save address that triggered error so we can write it to the 68K stack at the appropriate place |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2869 push_r(code, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2870 //swap USP and SSP if not already in supervisor mode |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2871 check_user_mode_swap_ssp_usp(opts); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2872 //save PC |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2873 subi_areg(opts, 4, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2874 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2875 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, last_prefetch_address), opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2876 call(code, opts->write_32_lowfirst); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2877 //save status register |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2878 subi_areg(opts, 2, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2879 call(code, opts->get_sr); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2880 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2881 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2882 //save instruction register |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2883 subi_areg(opts, 2, 7); |
989
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2884 //calculate IR |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2885 push_r(code, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2886 call(code, opts->gen.save_context); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2887 call_args_abi(code, (code_ptr)m68k_get_ir, 1, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2888 mov_rr(code, RAX, opts->gen.scratch1, SZ_W); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2889 pop_r(code, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2890 pop_r(code, opts->gen.scratch2); //access address |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2891 push_r(code, RAX); //save it for use in the "info" word |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2892 push_r(code, opts->gen.scratch2); //access address |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2893 call(code, opts->gen.load_context); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2894 //write it to the stack |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2895 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2896 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2897 //save access address |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2898 subi_areg(opts, 4, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2899 pop_r(code, opts->gen.scratch1); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2900 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2901 call(code, opts->write_32_lowfirst); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2902 //save FC, I/N and R/W word' |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2903 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_W); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2904 //FC3 is basically the same as the supervisor bit |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2905 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2906 shr_ir(code, 3, opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2907 and_ir(code, 4, opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2908 //set FC0 to one to indicate data access |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2909 or_ir(code, 1, opts->gen.scratch1, SZ_B); |
989
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2910 //set undefined bits to IR value |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2911 pop_r(code, opts->gen.scratch2); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2912 and_ir(code, 0xFFE0, opts->gen.scratch2, SZ_W); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2913 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2914 subi_areg(opts, 2, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2915 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2916 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2917 //set supervisor bit |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2918 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2919 //load vector address |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2920 mov_ir(code, 4 * VECTOR_ADDRESS_ERROR, opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2921 call(code, opts->read_32); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2922 call(code, opts->native_addr_and_sync); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2923 cycles(&opts->gen, 18); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2924 jmp_r(code, opts->gen.scratch1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2925 |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2926 code->cur = opts->gen.handle_align_error_read; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2927 code->last = code->cur + 256; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2928 //unwind the stack one functinon call |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2929 add_ir(code, 16, RSP, SZ_PTR); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2930 //save address that triggered error so we can write it to the 68K stack at the appropriate place |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2931 push_r(code, opts->gen.scratch1); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2932 //swap USP and SSP if not already in supervisor mode |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2933 check_user_mode_swap_ssp_usp(opts); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2934 //save PC |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2935 subi_areg(opts, 4, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2936 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2937 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, last_prefetch_address), opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2938 call(code, opts->write_32_lowfirst); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2939 //save status register |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2940 subi_areg(opts, 2, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2941 call(code, opts->get_sr); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2942 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2943 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2944 //save instruction register |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2945 subi_areg(opts, 2, 7); |
989
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2946 //calculate IR |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2947 push_r(code, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2948 call(code, opts->gen.save_context); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2949 call_args_abi(code, (code_ptr)m68k_get_ir, 1, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2950 mov_rr(code, RAX, opts->gen.scratch1, SZ_W); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2951 pop_r(code, opts->gen.context_reg); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2952 pop_r(code, opts->gen.scratch2); //access address |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2953 push_r(code, RAX); //save it for use in the "info" word |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2954 push_r(code, opts->gen.scratch2); //access address |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2955 call(code, opts->gen.load_context); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2956 //write it to the stack |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2957 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2958 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2959 //save access address |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2960 subi_areg(opts, 4, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2961 pop_r(code, opts->gen.scratch1); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2962 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2963 call(code, opts->write_32_lowfirst); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2964 //save FC, I/N and R/W word' |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2965 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_W); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2966 //FC3 is basically the same as the supervisor bit |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2967 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2968 shr_ir(code, 3, opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2969 and_ir(code, 4, opts->gen.scratch1, SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2970 //set FC0 to one to indicate data access, and R/W to indicate read |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2971 or_ir(code, 0x11, opts->gen.scratch1, SZ_B); |
989
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2972 //set undefined bits to IR value |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2973 pop_r(code, opts->gen.scratch2); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2974 and_ir(code, 0xFFE0, opts->gen.scratch2, SZ_W); |
d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
2975 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2976 subi_areg(opts, 2, 7); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2977 areg_to_native(opts, 7, opts->gen.scratch2); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2978 call(code, opts->write_16); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2979 //set supervisor bit |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2980 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2981 //load vector address |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2982 mov_ir(code, 4 * VECTOR_ADDRESS_ERROR, opts->gen.scratch1, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2983 call(code, opts->read_32); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2984 call(code, opts->native_addr_and_sync); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2985 cycles(&opts->gen, 18); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2986 jmp_r(code, opts->gen.scratch1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
2987 |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
986
diff
changeset
|
2988 *code = tmp_code; |
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
2989 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2990 opts->gen.handle_cycle_limit_int = code->cur; |
2232
0c42982dd4d8
Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2226
diff
changeset
|
2991 //calculate address adjust for sync return |
0c42982dd4d8
Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2226
diff
changeset
|
2992 check_cycles_int(&opts->gen, 0); |
902
6011409ded0d
Fix a few lingering stack alignment rework bugs
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
2993 uint32_t adjust_size = code->cur - opts->gen.handle_cycle_limit_int; |
6011409ded0d
Fix a few lingering stack alignment rework bugs
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
2994 code->cur = opts->gen.handle_cycle_limit_int; |
2232
0c42982dd4d8
Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2226
diff
changeset
|
2995 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
0c42982dd4d8
Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2226
diff
changeset
|
2996 adjust_size -= code->cur - opts->gen.handle_cycle_limit_int; |
0c42982dd4d8
Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2226
diff
changeset
|
2997 code->cur = opts->gen.handle_cycle_limit_int; |
1304
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
2998 //handle trace mode |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
2999 cmp_irdisp(code, 0, opts->gen.context_reg, offsetof(m68k_context, trace_pending), SZ_B); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3000 code_ptr do_trace = code->cur + 1; |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3001 jcc(code, CC_NZ, do_trace); |
1304
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
3002 bt_irdisp(code, 7, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
3003 code_ptr no_trace = code->cur + 1; |
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
3004 jcc(code, CC_NC, no_trace); |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3005 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(m68k_context, trace_pending), SZ_B); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3006 *no_trace = code->cur - (no_trace + 1); |
1304
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
3007 //handle interrupts |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
3008 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_cycle), opts->gen.cycles, SZ_D); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3009 code_ptr do_int = code->cur + 2; |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3010 jcc(code, CC_NC, do_int+512);//force 32-bit displacement |
1304
5b90d7669eee
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Michael Pavone <pavone@retrodev.com>
parents:
1303
diff
changeset
|
3011 //handle component synchronization |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
3012 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, sync_cycle), opts->gen.cycles, SZ_D); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3013 skip_sync = code->cur + 1; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3014 jcc(code, CC_C, code->cur + 2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3015 call(code, opts->gen.save_context); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3016 call_args_abi(code, (code_ptr)opts->sync_components, 2, opts->gen.context_reg, opts->gen.scratch1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3017 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3018 call(code, opts->gen.load_context); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3019 *skip_sync = code->cur - (skip_sync+1); |
872
7022ba865cfd
Initial work for allowing loading a ROM from menu
Michael Pavone <pavone@retrodev.com>
parents:
847
diff
changeset
|
3020 cmp_irdisp(code, 0, opts->gen.context_reg, offsetof(m68k_context, should_return), SZ_B); |
7022ba865cfd
Initial work for allowing loading a ROM from menu
Michael Pavone <pavone@retrodev.com>
parents:
847
diff
changeset
|
3021 code_ptr do_ret = code->cur + 1; |
7022ba865cfd
Initial work for allowing loading a ROM from menu
Michael Pavone <pavone@retrodev.com>
parents:
847
diff
changeset
|
3022 jcc(code, CC_NZ, do_ret); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3023 retn(code); |
872
7022ba865cfd
Initial work for allowing loading a ROM from menu
Michael Pavone <pavone@retrodev.com>
parents:
847
diff
changeset
|
3024 *do_ret = code->cur - (do_ret+1); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3025 uint32_t tmp_stack_off = code->stack_off; |
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3026 //fetch return address and adjust RSP |
872
7022ba865cfd
Initial work for allowing loading a ROM from menu
Michael Pavone <pavone@retrodev.com>
parents:
847
diff
changeset
|
3027 pop_r(code, opts->gen.scratch1); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3028 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
2232
0c42982dd4d8
Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2226
diff
changeset
|
3029 sub_ir(code, adjust_size, opts->gen.scratch1, SZ_PTR); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3030 //save return address for restoring later |
883
9f149f0e98b7
It is now possible to switch back and forth between the menu ROM and the game
Michael Pavone <pavone@retrodev.com>
parents:
872
diff
changeset
|
3031 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, resume_pc), SZ_PTR); |
872
7022ba865cfd
Initial work for allowing loading a ROM from menu
Michael Pavone <pavone@retrodev.com>
parents:
847
diff
changeset
|
3032 retn(code); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3033 code->stack_off = tmp_stack_off; |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3034 *do_trace = code->cur - (do_trace + 1); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3035 //clear out trace pending flag |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3036 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(m68k_context, trace_pending), SZ_B); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3037 //save PC as stored in scratch1 for later |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3038 push_r(code, opts->gen.scratch1); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3039 //swap USP and SSP if not already in supervisor mode |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3040 check_user_mode_swap_ssp_usp(opts); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3041 //save status register |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3042 subi_areg(opts, 6, 7); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3043 call(code, opts->get_sr); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3044 cycles(&opts->gen, 6); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3045 //save SR to stack |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3046 areg_to_native(opts, 7, opts->gen.scratch2); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3047 call(code, opts->write_16); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3048 //update the status register |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3049 and_irdisp(code, 0x7F, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3050 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3051 //save PC |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3052 areg_to_native(opts, 7, opts->gen.scratch2); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3053 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3054 pop_r(code, opts->gen.scratch1); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3055 call(code, opts->write_32_lowfirst); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3056 //read vector |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3057 mov_ir(code, 0x24, opts->gen.scratch1, SZ_D); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3058 call(code, opts->read_32); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3059 call(code, opts->native_addr_and_sync); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3060 //2 prefetch bus operations + 2 idle bus cycles |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3061 cycles(&opts->gen, 10); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3062 //discard function return address |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3063 pop_r(code, opts->gen.scratch2); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3064 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3065 jmp_r(code, opts->gen.scratch1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3066 |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3067 code->stack_off = tmp_stack_off; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3068 |
1303
208803173ebc
Implemented M68K trace mode. Some edge cases/SR update paths still need work
Michael Pavone <pavone@retrodev.com>
parents:
1297
diff
changeset
|
3069 *((uint32_t *)do_int) = code->cur - (do_int+4); |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
3070 //implement 1 instruction latency |
1097
faa3a4617f62
Get Jaguar video interrupt working
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
3071 cmp_irdisp(code, INT_PENDING_NONE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
3072 do_int = code->cur + 1; |
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
3073 jcc(code, CC_NZ, do_int); |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3074 //store current interrupt number so it doesn't change before we start processing the vector |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3075 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_num), opts->gen.scratch1, SZ_B); |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3076 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
846
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
3077 retn(code); |
98d7b6073163
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
Michael Pavone <pavone@retrodev.com>
parents:
839
diff
changeset
|
3078 *do_int = code->cur - (do_int + 1); |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3079 //Check if int_pending has an actual interrupt priority in it |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3080 cmp_irdisp(code, INT_PENDING_SR_CHANGE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3081 code_ptr already_int_num = code->cur + 1; |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3082 jcc(code, CC_NZ, already_int_num); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3083 |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3084 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_num), opts->gen.scratch2, SZ_B); |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3085 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3086 |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3087 *already_int_num = code->cur - (already_int_num + 1); |
847
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3088 //save PC as stored in scratch1 for later |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3089 push_r(code, opts->gen.scratch1); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
3090 //set target cycle to sync cycle |
656
24ccfd70133a
Added 2 new functions to gen_x86.c for handling passing args according to the C abi of the host system and adapted the code in m68k_core_x86.c to use that instead of doing everything by hand
Michael Pavone <pavone@retrodev.com>
parents:
654
diff
changeset
|
3091 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, sync_cycle), opts->gen.limit, SZ_D); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
3092 //swap USP and SSP if not already in supervisor mode |
687
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
3093 check_user_mode_swap_ssp_usp(opts); |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
3094 //save status register |
847
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3095 subi_areg(opts, 6, 7); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3096 call(code, opts->get_sr); |
847
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3097 //6 cycles before SR gets saved |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3098 cycles(&opts->gen, 6); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3099 //save SR to stack |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
3100 areg_to_native(opts, 7, opts->gen.scratch2); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3101 call(code, opts->write_16); |
847
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3102 //interrupt ack cycle |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3103 //the Genesis responds to these exclusively with !VPA which means its a slow |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3104 //6800 operation. documentation says these can take between 10 and 19 cycles. |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3105 //actual results measurements seem to suggest it's actually between 9 and 18 |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3106 //WARNING: this code might break with register assignment changes |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3107 //save RDX |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3108 push_r(code, RDX); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3109 //save cycle count |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3110 mov_rr(code, RAX, opts->gen.scratch1, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3111 //clear top doubleword of dividend |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3112 xor_rr(code, RDX, RDX, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3113 //set divisor to clock divider |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3114 mov_ir(code, opts->gen.clock_divider, opts->gen.scratch2, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3115 div_r(code, opts->gen.scratch2, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3116 //discard remainder |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3117 xor_rr(code, RDX, RDX, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3118 //set divisor to 10, the period of E |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3119 mov_ir(code, 10, opts->gen.scratch2, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3120 div_r(code, opts->gen.scratch2, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3121 //delay will be (9 + 4 + the remainder) * clock_divider |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3122 //the extra 4 is to cover the idle bus period after the ack |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3123 add_ir(code, 9 + 4, RDX, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3124 mov_ir(code, opts->gen.clock_divider, RAX, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3125 mul_r(code, RDX, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3126 pop_r(code, RDX); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3127 //add saved cycle count to result |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3128 add_rr(code, opts->gen.scratch1, RAX, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3129 |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
3130 //update status register |
1461
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
3131 and_irdisp(code, 0x78, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3132 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_num), opts->gen.scratch1, SZ_B); |
1461
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
3133 //clear trace pending flag |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
3134 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(m68k_context, trace_pending), SZ_B); |
1097
faa3a4617f62
Get Jaguar video interrupt working
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
3135 //need to separate int priority and interrupt vector, but for now mask out large interrupt numbers |
faa3a4617f62
Get Jaguar video interrupt working
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
3136 and_ir(code, 0x7, opts->gen.scratch1, SZ_B); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3137 or_ir(code, 0x20, opts->gen.scratch1, SZ_B); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3138 or_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
847
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3139 |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3140 pop_r(code, opts->gen.scratch1); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3141 |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3142 //save PC |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3143 areg_to_native(opts, 7, opts->gen.scratch2); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3144 add_ir(code, 2, opts->gen.scratch2, SZ_D); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3145 call(code, opts->write_32_lowfirst); |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3146 |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3147 //grab saved interrupt number |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3148 xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_D); |
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3149 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_pending), opts->gen.scratch1, SZ_B); |
887
fb4d09f874dd
Prevent the current interrupt number from being changed while interrupt is being processed. This fixes a bug in Sonic 2 split screen that showed up when interrupt timing was adjusted
Michael Pavone <pavone@retrodev.com>
parents:
883
diff
changeset
|
3150 //ack the interrupt (happens earlier on hardware, but shouldn't be an observable difference) |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3151 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, int_ack), SZ_W); |
887
fb4d09f874dd
Prevent the current interrupt number from being changed while interrupt is being processed. This fixes a bug in Sonic 2 split screen that showed up when interrupt timing was adjusted
Michael Pavone <pavone@retrodev.com>
parents:
883
diff
changeset
|
3152 //calculate the vector address |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3153 shl_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3154 add_ir(code, 0x60, opts->gen.scratch1, SZ_D); |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3155 //clear out pending flag |
1097
faa3a4617f62
Get Jaguar video interrupt working
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
3156 mov_irdisp(code, INT_PENDING_NONE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
996
784bc1e45e80
Fix 68K interrupt handling some more. Fatal Rewind is working again.
Michael Pavone <pavone@retrodev.com>
parents:
990
diff
changeset
|
3157 //read vector |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3158 call(code, opts->read_32); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3159 call(code, opts->native_addr_and_sync); |
847
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3160 //2 prefetch bus operations + 2 idle bus cycles |
7decd421cdc8
Update timing and order of steps in interrupt processing to match latest measurements
Michael Pavone <pavone@retrodev.com>
parents:
846
diff
changeset
|
3161 cycles(&opts->gen, 10); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3162 tmp_stack_off = code->stack_off; |
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
3163 //discard function return address |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3164 pop_r(code, opts->gen.scratch2); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3165 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3166 jmp_r(code, opts->gen.scratch1); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
887
diff
changeset
|
3167 code->stack_off = tmp_stack_off; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3168 |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3169 opts->handle_int_latch = code->cur; |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3170 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_cycle), opts->gen.cycles, SZ_D); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3171 code_ptr do_latch = code->cur + 1; |
1363
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3172 jcc(code, CC_NC, do_latch); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3173 retn(code); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3174 *do_latch = code->cur - (do_latch + 1); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3175 cmp_irdisp(code, INT_PENDING_NONE, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3176 do_latch = code->cur + 1; |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3177 jcc(code, CC_Z, do_latch); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3178 retn(code); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3179 *do_latch = code->cur - (do_latch + 1); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3180 //store current interrupt number so it doesn't change before we start processing the vector |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3181 push_r(code, opts->gen.scratch1); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3182 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_num), opts->gen.scratch1, SZ_B); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3183 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3184 pop_r(code, opts->gen.scratch1); |
df6af7187b36
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Michael Pavone <pavone@retrodev.com>
parents:
1332
diff
changeset
|
3185 retn(code); |
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3186 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3187 opts->trap = code->cur; |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3188 push_r(code, opts->gen.scratch2); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3189 //swap USP and SSP if not already in supervisor mode |
687
a61d33ccea7d
Moved translate_m68k_rte and translate_m68k_reset to m68k_core.c
Michael Pavone <pavone@retrodev.com>
parents:
686
diff
changeset
|
3190 check_user_mode_swap_ssp_usp(opts); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3191 //save PC |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
3192 subi_areg(opts, 4, 7); |
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
3193 areg_to_native(opts, 7, opts->gen.scratch2); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3194 call(code, opts->write_32_lowfirst); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3195 //save status register |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
3196 subi_areg(opts, 2, 7); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3197 call(code, opts->get_sr); |
574
1594525e2157
More 68K core refactoring to both reduce the amount of code and better split the host-cpu specific parts from the generic parts
Michael Pavone <pavone@retrodev.com>
parents:
571
diff
changeset
|
3198 areg_to_native(opts, 7, opts->gen.scratch2); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3199 call(code, opts->write_16); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3200 //set supervisor bit |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3201 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
1461
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
3202 //clear trace bit |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
3203 and_irdisp(code, 0x7F, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
aa945f1bdd71
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Michael Pavone <pavone@retrodev.com>
parents:
1430
diff
changeset
|
3204 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(m68k_context, trace_pending), SZ_B); |
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3205 //calculate vector address |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3206 pop_r(code, opts->gen.scratch1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3207 shl_ir(code, 2, opts->gen.scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3208 call(code, opts->read_32); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3209 call(code, opts->native_addr_and_sync); |
2225
e22137f0aca4
Fix some 68K exception processing cycle times
Michael Pavone <pavone@retrodev.com>
parents:
2224
diff
changeset
|
3210 cycles(&opts->gen, 14); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
3211 jmp_r(code, opts->gen.scratch1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3212 |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3213 opts->retrans_stub = code->cur; |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3214 call(code, opts->gen.save_context); |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3215 push_r(code, opts->gen.context_reg); |
1465
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1461
diff
changeset
|
3216 call_args(code,(code_ptr)m68k_retranslate_inst, 2, opts->gen.scratch1, opts->gen.context_reg); |
1228
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3217 pop_r(code, opts->gen.context_reg); |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3218 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR); |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3219 call(code, opts->gen.load_context); |
2e6dcb5c11a2
WIP support for XBAND mapper hardware
Michael Pavone <pavone@retrodev.com>
parents:
1219
diff
changeset
|
3220 jmp_r(code, opts->gen.scratch1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3221 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3222 |
1329
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3223 check_code_prologue(code); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3224 opts->bp_stub = code->cur; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3225 |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3226 tmp_stack_off = code->stack_off; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3227 //Calculate length of prologue |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3228 check_cycles_int(&opts->gen, 0x1234); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3229 int check_int_size = code->cur-opts->bp_stub; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3230 code->cur = opts->bp_stub; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3231 code->stack_off = tmp_stack_off; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3232 opts->prologue_start = *opts->bp_stub; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3233 //Calculate length of patch |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3234 mov_ir(code, 0x1234, opts->gen.scratch1, SZ_D); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3235 call(code, opts->bp_stub); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3236 int patch_size = code->cur - opts->bp_stub; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3237 code->cur = opts->bp_stub; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3238 code->stack_off = tmp_stack_off; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3239 |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3240 //Save context and call breakpoint handler |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3241 call(code, opts->gen.save_context); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3242 push_r(code, opts->gen.scratch1); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3243 call_args_abi(code, (code_ptr)m68k_bp_dispatcher, 2, opts->gen.context_reg, opts->gen.scratch1); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3244 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3245 //Restore context |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3246 call(code, opts->gen.load_context); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3247 pop_r(code, opts->gen.scratch1); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3248 //do prologue stuff |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3249 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3250 code_ptr jmp_off = code->cur + 1; |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3251 jcc(code, CC_NC, code->cur + 7); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3252 call(code, opts->gen.handle_cycle_limit_int); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3253 *jmp_off = code->cur - (jmp_off+1); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3254 //jump back to body of translated instruction |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3255 pop_r(code, opts->gen.scratch1); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3256 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3257 jmp_r(code, opts->gen.scratch1); |
85a90964b557
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Michael Pavone <pavone@retrodev.com>
parents:
1304
diff
changeset
|
3258 code->stack_off = tmp_stack_off; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1989
diff
changeset
|
3259 |
1465
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1461
diff
changeset
|
3260 retranslate_calc(&opts->gen); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3261 } |