repos/blastem: cpu_dsl.py annotate

annotate cpu_dsl.py @ 2593:b0a7b1f708cc

Fix andi to ccr in new 68K core

author	Michael Pavone <pavone@retrodev.com>
date	Sun, 09 Feb 2025 16:55:00 -0800
parents	8ef8b2e99f4f
children	1c493b8c513b

rev	line source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	3 assignmentOps = {
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	4 '=': 'mov',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	5 '+=': 'add',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	6 '-=': 'sub',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	7 '<<=': 'lsl',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	8 '>>=': 'lsr',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	9 '&=': 'and',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	10 '\|=': 'or',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	11 '^=': 'xor'
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	12 }
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	13 binaryOps = {
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	14 '+': 'add',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	15 '-': 'sub',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	16 '<<': 'lsl',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	17 '>>': 'lsr',
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	18 '*': 'mulu',
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	19 '*S': 'muls',
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	20 '&': 'and',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	21 '\|': 'or',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	22 '^': 'xor'
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	23 }
2443 461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	24 unaryOps = {
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	25 '~': 'not',
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	26 '!': 'lnot',
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	27 '-': 'neg'
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	28 }
2442 52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	29 compareOps = {'>=U', '=', '!='}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	30 class Block:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 if parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 o = Switch(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39 elif parts[0] == 'if':
2442 52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	40 if len(parts) == 4 and parts[2] in compareOps:
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	41 self.addOp(NormalOp(['cmp', parts[3], parts[1]]))
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	42 cond = parts[2]
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	43 else:
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	44 cond = parts[1]
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	45 o = If(self, cond)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	48 elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	49 raise Exception('end is only allowed inside a switch or if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	50 else:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	51 if len(parts) > 1 and parts[1] in assignmentOps:
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	52 dst = parts[0]
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	53 dst,_,size = dst.partition(':')
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	54 op = parts[1]
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	55 parts = [assignmentOps[op]] + parts[2:]
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	56 if op == '=':
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	57 if len(parts) > 2 and parts[2] in binaryOps:
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	58 op = parts[2]
2478 ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	59 if op == '-':
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	60 tmp = parts[1]
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	61 parts[1] = parts[3]
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	62 parts[3] = tmp
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	63 parts[0] = binaryOps[op]
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	64 del parts[2]
2443 461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	65 elif len(parts) > 1 and parts[1][0] in unaryOps:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	66 rest = parts[1][1:]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	67 op = parts[1][0]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	68 if rest:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	69 parts[1] = rest
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	70 else:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	71 del parts[1]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	72 parts[0] = unaryOps[op]
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	73 else:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	74 if op == '<<=' or op == '>>=':
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	75 parts.insert(1, dst)
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	76 else:
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	77 parts.append(dst)
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	78 parts.append(dst)
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	79 if size:
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	80 parts.append(size)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	81 self.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	82 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	83
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	84 def processOps(self, prog, fieldVals, output, otype, oplist):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	85 for i in range(0, len(oplist)):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	86 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	87 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0])
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	88 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	89 flagUpdates = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	90 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	91
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	92 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	93 for op in self.implementation:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	94 op.processDispatch(prog)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	95
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	96 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	97 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	98
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	99 class ChildBlock(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	101 if parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	102 return self.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	103 return super().processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	104
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105 #Represents an instruction of the emulated CPU
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 class Instruction(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107 def __init__(self, value, fields, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108 self.value = value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109 self.fields = fields
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	110 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	111 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	112 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	113 self.regValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	114 self.varyingBits = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	115 self.invalidFieldValues = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	116 self.invalidCombos = []
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	117 self.newLocals = []
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	118 self.noSpecialize = set()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	119 for field in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	120 self.varyingBits += fields[field][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	121
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	122 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	123 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	124 name = op.params[0]
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	125 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	126 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	127 elif op.op == 'invalid':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	128 if len(op.params) < 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	129 name = op.params[0]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	130 value = int(op.params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	131 self.invalidFieldValues.setdefault(name, set()).add(value)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	132 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	133 vmap = {}
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	134 for i in range(0, len(op.params), 2):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	135 name = op.params[i]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	136 value = int(op.params[i+1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	137 vmap[name] = value
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	138 self.invalidCombos.append(vmap)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	139 elif op.op == 'nospecialize':
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	140 for name in op.params:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	141 self.noSpecialize.add(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	142 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	143 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	144
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	145 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 self.locals[name] = size
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	152 self.newLocals.append(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	153
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 return self.locals.get(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	156
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157 def __lt__(self, other):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	158 if isinstance(other, Instruction):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	159 if self.varyingBits != other.varyingBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	160 return self.varyingBits < other.varyingBits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	161 return self.value < other.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	162 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	163 return NotImplemented
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	164
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	165 def allValues(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	166 values = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	167 for i in range(0, 1 << self.varyingBits):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	168 iword = self.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	169 doIt = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	170 combos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	171 for combo in self.invalidCombos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	172 combos.append(dict(combo))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	173 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	174 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	175 val = i & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	176 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	177 doIt = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	178 break
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	179 nextcombos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	180 for combo in combos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	181 if field in combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	182 if combo[field] == val:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	183 del combo[field]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	184 if not combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	185 doIt = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	186 break
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	187 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	188 continue
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	189 nextcombos.append(combo)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	190 combos = nextcombos
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	191 if not doIt:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	192 break
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	193 i >>= bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	194 iword \|= val << shift
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	195 if doIt:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	196 values.append(iword)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	197 return values
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	199 def getFieldVals(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	200 fieldVals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	201 fieldBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	203 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 val = (value >> shift) & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 fieldVals[field] = val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	206 fieldBits[field] = bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207 return (fieldVals, fieldBits)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209 def generateName(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210 fieldVals,fieldBits = self.getFieldVals(value)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	211 for name in self.noSpecialize:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	212 del fieldVals[name]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	213 names = list(fieldVals.keys())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	214 names.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	215 funName = self.name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	216 for name in names:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	217 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	218 return funName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	219
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	220 def generateBody(self, value, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	221 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	222 prog.meta = {}
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	223 prog.pushScope(self)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	224 self.regValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	225 for var in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	226 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	227 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	228 fieldVals,_ = self.getFieldVals(value)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	229 for name in self.noSpecialize:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	230 del fieldVals[name]
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	231 self.locals[name] = prog.opsize
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	232 if len(prog.mainDispatch) != 1:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	233 raise Exception('nospecialize requires exactly 1 field used for main table dispatch')
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	234 shift,bits = self.fields[name]
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	235 mask = (1 << bits) - 1
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	236 opfield = list(prog.mainDispatch)[0]
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	237 if shift:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	238 output.append(f'\n\tuint{prog.opsize}_t {name} = context->{opfield} >> {shift} & {mask};')
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	239 else:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	240 output.append(f'\n\tuint{prog.opsize}_t {name} = context->{opfield} & {mask};')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	241 self.processOps(prog, fieldVals, output, otype, self.implementation)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	242 for name in self.noSpecialize:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	243 del self.locals[name]
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	244
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	245 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	246 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context, uint32_t target_cycle)\n{'
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	247 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	248 begin = '\n' + self.generateName(value) + ': {'
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	249 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	250 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	251 if prog.needFlagCoalesce:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	252 begin += prog.flags.coalesceFlags(prog, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	253 if prog.needFlagDisperse:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	254 output.append(prog.flags.disperseFlags(prog, otype))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	255 for var in self.newLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	256 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	257 for size in prog.temp:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	258 begin += '\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	259 prog.popScope()
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	260 if prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	261 output += prog.nextInstruction(otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	262 return begin + ''.join(output) + '\n}'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	263
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	264 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	265 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	267 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	270 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	271
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 #Represents the definition of a helper function
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 class SubRoutine(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	274 def __init__(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	275 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	276 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 self.args = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	278 self.arg_map = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	279 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	280 self.regValues = {}
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	281 self.argValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	282
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	283 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	284 if op.op == 'arg':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	285 name = op.params[0]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	286 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	287 self.arg_map[name] = len(self.args)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	288 self.args.append((name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	289 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	290 name = op.params[0]
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	291 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	292 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	293 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	294 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	295
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	296 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	297 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	298 return self.name + '_' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	299 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	300
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	301 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	302 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	303
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	304 def localSize(self, name):
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	305 if name in self.locals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	306 return self.locals[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	307 if name in self.arg_map:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	308 argIndex = self.arg_map[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	309 return self.args[argIndex][1]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	310 return None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	311
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	312 def inline(self, prog, params, output, otype, parent):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	313 if len(params) != len(self.args):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	314 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	315 argValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	316 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	317 self.regValues = parent.regValues
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	318 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	319 i = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	320 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	321 argValues[name] = params[i]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	322 i += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	323 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 size = self.locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name))
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	326 self.argValues = argValues
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	327 self.processOps(prog, argValues, output, otype, self.implementation)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	328 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	329
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	330 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	331 pieces = [self.name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	332 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	333 pieces.append('\n\targ {0} {1}'.format(name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	334 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	335 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	336 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	337 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	338 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	339
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	340 class Op:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	341 def __init__(self, evalFun = None):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	342 self.evalFun = evalFun
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	343 self.impls = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	344 self.outOp = ()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	345 def cBinaryOperator(self, op):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	346 def _impl(prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	347 if op == '-':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	348 a = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	349 b = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	350 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	351 a = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	352 b = params[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	353 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	354 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	355 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	356 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	357 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	358 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	359 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	360 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	361 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	362 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	363 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	364 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	365 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	366 prog.sizeAdjust = size
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	367 needsCarry = needsOflow = needsHalf = False
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	368 if flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	369 for flag in flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	370 calc = prog.flags.flagCalc[flag]
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	371 if calc == 'carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	372 needsCarry = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	373 elif calc == 'half-carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	374 needsHalf = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	375 elif calc == 'overflow':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	376 needsOflow = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	377 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	378 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	379 if len(params) <= 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	380 size = prog.paramSize(rawParams[2])
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	381 if needsCarry and op != '>>':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	382 size *= 2
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	383 decl,name = prog.getTemp(size)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	384 dst = prog.carryFlowDst = name
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	385 prog.lastA = a
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	386 prog.lastB = b
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	387 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	388 a = '((uint64_t){a})'.format(a=a)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	389 b = '((uint64_t){b})'.format(b=b)
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	390 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	391 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	392 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	393 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	394 return '{decl}\n\t{tmp} = ({a} & {mask}) {op} ({b} & {mask});\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	395 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	396 )
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	397 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	398 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	399 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	400 return decl + '\n\t{dst} = ({a} & {mask}) {op} ({b} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	401 dst = dst, a = a, b = b, op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	402 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	403 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	404 return decl + '\n\t{dst} = {a} {op} {b};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	405 dst = dst, a = a, b = b, op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	406 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	407 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	408 self.outOp = (2,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	409 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	410 def cUnaryOperator(self, op):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	411 def _impl(prog, params, rawParams, flagUpdates):
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	412 dst = params[1]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	413 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	414 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	415 if len(params) > 2:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	416 size = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	417 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	418 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	419 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	420 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	421 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	422 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	423 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	424 destSize = prog.paramSize(rawParams[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	425 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	426 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	427 prog.sizeAdjust = size
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	428 needsCarry = needsOflow = needsHalf = False
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	429 if op == '-':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	430 if flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	431 for flag in flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	432 calc = prog.flags.flagCalc[flag]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	433 if calc == 'carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	434 needsCarry = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	435 elif calc == 'half-carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	436 needsHalf = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	437 elif calc == 'overflow':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	438 needsOflow = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	439 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	440 size = prog.paramSize(rawParams[1])
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	441 decl,name = prog.getTemp(size)
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	442 dst = prog.carryFlowDst = name
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	443 prog.lastA = 0
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	444 prog.lastB = params[0]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	445 prog.lastBFlow = params[0]
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	446 if needsSizeAdjust:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	447 return decl + '\n\t{dst} = {op}({a} & {mask});'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	448 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	449 )
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	450 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	451 return decl + '\n\t{dst} = ({dst} & ~{mask}) \| (({op}{a}) & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	452 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	453 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	454 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	455 return decl + '\n\t{dst} = {op}{a};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	456 dst = dst, a = params[0], op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	457 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	458 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	459 self.outOp = (1,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	461 def addImplementation(self, lang, outOp, impl):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	462 self.impls[lang] = impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	463 if not outOp is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	464 if type(outOp) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	465 self.outOp = outOp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	466 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	467 self.outOp = (outOp,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	468 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	469 def evaluate(self, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	470 return self.evalFun(*params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	471 def canEval(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	472 return not self.evalFun is None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	473 def numArgs(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	474 return self.evalFun.__code__.co_argcount
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	475 def numParams(self):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	476 if self.outOp:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	477 params = max(self.outOp) + 1
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	478 else:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	479 params = 0
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	480 if self.evalFun:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	481 params = max(params, self.numArgs())
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	482 return params
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	483 def generate(self, otype, prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	484 if self.impls[otype].__code__.co_argcount == 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	485 return self.impls[otype](prog, params)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	486 elif self.impls[otype].__code__.co_argcount == 3:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	487 return self.impls[otype](prog, params, rawParams)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	488 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	489 return self.impls[otype](prog, params, rawParams, flagUpdates)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	490
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	491
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	492 def _xchgCImpl(prog, params, rawParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	493 size = prog.paramSize(rawParams[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	494 decl,name = prog.getTemp(size)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	495 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	496
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	497 def _dispatchCImpl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	498 if len(params) == 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	499 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	500 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	501 table = params[1]
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	502 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	503 return '\n\timpl_{tbl}[{op}](context, target_cycle);'.format(tbl = table, op = params[0])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	504 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	505 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	506 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	507 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	508
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	509 def _addExplicitFlagSet(prog, output, flag, flagval):
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	510 location = prog.flags.getStorage(flag)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	511 if type(location) is tuple:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	512 reg,bit = location
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	513 reg = prog.resolveReg(reg, None, {})
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	514 value = str(1 << bit)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	515 if flagval:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	516 operator = '\|='
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	517 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	518 operator = '&='
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	519 value = '~' + value
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	520 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value))
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	521 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	522 reg = prog.resolveReg(location, None, {})
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	523 output.append('\n\t{reg} = {val};'.format(reg=reg, val=flagval))
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	524
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	525 def _updateFlagsCImpl(prog, params, rawParams):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	526 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	527 output = []
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	528 parity = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	529 directFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	530 for flag in autoUpdate:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	531 calc = prog.flags.flagCalc[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	532 calc,_,resultBit = calc.partition('-')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	533 if prog.carryFlowDst:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	534 lastDst = prog.carryFlowDst
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	535 else:
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	536 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	537 storage = prog.flags.getStorage(flag)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	538 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	539 myRes = lastDst
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	540 after = ''
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	541 if calc == 'sign':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	542 resultBit = prog.getLastSize() - 1
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	543 elif calc == 'carry':
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	544 if prog.lastOp.op in ('asr', 'lsr', 'rrc'):
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	545 if type(prog.lastB) is int:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	546 if prog.lastB == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	547 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	548 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	549 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	550 resultBit = prog.lastB - 1
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	551 else:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	552 output.append(f'\n\tif (!{prog.lastB}) {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	553 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	554 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	555 after = '\n\t}'
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	556 resultBit = f'({prog.lastB} - 1)'
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	557 myRes = prog.lastA
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	558 elif prog.lastOp.op == 'rlc':
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	559 if type(prog.lastB) is int:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	560 if prog.lastB == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	561 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	562 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	563 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	564 resultBit = prog.getLastSize() - prog.lastB
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	565 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	566 output.append(f'\n\tif (!{prog.lastB}) {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	567 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	568 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	569 after = '\n\t}'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	570 resultBit = f'({prog.getLastSize()} - {prog.lastB})'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	571 myRes = prog.lastA
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	572 elif prog.lastOp.op == 'rol':
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	573 if type(prog.lastBUnmasked) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	574 if prog.lastBUnmasked == 0:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	575 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	576 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	577 else:
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	578 output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	579 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	580 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	581 after = '\n\t}'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	582 resultBit = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	583 elif prog.lastOp.op == 'ror':
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	584 if type(prog.lastBUnmasked) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	585 if prog.lastBUnmasked == 0:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	586 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	587 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	588 else:
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	589 output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	590 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	591 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	592 after = '\n\t}'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	593 resultBit = prog.getLastSize() - 1
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	594 elif prog.lastOp.op == 'neg':
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	595 if prog.carryFlowDst:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	596 realSize = prog.getLastSize()
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	597 if realSize != prog.paramSize(prog.carryFlowDst):
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	598 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	599 if type(storage) is tuple:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	600 reg,storageBit = storage
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	601 reg = prog.resolveParam(reg, None, {})
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	602 output.append('\n\t{reg} = {res} ? ({reg} \| {bit}U) : ({reg} & {mask}U);'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	603 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	604 ))
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	605 else:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	606 reg = prog.resolveParam(storage, None, {})
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	607 output.append('\n\t{reg} = {res} != 0;'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	608 reg = reg, res = lastDst
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	609 ))
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	610 continue
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	611 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	612 resultBit = prog.getLastSize()
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	613 elif calc == 'half':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	614 resultBit = prog.getLastSize() - 4
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	615 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	616 elif calc == 'overflow':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	617 resultBit = prog.getLastSize() - 1
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	618 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	619 else:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	620 #Note: offsetting this by the operation size - 8 makes sense for the Z80
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	621 #but might not for other CPUs with this kind of fixed bit flag behavior
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	622 resultBit = int(resultBit) + prog.getLastSize() - 8
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	623 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	624 reg,storageBit = storage
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	625 if storageBit == resultBit:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	626 directFlags.setdefault((reg, myRes), []).append(resultBit)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	627 else:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	628 reg = prog.resolveParam(reg, None, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	629 if resultBit > storageBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	630 op = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	631 shift = resultBit - storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	632 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	633 op = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	634 shift = storageBit - resultBit
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	635 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} {op} {shift}U & {mask}U);'.format(
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	636 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	637 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	638 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	639 reg = prog.resolveParam(storage, None, {})
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	640 maxBit = prog.paramSize(storage) - 1
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	641 if type(resultBit) is int:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	642 mask = f'{1 << resultBit}U'
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	643 else:
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	644 mask = f'(1 << {resultBit})'
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	645 if not type(resultBit) is int:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	646 output.append(f'\n\t{reg} = !!({myRes} & {mask});')
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	647 elif resultBit > maxBit:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	648 mask = f'{1 << maxBit}U'
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	649 output.append('\n\t{reg} = {res} >> {shift} & {mask};'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = mask))
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	650 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	651 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask))
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	652 if after:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	653 output.append(after)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	654 elif calc == 'zero':
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	655 if prog.carryFlowDst:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	656 realSize = prog.getLastSize()
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	657 if realSize != prog.paramSize(prog.carryFlowDst):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	658 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	659 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	660 reg,storageBit = storage
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	661 reg = prog.resolveParam(reg, None, {})
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	662 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} \| {bit}U);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	663 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	664 ))
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	665 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	666 reg = prog.resolveParam(storage, None, {})
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	667 output.append('\n\t{reg} = {res} == 0;'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	668 reg = reg, res = lastDst
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	669 ))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	670 elif calc == 'parity':
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	671 parity = storage
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	672 paritySize = prog.getLastSize()
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	673 if prog.carryFlowDst:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	674 parityDst = paritySrc = prog.carryFlowDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	675 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	676 paritySrc = lastDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	677 decl,name = prog.getTemp(paritySize)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	678 output.append(decl)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	679 parityDst = name
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	680 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	681 raise Exception('Unknown flag calc type: ' + calc)
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	682 for reg, myRes in directFlags:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	683 bits = directFlags[(reg, myRes)]
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	684 resolved = prog.resolveParam(reg, None, {})
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	685 if len(bits) == len(prog.flags.storageToFlags[reg]):
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	686 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes))
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	687 else:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	688 mask = 0
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	689 for bit in bits:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	690 mask \|= 1 << bit
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	691 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} & {mask}U);'.format(
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	692 reg = resolved, mask = mask, res = myRes
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	693 ))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	694 if prog.carryFlowDst:
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	695 if prog.lastOp.op != 'cmp':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	696 if prog.sizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	697 output.append('\n\t{dst} = ({dst} & ~{mask}) \| ({tmpdst} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	698 dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst, mask = ((1 << prog.sizeAdjust) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	699 ))
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	700 prog.sizeAdjust = None
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	701 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	702 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	703 prog.carryFlowDst = None
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	704 if parity:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	705 if paritySize > 8:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	706 if paritySize > 16:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	707 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	708 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	709 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	710 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	711 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	712 if type(parity) is tuple:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	713 reg,bit = parity
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	714 reg = prog.resolveParam(reg, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	715 output.append('\n\t{flag} = ({flag} & ~{mask}U) \| ((0x6996 >> {parity}) << {bit} & {mask}U);'.format(
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	716 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	717 ))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	718 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	719 reg = prog.resolveParam(parity, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	720 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	721
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	722 #TODO: combine explicit flags targeting the same storage location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	723 for flag in explicit:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	724 _addExplicitFlagSet(prog, output, flag, explicit[flag])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	725 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	726
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	727 def _cmpCImpl(prog, params, rawParams, flagUpdates):
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	728 b_size = size = prog.paramSize(rawParams[1])
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	729 needsCarry = False
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	730 if flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	731 for flag in flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	732 calc = prog.flags.flagCalc[flag]
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	733 if calc == 'carry':
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	734 needsCarry = True
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	735 break
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	736 if len(params) > 2:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	737 size = params[2]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	738 if size == 0:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	739 size = 8
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	740 elif size == 1:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	741 size = 16
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	742 else:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	743 size = 32
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	744 prog.lastSize = size
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	745 if needsCarry:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	746 size *= 2
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	747 tmpvar = 'cmp_tmp{sz}__'.format(sz=size)
1745 a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	748 if flagUpdates:
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	749 prog.carryFlowDst = tmpvar
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	750 prog.lastA = params[1]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	751 prog.lastB = params[0]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	752 prog.lastBFlow = params[0]
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	753 scope = prog.getRootScope()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	754 if not scope.resolveLocal(tmpvar):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	755 scope.addLocal(tmpvar, size)
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	756 prog.lastDst = rawParams[1]
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	757 a = params[0]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	758 b = params[1]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	759 a_size = prog.paramSize(rawParams[0])
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	760 if prog.lastSize != a_size:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	761 a = '(({a}) & {mask})'.format(a = a, mask = (1 << prog.lastSize) - 1)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	762 if prog.lastSize != b_size:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	763 b = '(({b}) & {mask})'.format(b = b, mask = (1 << prog.lastSize) - 1)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	764 if size == 64:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	765 a = '((uint64_t){a})'.format(a = a)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	766 b = '((uint64_t){b})'.format(b = b)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	767 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = a, b = b)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	768
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	769 def _asrCImpl(prog, params, rawParams, flagUpdates):
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	770 needsCarry = False
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	771 if flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	772 for flag in flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	773 calc = prog.flags.flagCalc[flag]
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	774 if calc == 'carry':
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	775 needsCarry = True
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	776 decl = ''
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	777 needsSizeAdjust = False
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	778 destSize = prog.paramSize(rawParams[2])
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	779 if len(params) > 3:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	780 size = params[3]
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	781 if size == 0:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	782 size = 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	783 elif size == 1:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	784 size = 16
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	785 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	786 size = 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	787 prog.lastSize = size
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	788 if destSize > size:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	789 needsSizeAdjust = True
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	790 prog.sizeAdjust = size
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	791 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	792 size = destSize
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	793 mask = 1 << (size - 1)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	794 if needsCarry:
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	795 decl,name = prog.getTemp(size)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	796 dst = prog.carryFlowDst = name
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	797 prog.lastA = params[0]
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	798 prog.lastB = params[1]
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	799 if needsSizeAdjust:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	800 sizeMask = (1 << size) - 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	801 return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format(
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	802 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	803 elif needsSizeAdjust:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	804 decl,name = prog.getTemp(size)
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	805 sizeMask = (1 << size) - 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	806 return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' +
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	807 '\n\t{dst} = ({dst} & ~{sizeMask}) \| {name};').format(
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	808 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	809 else:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	810 dst = params[2]
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	811
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	812 return decl + '\n\t{dst} = ({a} >> {b}) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	813 a = params[0], b = params[1], dst = dst, mask = mask, size=size)
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	814
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	815 def _sext(size, src):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	816 if size == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	817 return src \| 0xFF00 if src & 0x80 else src & 0x7F
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	818 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	819 return src \| 0xFFFF0000 if src & 0x8000 else src & 0x7FFF
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	820
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	821 def _sextCImpl(prog, params, rawParms):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	822 if params[0] == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	823 fmt = '\n\t{dst} = {src} & 0x80 ? {src} \| 0xFF00 : {src} & 0x7F;'
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	824 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	825 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} \| 0xFFFF0000 : {src} & 0x7FFF;'
2468 0ca78837e4d2 Implement ext instruction in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2463 diff changeset	826 prog.lastSize = params[0]
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	827 return fmt.format(src=params[1], dst=params[2])
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	828
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	829 def _mulsCImpl(prog, params, rawParams, flagUpdates):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	830 p0Size = prog.paramSize(rawParams[0])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	831 p1Size = prog.paramSize(rawParams[1])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	832 destSize = prog.paramSize(rawParams[2])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	833 if len(params) > 3:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	834 size = params[3]
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	835 if size == 0:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	836 size = 8
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	837 elif size == 1:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	838 size = 16
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	839 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	840 size = 32
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	841 prog.lastSize = size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	842 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	843 size = destSize
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	844 if p0Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	845 p0Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	846 if p1Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	847 p1Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	848 #TODO: Handle case in which destSize > size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	849 return f'\n\t{params[2]} = (int{size}_t)(((int{p0Size}_t){params[0]}) * ((int{p1Size}_t){params[1]}));'
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	850
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	851 def _muluCImpl(prog, params, rawParams, flagUpdates):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	852 p0Size = prog.paramSize(rawParams[0])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	853 p1Size = prog.paramSize(rawParams[1])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	854 destSize = prog.paramSize(rawParams[2])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	855 if len(params) > 3:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	856 size = params[3]
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	857 if size == 0:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	858 size = 8
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	859 elif size == 1:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	860 size = 16
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	861 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	862 size = 32
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	863 prog.lastSize = size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	864 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	865 size = destSize
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	866 if p0Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	867 p0Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	868 if p1Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	869 p1Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	870 #TODO: Handle case in which destSize > size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	871 return f'\n\t{params[2]} = ((uint{p0Size}_t){params[0]}) * ((uint{p1Size}_t){params[1]});'
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	872
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	873 def _getCarryCheck(prog):
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	874 carryFlag = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	875 for flag in prog.flags.flagOrder:
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	876 if prog.flags.flagCalc[flag] == 'carry':
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	877 carryFlag = flag
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	878 break
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	879 if carryFlag is None:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	880 raise Exception('adc requires a defined carry flag')
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	881 carryStorage = prog.flags.getStorage(carryFlag)
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	882 if type(carryStorage) is tuple:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	883 reg,bit = carryStorage
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	884 reg = prog.resolveReg(reg, None, (), False)
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	885 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	886 else:
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	887 return prog.resolveReg(carryStorage, None, (), False)
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	888
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	889 def _adcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	890 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	891 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	892 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	893 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	894 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	895 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	896 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	897 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	898 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	899 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	900 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	901 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	902 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	903 prog.sizeAdjust = size
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	904 needsCarry = needsOflow = needsHalf = False
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	905 if flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	906 for flag in flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	907 calc = prog.flags.flagCalc[flag]
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	908 if calc == 'carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	909 needsCarry = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	910 elif calc == 'half-carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	911 needsHalf = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	912 elif calc == 'overflow':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	913 needsOflow = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	914 decl = ''
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	915 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	916 vals = '1 : 0'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	917 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	918 if len(params) <= 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	919 size = prog.paramSize(rawParams[2])
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	920 if needsCarry:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	921 size *= 2
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	922 decl,name = prog.getTemp(size)
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	923 dst = prog.carryFlowDst = name
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	924 prog.lastA = params[0]
1744 91aa789e57bd Fixed half-carry flag calcuation for adc/sbc in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1742 diff changeset	925 prog.lastB = params[1]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	926 prog.lastBFlow = '(~{b})'.format(b=params[1])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	927 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	928 params[0] = '((uint64_t){a})'.format(a=params[0])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	929 params[1] = '((uint64_t){b})'.format(b=params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	930 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	931 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	932 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	933 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	934 return '{decl}\n\t{tmp} = ({a} & {mask}) + ({b} & {mask}) + ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	935 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	936 )
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	937 else:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	938 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	939 return decl + '\n\t{dst} = {a} + {b} + ({check} ? {vals});'.format(dst = dst,
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	940 a = params[0], b = params[1], check = carryCheck, vals = vals
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	941 )
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	942
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	943 def _sbcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	944 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	945 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	946 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	947 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	948 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	949 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	950 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	951 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	952 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	953 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	954 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	955 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	956 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	957 prog.sizeAdjust = size
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	958 needsCarry = needsOflow = needsHalf = False
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	959 if flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	960 for flag in flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	961 calc = prog.flags.flagCalc[flag]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	962 if calc == 'carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	963 needsCarry = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	964 elif calc == 'half-carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	965 needsHalf = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	966 elif calc == 'overflow':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	967 needsOflow = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	968 decl = ''
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	969 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	970 vals = '1 : 0'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	971 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	972 size = prog.paramSize(rawParams[2])
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	973 if needsCarry:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	974 size *= 2
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	975 decl,name = prog.getTemp(size)
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	976 dst = prog.carryFlowDst = name
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	977 prog.lastA = params[1]
1744 91aa789e57bd Fixed half-carry flag calcuation for adc/sbc in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1742 diff changeset	978 prog.lastB = params[0]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	979 prog.lastBFlow = params[0]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	980 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	981 params[1] = '((uint64_t){a})'.format(a=params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	982 params[0] = '((uint64_t){b})'.format(b=params[0])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	983 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	984 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	985 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	986 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	987 return '{decl}\n\t{tmp} = ({b} & {mask}) - ({a} & {mask}) - ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
2589 6bca3c28e2ad Low confidence fix for edge case in CPU DSL not currently hit Michael Pavone <pavone@retrodev.com> parents: 2587 diff changeset	988 decl = decl, tmp = name, a = params[0], b = params[1], dst = dst, mask = ((1 << size) - 1), check = carryCheck
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	989 )
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	990 else:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	991 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	992 return decl + '\n\t{dst} = {b} - {a} - ({check} ? {vals});'.format(dst = dst,
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	993 a = params[0], b = params[1], check=_getCarryCheck(prog), vals = vals
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	994 )
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	995
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	996 def _rolCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	997 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	998 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	999 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1000 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1001 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1002 needsCarry = True
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1003 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1004 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1005 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1006 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1007 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1008 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1009 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1010 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1011 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1012 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1013 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1014 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1015 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1016 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1017 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1018 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1019 size = destSize
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1020 rotMask = size - 1
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1021 if type(params[1]) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1022 b = params[1] & rotMask
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1023 mdecl = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1024 ret = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1025 else:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1026 mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1027 ret = f'\n\t{b} = {params[1]} & {rotMask};'
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1028 prog.lastB = b
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1029 prog.lastBUnmasked = params[1]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1030 if needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1031 decl,name = prog.getTemp(size)
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1032 mdecl += decl
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1033 dst = prog.carryFlowDst = name
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1034 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1035 dst = params[2]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1036 ret += '\n\t{dst} = {a} << {b} \| {a} >> ({size} - {b});'.format(dst = dst,
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1037 a = params[0], b = b, size=size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1038 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1039 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1040 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1041 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1042 return mdecl + ret
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1043
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1044 def _rlcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1045 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1046 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1047 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1048 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1049 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1050 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1051 decl = ''
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1052 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1053 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1054 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1055 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1056 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1057 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1058 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1059 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1060 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1061 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1062 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1063 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1064 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1065 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1066 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1067 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1068 size = destSize
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1069 carryCheck = _getCarryCheck(prog)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1070 size = prog.paramSize(rawParams[2])
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1071 if needsCarry or needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1072 decl,name = prog.getTemp(size)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1073 dst = prog.carryFlowDst = name
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1074 prog.lastA = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1075 prog.lastB = params[1]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1076 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1077 dst = params[2]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1078 if size == 32 and (not type(params[1]) is int) or params[1] <= 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1079 # we may need to shift by 32-bits which is too much for a normal int
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1080 a = f'((uint64_t){params[0]})'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1081 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1082 a = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1083 ret = decl + '\n\t{dst} = {a} << {b} \| {a} >> ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst,
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1084 a = a, b = params[1], size=size, check=carryCheck
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1085 )
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1086 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1087 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1088 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1089 return ret
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1090
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1091 def _rorCImpl(prog, params, rawParams, flagUpdates):
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1092 needsCarry = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1093 if flagUpdates:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1094 for flag in flagUpdates:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1095 calc = prog.flags.flagCalc[flag]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1096 if calc == 'carry':
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1097 needsCarry = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1098 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1099 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1100 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1101 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1102 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1103 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1104 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1105 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1106 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1107 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1108 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1109 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1110 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1111 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1112 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1113 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1114 size = destSize
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1115 rotMask = size - 1
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1116 if type(params[1]) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1117 b = params[1] & rotMask
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1118 mdecl = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1119 ret = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1120 else:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1121 mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1122 ret = f'\n\t{b} = {params[1]} & {rotMask};'
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1123 prog.lastB = b
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1124 prog.lastBUnmasked = params[1]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1125 if needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1126 decl,name = prog.getTemp(size)
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1127 dst = prog.carryFlowDst = name
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1128 mdecl += decl
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1129 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1130 dst = params[2]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1131 ret += '\n\t{dst} = {a} >> {b} \| {a} << ({size} - {b});'.format(dst = dst,
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1132 a = params[0], b = b, size=size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1133 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1134 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1135 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1136 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1137 return mdecl + ret
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1138
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1139 def _rrcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1140 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1141 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1142 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1143 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1144 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1145 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1146 decl = ''
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1147 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1148 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1149 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1150 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1151 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1152 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1153 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1154 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1155 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1156 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1157 prog.lastSize = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1158 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1159 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1160 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1161 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1162 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1163 size = destSize
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1164 carryCheck = _getCarryCheck(prog)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1165 size = prog.paramSize(rawParams[2])
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1166 if needsCarry or needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1167 decl,name = prog.getTemp(size)
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1168 dst = prog.carryFlowDst = name
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1169 prog.lastA = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1170 prog.lastB = params[1]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1171 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1172 dst = params[2]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1173 if size == 32 and (not type(params[1]) is int) or params[1] <= 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1174 # we may need to shift by 32-bits which is too much for a normal int
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1175 a = f'((uint64_t){params[0]})'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1176 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1177 a = params[0]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1178 ret = decl + '\n\t{dst} = {a} >> {b} \| {a} << ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst,
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1179 a = a, b = params[1], size=size, check=carryCheck
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1180 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1181 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1182 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1183 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1184 return ret
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1185
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1186 def _updateSyncCImpl(prog, params):
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1187 return '\n\t{sync}(context, target_cycle);'.format(sync=prog.sync_cycle)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	1188
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1189 _opMap = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1190 'mov': Op(lambda val: val).cUnaryOperator(''),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1191 'not': Op(lambda val: ~val).cUnaryOperator('~'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1192 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1193 'neg': Op(lambda val: -val).cUnaryOperator('-'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1194 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	1195 'adc': Op().addImplementation('c', 2, _adcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1196 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	1197 'sbc': Op().addImplementation('c', 2, _sbcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1198 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1199 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1200 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1201 'rol': Op().addImplementation('c', 2, _rolCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1202 'rlc': Op().addImplementation('c', 2, _rlcCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1203 'ror': Op().addImplementation('c', 2, _rorCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1204 'rrc': Op().addImplementation('c', 2, _rrcCImpl),
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1205 'mulu': Op(lambda a, b: a * b).addImplementation('c', 2, _muluCImpl),
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1206 'muls': Op().addImplementation('c', 2, _mulsCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1207 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1208 'or': Op(lambda a, b: a \| b).cBinaryOperator('\|'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1209 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1210 'abs': Op(lambda val: abs(val)).addImplementation(
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1211 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1212 ),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1213 'cmp': Op().addImplementation('c', None, _cmpCImpl),
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	1214 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1215 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1216 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1217 )),
2587 e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1218 'ccall': Op().addImplementation('c', None, lambda prog, params: '\n\t{fun}({args});'.format(
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1219 pre = prog.prefix, fun = params[0], args = ', '.join([str(p) for p in params[1:]])
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1220 )),
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1221 'pcall': Op().addImplementation('c', None, lambda prog, params: '\n\t(({typ}){fun})({args});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1222 typ = params[1], fun = params[0], args = ', '.join([str(p) for p in params[2:]])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1223 )),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1224 'cycles': Op().addImplementation('c', None,
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1225 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1226 params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1227 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1228 ),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1229 'addsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1230 lambda a, b: b + (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1231 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + ({sz} ? {sz} * 2 : 1);'.format(
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1232 dst = params[2], sz = params[0], val = params[1]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1233 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1234 'decsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1235 lambda a, b: b - (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1236 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - ({sz} ? {sz} * 2 : 1);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1237 dst = params[2], sz = params[0], val = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1238 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1239 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1240 'dispatch': Op().addImplementation('c', None, _dispatchCImpl),
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1241 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl),
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1242 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1243 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1244
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1245 #represents a simple DSL instruction
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1246 class NormalOp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1247 def __init__(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1248 self.op = parts[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1249 self.params = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1250
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1251 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1252 procParams = []
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1253 allParamsConst = flagUpdates is None and not prog.conditional
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1254 opDef = _opMap.get(self.op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1255 for param in self.params:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1256 isDst = (not opDef is None) and len(procParams) in opDef.outOp
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1257 allowConst = (self.op in prog.subroutines or not isDst) and param in parent.regValues
1765 7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1258 if isDst and self.op == 'xchg':
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1259 #xchg uses its regs as both source and destination
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1260 #we need to resolve as both so that disperse/coalesce flag stuff gets done
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	1261 prog.resolveParam(param, parent, fieldVals, allowConst, False)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1262 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1263
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1264 if (not type(param) is int) and len(procParams) != len(self.params) - 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1265 allParamsConst = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1266 procParams.append(param)
2587 e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1267 if prog.needFlagCoalesce:
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1268 output.append(prog.flags.coalesceFlags(prog, otype))
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1269 prog.needFlagCoalesce = False
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1270
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1271 if self.op == 'meta':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1272 param,_,index = self.params[1].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1273 if index:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1274 index = (parent.resolveLocal(index) or index)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1275 if index in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1276 index = str(fieldVals[index])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1277 param = param + '.' + index
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1278 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1279 param = parent.resolveLocal(param) or param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1280 if param in fieldVals:
1991 7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core Michael Pavone <pavone@retrodev.com> parents: 1938 diff changeset	1281 param = fieldVals[param]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1282 prog.meta[self.params[0]] = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1283 elif self.op == 'dis':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1284 #TODO: Disassembler
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1285 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1286 elif not opDef is None:
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1287 if opDef.numParams() > len(procParams):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1288 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1289 if opDef.canEval() and allParamsConst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1290 #do constant folding
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1291 if opDef.numArgs() >= len(procParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1292 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1293 dst = self.params[opDef.numArgs()]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1294 result = opDef.evaluate(procParams[:opDef.numArgs()])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1295 while dst in prog.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1296 dst = prog.meta[dst]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1297 maybeLocal = parent.resolveLocal(dst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1298 if maybeLocal:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1299 dst = maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1300 parent.regValues[dst] = result
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1301 if prog.isReg(dst):
2497 95d9809a3973 Fix constant propagation for sext instruction Michael Pavone <pavone@retrodev.com> parents: 2478 diff changeset	1302 shortProc = (result, procParams[-1])
95d9809a3973 Fix constant propagation for sext instruction Michael Pavone <pavone@retrodev.com> parents: 2478 diff changeset	1303 shortParams = (result, self.params[-1])
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1304 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1305 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1306 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
1728 b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1307 for dstIdx in opDef.outOp:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1308 dst = self.params[dstIdx]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1309 while dst in prog.meta:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1310 dst = prog.meta[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1311 if dst in parent.regValues:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1312 del parent.regValues[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1313
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1314 elif self.op in prog.subroutines:
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1315 procParams = []
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1316 for param in self.params:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1317 begin,sep,end = param.partition('.')
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1318 if sep:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1319 if end in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1320 param = begin + '.' + str(fieldVals[end])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1321 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1322 if param in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1323 param = fieldVals[param]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1324 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1325 maybeLocal = parent.resolveLocal(param)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1326 if maybeLocal and maybeLocal in parent.regValues:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1327 param = parent.regValues[maybeLocal]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1328 procParams.append(param)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1329 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1330 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1331 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1332 prog.lastOp = self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1333
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1334 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1335 if self.op == 'dispatch' and (len(self.params) == 1 or self.params[1] == 'main'):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1336 prog.mainDispatch.add(self.params[0])
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1337
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1338 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1339 return '\n\t' + self.op + ' ' + ' '.join(self.params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1340
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1341 #represents a DSL switch construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1342 class Switch(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1343 def __init__(self, parent, param):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1344 self.op = 'switch'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1345 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1346 self.param = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1347 self.cases = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1348 self.regValues = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1349 self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1350 self.case_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1351 self.current_case = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1352 self.default = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1353 self.default_locals = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1354
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1355 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1356 if op.op == 'case':
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1357 if op.params[0].startswith('0x'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1358 val = int(op.params[0], 16)
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1359 elif op.params[0].startswith('0b'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1360 val = int(op.params[0], 2)
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1361 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1362 val = int(op.params[0])
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1363 self.cases[val] = self.current_case = []
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1364 self.case_locals[val] = self.current_locals = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1365 elif op.op == 'default':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1366 self.default = self.current_case = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1367 self.default_locals = self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1368 elif self.current_case == None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1369 raise ion('Orphan instruction in switch')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1370 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1371 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1372 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1373 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1374 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1375 self.current_case.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1376
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1377 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1378 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1379 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1380 return self.parent.resolveLocal(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1381
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1382 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1383 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1384
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1385 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1386 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1387 return self.current_locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1388 return self.parent.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1389
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1390 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1391 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1392 param = prog.resolveParam(self.param, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1393 if type(param) is int:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1394 self.regValues = self.parent.regValues
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1395 if param in self.cases:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1396 self.current_locals = self.case_locals[param]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1397 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1398 for local in self.case_locals[param]:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1399 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1400 self.processOps(prog, fieldVals, output, otype, self.cases[param])
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1401 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1402 elif self.default:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1403 self.current_locals = self.default_locals
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1404 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1405 for local in self.default_locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1406 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1407 self.processOps(prog, fieldVals, output, otype, self.default)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1408 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1409 else:
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1410 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1411 prog.conditional = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1412 output.append('\n\tswitch(' + param + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1413 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1414 for case in self.cases:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1415 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1416 self.current_locals = self.case_locals[case]
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1417 self.regValues = dict(self.parent.regValues)
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1418 output.append('\n\tcase {0}U: '.format(case) + '{')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1419 for local in self.case_locals[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1420 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1421 self.processOps(prog, fieldVals, output, otype, self.cases[case])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1422 output.append('\n\tbreak;')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1423 output.append('\n\t}')
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1424 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1425 if self.default:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1426 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1427 self.current_locals = self.default_locals
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1428 self.regValues = dict(self.parent.regValues)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1429 output.append('\n\tdefault: {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1430 for local in self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1431 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1432 self.processOps(prog, fieldVals, output, otype, self.default)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1433 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1434 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1435 prog.conditional = oldCond
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1436 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1437
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1438 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1439 for case in self.cases:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1440 for op in self.cases[case]:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1441 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1442 if self.default:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1443 for op in self.default:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1444 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1445
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1446 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1447 keys = self.cases.keys()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1448 keys.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1449 lines = ['\n\tswitch']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1450 for case in keys:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1451 lines.append('\n\tcase {0}'.format(case))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1452 lines.append(''.join([str(op) for op in self.cases[case]]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1453 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1454 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1455
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1456
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1457 def _geuCImpl(prog, parent, fieldVals, output):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1458 if prog.lastOp.op == 'cmp':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1459 output.pop()
1616 8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1460 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1461 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{'
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1462 else:
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1463 raise Exception(">=U not implemented in the general case yet")
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1464
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1465 def _eqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1466 if prog.lastOp.op == 'cmp':
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1467 output.pop()
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1468 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1469 return '\n\tif ({a} == {b}) '.format(a=params[1], b = params[0]) + '{'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1470 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1471 return '\n\tif (!{a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1472
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1473 def _neqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1474 return '\n\tif ({a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1475
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1476 _ifCmpImpl = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1477 'c': {
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1478 '>=U': _geuCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1479 '=': _eqCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1480 '!=': _neqCImpl
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1481 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1482 }
2452 8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1483 _ifCmpEval = {
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1484 '>=U': lambda a, b: a >= b,
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1485 '=': lambda a, b: a == b,
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1486 '!=': lambda a, b: a != b
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1487 }
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1488 #represents a DSL conditional construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1489 class If(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1490 def __init__(self, parent, cond):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1491 self.op = 'if'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1492 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1493 self.cond = cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1494 self.body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1495 self.elseBody = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1496 self.curBody = self.body
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1497 self.locals = {}
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1498 self.elseLocals = {}
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1499 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1500 self.regValues = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1501
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1502 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1503 if op.op in ('case', 'arg'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1504 raise Exception(self.op + ' is not allows inside an if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1505 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1506 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1507 size = op.params[1]
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1508 self.curLocals[name] = size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1509 elif op.op == 'else':
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1510 self.curLocals = self.elseLocals
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1511 self.curBody = self.elseBody
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1512 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1513 self.curBody.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1514
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1515 def localSize(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1516 return self.curLocals.get(name)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1517
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1518 def resolveLocal(self, name):
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1519 if name in self.curLocals:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1520 return name
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1521 return self.parent.resolveLocal(name)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1522
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1523 def _genTrueBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1524 self.curLocals = self.locals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1525 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1526 self.processOps(prog, fieldVals, subOut, otype, self.body)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1527 for local in self.locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1528 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1529 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1530
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1531 def _genFalseBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1532 self.curLocals = self.elseLocals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1533 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1534 self.processOps(prog, fieldVals, subOut, otype, self.elseBody)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1535 for local in self.elseLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1536 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1537 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1538
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1539 def _genConstParam(self, param, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1540 if param:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1541 self._genTrueBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1542 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1543 self._genFalseBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1544
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1545 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1546 self.regValues = parent.regValues
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1547 if self.cond in prog.booleans:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1548 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1549 else:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1550 if self.cond in _ifCmpImpl[otype]:
2452 8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1551 if prog.lastOp.op == 'cmp':
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1552 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1553 if type(params[0]) is int and type(params[1]) is int:
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1554 output.pop()
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1555 res = _ifCmpEval[self.cond](params[1], params[0])
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1556 self._genConstParam(res, prog, fieldVals, output, otype)
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1557 return
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1558 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1559 prog.conditional = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1560 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1561 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1562 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1563 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1564 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1565 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1566 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1567 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1568 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1569 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1570 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1571 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1572 cond = prog.resolveParam(self.cond, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1573 if type(cond) is int:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1574 self._genConstParam(cond, prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1575 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1576 #temp = prog.temp.copy()
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1577 output.append('\n\tif ({cond}) '.format(cond=cond) + '{')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1578 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1579 prog.conditional = True
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1580 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1581 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1582 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1583 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1584 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1585 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1586 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1587 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1588 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1589
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1590
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1591 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1592 for op in self.body:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1593 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1594 for op in self.elseBody:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1595 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1596
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1597 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1598 lines = ['\n\tif']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1599 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1600 lines.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1601 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1602 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1603
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1604 class Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1605 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1606 self.regs = {}
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1607 self.pointers = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1608 self.regArrays = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1609 self.regToArray = {}
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1610 self.addReg('cycles', 32)
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1611 self.addReg('sync_cycle', 32)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1612
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1613 def addReg(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1614 self.regs[name] = size
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1615
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1616 def addPointer(self, name, size, count):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1617 self.pointers[name] = (size, count)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1618
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1619 def addRegArray(self, name, size, regs):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1620 self.regArrays[name] = (size, regs)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1621 idx = 0
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1622 if not type(regs) is int:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1623 for reg in regs:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1624 self.regs[reg] = size
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1625 self.regToArray[reg] = (name, idx)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1626 idx += 1
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1627
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1628 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1629 return name in self.regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1630
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1631 def isRegArray(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1632 return name in self.regArrays
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1633
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1634 def isRegArrayMember(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1635 return name in self.regToArray
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1636
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1637 def arrayMemberParent(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1638 return self.regToArray[name][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1639
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1640 def arrayMemberIndex(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1641 return self.regToArray[name][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1642
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1643 def arrayMemberName(self, array, index):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1644 if type(index) is int and not type(self.regArrays[array][1]) is int:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1645 return self.regArrays[array][1][index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1646 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1647 return None
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1648
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1649 def isNamedArray(self, array):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1650 return array in self.regArrays and type(self.regArrays[array][1]) is int
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1651
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1652 def processLine(self, parts):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1653 if len(parts) == 3:
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1654 if parts[1].startswith('ptr'):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1655 self.addPointer(parts[0], parts[1][3:], int(parts[2]))
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1656 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1657 self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1658 elif len(parts) > 2:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1659 self.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1660 else:
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1661 if parts[1].startswith('ptr'):
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1662 self.addPointer(parts[0], parts[1][3:], 1)
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1663 else:
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1664 self.addReg(parts[0], int(parts[1]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1665 return self
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1666
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1667 def writeHeader(self, otype, hFile):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1668 fieldList = []
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1669 for pointer in self.pointers:
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1670 stars = '*'
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1671 ptype, count = self.pointers[pointer]
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1672 while ptype.startswith('ptr'):
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1673 stars += '*'
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1674 ptype = ptype[3:]
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1675 if ptype.isdigit():
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1676 ptype = 'uint{sz}_t'.format(sz=ptype)
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1677 if count > 1:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1678 arr = '[{n}]'.format(n=count)
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1679 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1680 arr = ''
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1681 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1682 for reg in self.regs:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1683 if not self.isRegArrayMember(reg):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1684 fieldList.append((self.regs[reg], 1, reg))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1685 for arr in self.regArrays:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1686 size,regs = self.regArrays[arr]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1687 if not type(regs) is int:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1688 regs = len(regs)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1689 fieldList.append((size, regs, arr))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1690 fieldList.sort()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1691 fieldList.reverse()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1692 for size, count, name in fieldList:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1693 if count > 1:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1694 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1695 else:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1696 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1697
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1698 class Flags:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1699 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1700 self.flagBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1701 self.flagCalc = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1702 self.flagStorage = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1703 self.flagOrder = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1704 self.flagReg = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1705 self.storageToFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1706 self.maxBit = -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1707
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1708 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1709 if parts[0] == 'register':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1710 self.flagReg = parts[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1711 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1712 flag,bit,calc,storage = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1713 bit,_,top = bit.partition('-')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1714 bit = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1715 if top:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1716 top = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1717 if top > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1718 self.maxBit = top
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1719 self.flagBits[flag] = (bit,top)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1720 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1721 if bit > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1722 self.maxBit = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1723 self.flagBits[flag] = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1724 self.flagCalc[flag] = calc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1725 self.flagStorage[flag] = storage
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1726 storage,_,storebit = storage.partition('.')
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1727 self.storageToFlags.setdefault(storage, []).append((storebit, flag))
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1728 self.flagOrder.append(flag)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1729 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1730
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1731 def getStorage(self, flag):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1732 if not flag in self.flagStorage:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1733 raise Exception('Undefined flag ' + flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1734 loc,_,bit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1735 if bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1736 return (loc, int(bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1737 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1738 return loc
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1739
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1740 def parseFlagUpdate(self, flagString):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1741 last = ''
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1742 autoUpdate = set()
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1743 explicit = {}
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1744 for c in flagString:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1745 if c.isdigit():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1746 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1747 num = int(c)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1748 if num > 1:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1749 raise Exception(c + ' is not a valid digit for update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1750 explicit[last] = num
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1751 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1752 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1753 raise Exception('Digit must follow flag letter in update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1754 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1755 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1756 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1757 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1758 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1759 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1760 return (autoUpdate, explicit)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1761
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1762 def disperseFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1763 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1764 src = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1765 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1766 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1767 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1768 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1769 bot,top = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1770 mask = ((1 << (top + 1 - bot)) - 1) << bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1771 output.append('\n\t{dst} = {src} & mask;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1772 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1773 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1774 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1775 bitToFlag[self.flagBits[flag]] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1776 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1777 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1778 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1779 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1780 field,_,dstbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1781 dst = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1782 if dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1783 dstbit = int(dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1784 multi.setdefault(dst, []).append((dstbit, bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1785 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1786 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1787 for dst in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1788 didClear = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1789 direct = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1790 for dstbit, bit in multi[dst]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1791 if dstbit == bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1792 direct.append(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1793 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1794 if not didClear:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1795 output.append('\n\t{dst} = 0;'.format(dst=dst))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1796 didClear = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1797 if dstbit > bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1798 shift = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1799 diff = dstbit - bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1800 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1801 shift = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1802 diff = bit - dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1803 output.append('\n\t{dst} \|= {src} {shift} {diff} & {mask};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1804 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1805 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1806 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1807 if len(direct) == len(multi[dst]):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1808 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1809 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1810 mask = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1811 for bit in direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1812 mask = mask \| (1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1813 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1814 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1815
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1816 def coalesceFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1817 dst = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1818 output = ['\n\t{dst} = 0;'.format(dst=dst)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1819 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1820 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1821 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1822 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1823 bot,_ = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1824 src = prog.resolveReg(self.flagStorage[flag], None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1825 if bot:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1826 output.append('\n\t{dst} \|= {src} << {shift};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1827 dst=dst, src = src, shift = bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1828 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1829 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1830 output.append('\n\t{dst} \|= {src};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1831 dst=dst, src = src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1832 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1833 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1834 bitToFlag[bit] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1835 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1836 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1837 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1838 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1839 field,_,srcbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1840 src = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1841 if srcbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1842 srcbit = int(srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1843 multi.setdefault(src, []).append((srcbit,bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1844 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1845 output.append('\n\tif ({src}) {{\n\t\t{dst} \|= 1 << {bit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1846 dst=dst, src=src, bit=bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1847 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1848 for src in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1849 direct = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1850 for srcbit, dstbit in multi[src]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1851 if srcbit == dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1852 direct = direct \| (1 << srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1853 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1854 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} \|= 1 << {dstbit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1855 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1856 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1857 if direct:
1698 90272218469c Fixed missing semicolon in coalesceFlags Michael Pavone <pavone@retrodev.com> parents: 1697 diff changeset	1858 output.append('\n\t{dst} \|= {src} & {mask};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1859 dst=dst, src=src, mask=direct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1860 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1861 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1862
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1863
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1864 class Program:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1865 def __init__(self, regs, instructions, subs, info, flags):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1866 self.regs = regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1867 self.instructions = instructions
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1868 self.subroutines = subs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1869 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1870 self.booleans = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1871 self.prefix = info.get('prefix', [''])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1872 self.opsize = int(info.get('opcode_size', ['8'])[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1873 self.extra_tables = info.get('extra_tables', [])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1874 self.context_type = self.prefix + 'context'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1875 self.body = info.get('body', [None])[0]
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1876 self.interrupt = info.get('interrupt', [None])[0]
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1877 self.sync_cycle = info.get('sync_cycle', [None])[0]
1620 a172f97d873f Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16 Michael Pavone <pavone@retrodev.com> parents: 1619 diff changeset	1878 self.includes = info.get('include', [])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1879 self.flags = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1880 self.lastDst = None
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1881 self.scopes = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1882 self.currentScope = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1883 self.lastOp = None
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1884 self.carryFlowDst = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1885 self.lastA = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1886 self.lastB = None
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	1887 self.lastBFlow = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1888 self.sizeAdjust = None
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1889 self.conditional = False
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1890 self.declares = []
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1891 self.lastSize = None
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1892 self.mainDispatch = set()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1893
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1894 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1895 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1896 for reg in self.regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1897 pieces.append(str(self.regs[reg]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1898 for name in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1899 pieces.append('\n'+str(self.subroutines[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1900 for instruction in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1901 pieces.append('\n'+str(instruction))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1902 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1903
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1904 def writeHeader(self, otype, header):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1905 hFile = open(header, 'w')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1906 macro = header.upper().replace('.', '_')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1907 hFile.write('#ifndef {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1908 hFile.write('\n#define {0}_'.format(macro))
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	1909 hFile.write('\n#include <stdio.h>')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1910 hFile.write('\n#include "backend.h"')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1911 hFile.write(f'\n\ntypedef struct {self.prefix}options {self.prefix}options;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1912 hFile.write(f'\n\ntypedef struct {self.prefix}context {self.prefix}context;')
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1913 for decl in self.declares:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2497 diff changeset	1914 if decl.startswith('define '):
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2497 diff changeset	1915 decl = '#' + decl
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1916 hFile.write('\n' + decl)
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1917 hFile.write(f'\n\nstruct {self.prefix}options {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1918 hFile.write('\n\tcpu_options gen;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1919 hFile.write('\n\tFILE* address_log;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1920 hFile.write('\n};')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1921 hFile.write(f'\n\nstruct {self.prefix}context {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1922 hFile.write(f'\n\t{self.prefix}options *opts;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1923 self.regs.writeHeader(otype, hFile)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1924 hFile.write('\n};')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1925 hFile.write('\n')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1926 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1927 hFile.write('\n#endif //{0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1928 hFile.write('\n')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1929 hFile.close()
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1930
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1931 def _buildTable(self, otype, table, body, lateBody):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1932 pieces = []
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1933 opmap = [None] * (1 << self.opsize)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1934 bodymap = {}
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1935 if table in self.instructions:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1936 instructions = self.instructions[table]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1937 instructions.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1938 for inst in instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1939 for val in inst.allValues():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1940 if opmap[val] is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1941 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1942 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1943 self.needFlagCoalesce = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1944 self.needFlagDisperse = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1945 self.lastOp = None
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1946 name = inst.generateName(val)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1947 opmap[val] = name
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1948 if not name in bodymap:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1949 bodymap[name] = inst.generateBody(val, self, otype)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1950
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1951 alreadyAppended = set()
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1952 if self.dispatch == 'call':
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1953 lateBody.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1954 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1955 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1956 if op is None:
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1957 lateBody.append('\n\tunimplemented,')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1958 else:
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1959 lateBody.append('\n\t' + op + ',')
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1960 if not op in alreadyAppended:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1961 body.append(bodymap[op])
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1962 alreadyAppended.add(op)
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	1963 lateBody.append('\n};')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1964 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1965 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1966 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1967 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1968 if op is None:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1969 body.append('\n\t\t&&unimplemented,')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1970 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1971 body.append('\n\t\t&&' + op + ',')
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1972 if not op in alreadyAppended:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1973 lateBody.append(bodymap[op])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1974 body.append('\n\t};')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1975 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1976 raise Exception("unimplmeneted dispatch type " + self.dispatch)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1977 body.extend(pieces)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1978
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1979 def nextInstruction(self, otype):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1980 output = []
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1981 if self.dispatch == 'goto':
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1982 if self.interrupt in self.subroutines:
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1983 output.append('\n\tif (context->cycles >= context->sync_cycle) {')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1984 output.append('\n\tif (context->cycles >= target_cycle) { return; }')
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1985 if self.interrupt in self.subroutines:
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1986 self.meta = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1987 self.temp = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1988 self.subroutines[self.interrupt].inline(self, [], output, otype, None)
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1989 output.append('\n\t}')
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1990
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1991 self.meta = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1992 self.temp = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1993 self.subroutines[self.body].inline(self, [], output, otype, None)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1994 return output
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1995
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1996 def build(self, otype):
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1997 body = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1998 pieces = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1999 for include in self.includes:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2000 body.append('#include "{0}"\n'.format(include))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2001 if self.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2002 body.append('\ntypedef void (impl_fun)({pre}context context, uint32_t target_cycle);'.format(pre=self.prefix))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2003 for table in self.extra_tables:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2004 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2005 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2006 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2007 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2008 body.append('\n{')
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2009
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2010 for table in self.instructions:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2011 for inst in self.instructions[table]:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2012 inst.processDispatch(self)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2013 for sub in self.subroutines:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2014 self.subroutines[sub].processDispatch(self)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2015
1740 28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL Michael Pavone <pavone@retrodev.com> parents: 1737 diff changeset	2016 for table in self.extra_tables:
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2017 self._buildTable(otype, table, body, pieces)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2018 self._buildTable(otype, 'main', body, pieces)
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2019 if self.dispatch == 'call':
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2020 if self.body in self.subroutines:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2021 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2022 pieces.append('\n{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2023 pieces.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2024 pieces.append('\n\twhile (context->cycles < target_cycle)')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2025 pieces.append('\n\t{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2026 if self.interrupt in self.subroutines:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2027 pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2028 pieces.append(f'\n\t\t\t{self.sync_cycle}(context, target_cycle);')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2029 pieces.append('\n\t\t}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2030 self.meta = {}
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2031 self.temp = {}
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2032 intpieces = []
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2033 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2034 for size in self.temp:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2035 pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2036 pieces += intpieces
1883 9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	2037 self.meta = {}
9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	2038 self.temp = {}
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2039 self.subroutines[self.body].inline(self, [], pieces, otype, None)
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2040 pieces.append('\n\t}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2041 pieces.append('\n}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2042 body.append('\nstatic void unimplemented({pre}context *context, uint32_t target_cycle)'.format(pre = self.prefix))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2043 body.append('\n{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2044 if len(self.mainDispatch) == 1:
2592 8ef8b2e99f4f Fix regression in better unimplemented instruction error in CPU dsl Michael Pavone <pavone@retrodev.com> parents: 2591 diff changeset	2045 dispatch = self.resolveParam(list(self.mainDispatch)[0], None, {})
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2046 body.append(f'\n\tfatal_error("Unimplemented instruction: %X\\n", {dispatch});')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2047 else:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2048 body.append('\n\tfatal_error("Unimplemented instruction\\n");')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2049 body.append('\n}\n')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2050 elif self.dispatch == 'goto':
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	2051 body.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2052 body += self.nextInstruction(otype)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2053 pieces.append('\nunimplemented:')
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2054 if len(self.mainDispatch) == 1:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2055 dispatch = list(self.mainDispatch)[0]
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2056 body.append(f'\n\tfatal_error("Unimplemented instruction: %X\\n", {dispatch});')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2057 else:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2058 body.append('\n\tfatal_error("Unimplemented instruction\\n");')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2059 pieces.append('\n}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2060 return ''.join(body) + ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2061
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2062 def checkBool(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2063 if not name in self.booleans:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2064 raise Exception(name + ' is not a defined boolean flag')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2065 return self.booleans[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2066
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2067 def getTemp(self, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2068 if size in self.temp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2069 return ('', self.temp[size])
1742 6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1740 diff changeset	2070 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size);
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2071 return ('', self.temp[size])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2072
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2073 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2074 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2075 while keepGoing:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2076 keepGoing = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2077 try:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2078 if type(param) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2079 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2080 elif param.startswith('0x'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2081 param = int(param, 16)
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	2082 elif param.startswith('0b'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	2083 param = int(param, 2)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2084 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2085 param = int(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2086 except ValueError:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2087
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2088 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2089 if param in parent.regValues and allowConstant:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2090 return parent.regValues[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2091 maybeLocal = parent.resolveLocal(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2092 if maybeLocal:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2093 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2094 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2095 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2096 return maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2097 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2098 param = fieldVals[param]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	2099 fieldVals = {}
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	2100 keepGoing = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2101 elif param in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2102 param = self.meta[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2103 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2104 elif self.isReg(param):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2105 return self.resolveReg(param, parent, fieldVals, isdst)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2106 elif param in self.regs.pointers:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2107 return 'context->' + param
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2108 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2109 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2110 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2111 return param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2112
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2113 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2114 if not type(name) is str:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2115 return False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2116 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2117 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2118 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2119 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2120 return self.regs.isRegArray(begin)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2121 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2122 return self.regs.isReg(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2123
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2124 def resolveReg(self, name, parent, fieldVals, isDst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2125 begin,sep,end = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2126 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2127 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2128 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2129 if not self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2130 end = self.resolveParam(end, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2131 if not type(end) is int and self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2132 arrayName = self.regs.arrayMemberParent(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2133 end = self.regs.arrayMemberIndex(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2134 if arrayName != begin:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2135 end = 'context->{0}[{1}]'.format(arrayName, end)
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2136 if self.regs.isNamedArray(begin):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2137 regName = self.regs.arrayMemberName(begin, end)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2138 else:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2139 regName = '{0}.{1}'.format(begin, end)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2140 ret = 'context->{0}[{1}]'.format(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2141 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2142 regName = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2143 if self.regs.isRegArrayMember(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2144 arr,idx = self.regs.regToArray[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2145 ret = 'context->{0}[{1}]'.format(arr, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2146 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2147 ret = 'context->' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2148 if regName == self.flags.flagReg:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2149 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2150 self.needFlagDisperse = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2151 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2152 self.needFlagCoalesce = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2153 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2154 self.lastDst = regName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2155 return ret
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2156
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2157
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2158
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2159 def paramSize(self, name):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2160 if name in self.meta:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2161 return self.paramSize(self.meta[name])
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2162 for i in range(len(self.scopes) -1, -1, -1):
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2163 size = self.scopes[i].localSize(name)
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2164 if size:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2165 return size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2166 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2167 if sep and self.regs.isRegArray(begin):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2168 return self.regs.regArrays[begin][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2169 if self.regs.isReg(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2170 return self.regs.regs[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2171 return 32
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2172
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2173 def getLastSize(self):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2174 if self.lastSize:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2175 return self.lastSize
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2176 return self.paramSize(self.lastDst)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2177
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2178 def pushScope(self, scope):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2179 self.scopes.append(scope)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2180 self.currentScope = scope
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2181
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2182 def popScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2183 ret = self.scopes.pop()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2184 self.currentScope = self.scopes[-1] if self.scopes else None
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2185 return ret
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2186
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2187 def getRootScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2188 return self.scopes[0]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2189
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2190 def parse(args):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2191 f = args.source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2192 instructions = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2193 subroutines = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2194 registers = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2195 flags = None
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2196 declares = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2197 errors = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2198 info = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2199 line_num = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2200 cur_object = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2201 for line in f:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2202 line_num += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2203 line,_,comment = line.partition('#')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2204 if not line.strip():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2205 continue
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2206 if line[0].isspace():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2207 if not cur_object is None:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2208 sep = True
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2209 parts = []
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2210 while sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2211 before,sep,after = line.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2212 before = before.strip()
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2213 if before:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	2214 parts += [el.strip() for el in before.split(' ') if el.strip()]
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2215 if sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2216 #TODO: deal with escaped quotes
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2217 inside,sep,after = after.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2218 parts.append('"' + inside + '"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2219 line = after
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2220 if type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2221 cur_object[parts[0]] = parts[1:]
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2222 elif type(cur_object) is list:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2223 cur_object.append(' '.join(parts))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2224 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2225 cur_object = cur_object.processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2226
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2227 # if type(cur_object) is Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2228 # if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2229 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2230 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2231 # cur_object.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2232 # elif type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2233 # cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2234 # elif parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2235 # o = Switch(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2236 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2237 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2238 # elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2239 # o = If(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2240 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2241 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2242 # elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2243 # cur_object = cur_object.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2244 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2245 # cur_object.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2246 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2247 errors.append("Orphan instruction on line {0}".format(line_num))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2248 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2249 parts = line.split(' ')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2250 if len(parts) > 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2251 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2252 table,bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2253 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2254 bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2255 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2256 value = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2257 fields = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2258 curbit = len(bitpattern) - 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2259 for char in bitpattern:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2260 value <<= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2261 if char in ('0', '1'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2262 value \|= int(char)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2263 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2264 if char in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2265 fields[char] = (curbit, fields[char][1] + 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2266 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2267 fields[char] = (curbit, 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2268 curbit -= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2269 cur_object = Instruction(value, fields, name.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2270 instructions.setdefault(table, []).append(cur_object)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2271 elif line.strip() == 'regs':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2272 if registers is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2273 registers = Registers()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2274 cur_object = registers
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2275 elif line.strip() == 'info':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2276 cur_object = info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2277 elif line.strip() == 'flags':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2278 if flags is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2279 flags = Flags()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2280 cur_object = flags
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2281 elif line.strip() == 'declare':
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2282 cur_object = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2283 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2284 cur_object = SubRoutine(line.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2285 subroutines[cur_object.name] = cur_object
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2286 if errors:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2287 print(errors)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2288 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2289 p = Program(registers, instructions, subroutines, info, flags)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2290 p.dispatch = args.dispatch
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2291 p.declares = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2292 p.booleans['dynarec'] = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2293 p.booleans['interp'] = True
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2294 if args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2295 for define in args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2296 name,sep,val = define.partition('=')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2297 name = name.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2298 val = val.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2299 if sep:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2300 p.booleans[name] = bool(val)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2301 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2302 p.booleans[name] = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2303
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2304 if 'header' in info:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2305 print('#include "{0}"'.format(info['header'][0]))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2306 p.writeHeader('c', info['header'][0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2307 print('#include "util.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2308 print('#include <stdlib.h>')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2309 print(p.build('c'))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2310
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2311 def main(argv):
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2312 from argparse import ArgumentParser, FileType
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2313 argParser = ArgumentParser(description='CPU emulator DSL compiler')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2314 argParser.add_argument('source', type=FileType('r'))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2315 argParser.add_argument('-D', '--define', action='append')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2316 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2317 parse(argParser.parse_args(argv[1:]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2318
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2319 if __name__ == '__main__':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2320 from sys import argv
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2321 main(argv)

Mercurial > repos > blastem

annotate cpu_dsl.py @ 2593:b0a7b1f708cc