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annotate vdp.c @ 621:5196333b37a6

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Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
author Michael Pavone <pavone@retrodev.com>
date Mon, 16 Jun 2014 19:13:28 -0700
parents 1495179d6737
children b76d2a628ab9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*
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2 Copyright 2013 Michael Pavone
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "vdp.h"
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7 #include "blastem.h"
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8 #include <stdlib.h>
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9 #include <string.h>
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10 #include "render.h"
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11
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12 #define NTSC_ACTIVE 225
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13 #define PAL_ACTIVE 241
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14 #define BUF_BIT_PRIORITY 0x40
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15 #define MAP_BIT_PRIORITY 0x8000
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16 #define MAP_BIT_H_FLIP 0x800
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17 #define MAP_BIT_V_FLIP 0x1000
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18
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19 #define SCROLL_BUFFER_SIZE 32
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20 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
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21 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
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22
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23 #define MCLKS_SLOT_H40 16
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24 #define MCLKS_SLOT_H32 20
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25 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after
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26 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number
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27 #define HSYNC_SLOT_H40 21
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28 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332)
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29 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17)
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30 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32)
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31 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4)
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32 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5)
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33 #define FIFO_LATENCY 3
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34
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35 int32_t color_map[1 << 12];
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36 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
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37
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38 uint8_t debug_base[][3] = {
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39 {127, 127, 127}, //BG
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40 {0, 0, 127}, //A
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41 {127, 0, 0}, //Window
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42 {0, 127, 0}, //B
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43 {127, 0, 127} //Sprites
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44 };
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45
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46 uint8_t color_map_init_done;
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47
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48 void init_vdp_context(vdp_context * context)
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49 {
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50 memset(context, 0, sizeof(*context));
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51 context->vdpmem = malloc(VRAM_SIZE);
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52 memset(context->vdpmem, 0, VRAM_SIZE);
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53 /*
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54 */
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55 if (headless) {
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56 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (32 / 8));
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57 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (32 / 8));
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58 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (32 / 8));
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59 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (32 / 8));
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60 context->b32 = 1;
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61 } else {
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62 render_alloc_surfaces(context);
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63 context->b32 = render_depth() == 32;
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64 }
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65 context->framebuf = context->oddbuf;
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66 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
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67 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
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68 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
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69 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
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70 context->sprite_draws = MAX_DRAWS;
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71 context->fifo_write = 0;
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72 context->fifo_read = -1;
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73
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74 if (!color_map_init_done) {
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75 uint8_t b,g,r;
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76 for (uint16_t color = 0; color < (1 << 12); color++) {
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77 if (color & FBUF_SHADOW) {
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78 b = levels[(color >> 9) & 0x7];
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79 g = levels[(color >> 5) & 0x7];
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80 r = levels[(color >> 1) & 0x7];
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81 } else if(color & FBUF_HILIGHT) {
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82 b = levels[((color >> 9) & 0x7) + 7];
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83 g = levels[((color >> 5) & 0x7) + 7];
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84 r = levels[((color >> 1) & 0x7) + 7];
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85 } else {
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86 b = levels[(color >> 8) & 0xE];
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87 g = levels[(color >> 4) & 0xE];
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88 r = levels[color & 0xE];
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89 }
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90 color_map[color] = render_map_color(r, g, b);
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91 }
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92 color_map_init_done = 1;
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93 }
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94 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
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95 {
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96 uint8_t src = color & DBG_SRC_MASK;
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97 if (src > DBG_SRC_S) {
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98 context->debugcolors[color] = 0;
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99 } else {
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100 uint8_t r,g,b;
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101 b = debug_base[src][0];
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102 g = debug_base[src][1];
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103 r = debug_base[src][2];
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104 if (color & DBG_PRIORITY)
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105 {
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106 if (b) {
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107 b += 48;
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108 }
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109 if (g) {
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110 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
111 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
112 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
113 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
114 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
115 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
116 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
117 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
118 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
119 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
120 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
121 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
122 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
123 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
124 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
125 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
126 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
127 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
128 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
129 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
130 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
131 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
132 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
133 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
134 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
135 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
136
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
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parents: 454
diff changeset
137 int is_refresh(vdp_context * context, uint32_t slot)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
138 {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
139 if (context->latched_mode & BIT_H40) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
140 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210);
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
141 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy
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parents: 454
diff changeset
142 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
143 //These numbers are guesses based on H40 numbers
788ba843a731 Implement FIFO latency and improve DMA accuracy
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parents: 454
diff changeset
144 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152);
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
145 //The numbers below are the refresh slots during active display
788ba843a731 Implement FIFO latency and improve DMA accuracy
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parents: 454
diff changeset
146 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162);
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
147 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
148 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
149
21
72ce60cb1711 Sprites somewhat less broken
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parents: 20
diff changeset
150 void render_sprite_cells(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
151 {
21
72ce60cb1711 Sprites somewhat less broken
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parents: 20
diff changeset
152 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
153 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
154
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
155 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
156 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
157 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
158 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
159 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
160 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
161 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
162 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
163 }
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
164 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
165 context->cur_slot--;
143
e5487ef04619 Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents: 142
diff changeset
166 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
167 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
168 if (context->linebuf[x] && (context->vdpmem[address] >> 4)) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
169 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
170 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
172 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 x += dir;
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
174 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
175 if (context->linebuf[x] && (context->vdpmem[address] & 0xF)) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
176 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
177 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
179 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
180 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
181 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
182 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
183 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
184
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
185 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
186 {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
187 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
188 uint16_t current_index = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
189 uint8_t count = 0;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
190 do {
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
191 uint16_t address = current_index * 8 + sat_address;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
192 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
193 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
194 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
195 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF;
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
196 uint16_t link = context->vdpmem[address+3] & 0x7F;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
197 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
198 uint8_t pri = context->vdpmem[address + 4] >> 7;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
199 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5;
515
1495179d6737 Initial GDB remote debugging support. Lacks some features, but breakpoints and basic inspection of registers and memory work.
Mike Pavone <pavone@retrodev.com>
parents: 505
diff changeset
200 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
201 current_index = link;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
202 count++;
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
203 } while (current_index != 0 && count < 80);
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
204 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
205
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
206 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
207 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
208 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
209 printf("**Mode Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
210 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
211 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
212 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
213 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n",
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
214 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
215 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
216 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
217 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
218 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
219 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
220 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
221 printf("\n**Table Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
222 "02: %.2X | Scroll A Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
223 "03: %.2X | Window Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
224 "04: %.2X | Scroll B Name Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
225 "05: %.2X | Sprite Attribute Table: $%.4X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
226 "0D: %.2X | HScroll Data Table: $%.4X\n",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
227 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
228 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
229 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
230 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x7E : 0x7F)) << 9,
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
231 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
232 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
233 printf("\n**Misc Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
234 "07: %.2X | Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
235 "0A: %.2X | H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
236 "0F: %.2X | Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
237 "10: %.2X | Scroll A/B Size: %sx%s\n",
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
238 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
239 context->regs[REG_HINT], context->regs[REG_HINT],
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
240 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
241 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
242 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
243 printf("\n**DMA Group**\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
244 "13: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
245 "14: %.2X | DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
246 "15: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
247 "16: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
248 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
249 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
250 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
251 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
252 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
253 context->regs[REG_DMASRC_H],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
254 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
255 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
438
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
256 printf("\n**Internal Group**\n"
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
257 "Address: %X\n"
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
258 "CD: %X\n"
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
259 "Pending: %s\n",
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
260 context->address, context->cd, (context->flags & FLAG_PENDING) ? "true" : "false");
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
261
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
262 //TODO: Window Group, DMA Group
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
263 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
264
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 void scan_sprite_table(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 if (context->sprite_index && context->slot_counter) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
268 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
269 line &= 0xFF;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
270 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
271 uint8_t height_mult;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
272 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
273 line *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
274 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace
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parents: 337
diff changeset
275 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
276 }
36fbbced25c2 Initial work on interlace
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parents: 337
diff changeset
277 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace
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parents: 337
diff changeset
278 ymin = 256;
36fbbced25c2 Initial work on interlace
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parents: 337
diff changeset
279 height_mult = 16;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
280 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
281 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
282 ymin = 128;
36fbbced25c2 Initial work on interlace
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parents: 337
diff changeset
283 height_mult = 8;
36fbbced25c2 Initial work on interlace
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parents: 337
diff changeset
284 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
285 context->sprite_index &= 0x7F;
38
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
286 if (context->latched_mode & BIT_H40) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
287 if (context->sprite_index >= MAX_SPRITES_FRAME) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
288 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
289 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
290 }
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
291 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
292 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
293 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
294 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
295 //TODO: Read from SAT cache rather than from VRAM
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
296 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
297 uint16_t address = context->sprite_index * 8 + sat_address;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
298 line += ymin;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
299 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
300 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
301 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
302 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
303 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
306 context->sprite_info_list[context->slot_counter].y = y-ymin;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
307 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 context->sprite_index = context->vdpmem[address+3] & 0x7F;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309 if (context->sprite_index && context->slot_counter)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 address = context->sprite_index * 8 + sat_address;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
312 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
313 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
314 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
315 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
316 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
319 context->sprite_info_list[context->slot_counter].y = y-ymin;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 }
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
321 context->sprite_index = context->vdpmem[address+3] & 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
326 void read_sprite_x(uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
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parents:
diff changeset
327 {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
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parents: 32
diff changeset
328 if (context->cur_slot >= context->slot_counter) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
329 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
330 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
331 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
332 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
333 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
334 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
335 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
336 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
337 line *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
338 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
339 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
340 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
341 height *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
342 }
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
343 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
344 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1];
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
345 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
346 uint8_t row;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
347 if (tileinfo & MAP_BIT_V_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
348 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
349 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
350 row = line-context->sprite_info_list[context->cur_slot].y;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
351 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
352 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
353 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
354 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
355 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
356 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
357 }
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
358 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
359 if (x) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
360 context->flags |= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
361 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
362 context->flags |= FLAG_MASKED;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
363 }
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
364
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
365 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
366 int16_t i;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
367 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
368 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
369 --context->sprite_draws;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
370 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
371 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
372 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
373 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
374 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
375 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
376 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
377 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
378 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
379 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
380 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
381 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
382 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35
233c7737c152 Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents: 34
diff changeset
383 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
384 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
385 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
386 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
387 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
388 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
389 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
390 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
391 if (i < width) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
392 context->flags |= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
393 }
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
394 context->cur_slot--;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
396 context->flags |= FLAG_DOT_OFLOW;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
399 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
401 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
402 {
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
403 uint16_t addr = (address/2) & (CRAM_SIZE-1);
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
404 context->cram[addr] = value;
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
405 context->colors[addr] = color_map[value & 0xEEE];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
406 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
407 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT];
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
408 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
409
473
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
410 #define VRAM_READ 0 //0000
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
411 #define VRAM_WRITE 1 //0001
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
412 //2 would trigger register write 0010
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
413 #define CRAM_WRITE 3 //0011
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
414 #define VSRAM_READ 4 //0100
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
415 #define VSRAM_WRITE 5//0101
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
416 //6 would trigger regsiter write 0110
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
417 //7 is a mystery
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
418 #define CRAM_READ 8 //1000
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
419 //9 is also a mystery //1001
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
420 //A would trigger register write 1010
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
421 //B is a mystery 1011
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
422 #define VRAM_READ8 0xC //1100
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
423 //D is a mystery 1101
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
424 //E would trigger register write 1110
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
425 //F is a mystery 1111
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
426 #define DMA_START 0x20
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
427
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
428 void external_slot(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
429 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
430 fifo_entry * start = context->fifo + context->fifo_read;
474
e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents: 473
diff changeset
431 /*if (context->flags2 & FLAG2_READ_PENDING) {
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
432 context->flags2 &= ~FLAG2_READ_PENDING;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
433 context->flags |= FLAG_UNUSED_SLOT;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
434 return;
474
e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents: 473
diff changeset
435 }*/
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
436 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
437 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
438 {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
439 case VRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
440 if (start->partial) {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
441 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
442 context->vdpmem[start->address ^ 1] = start->partial == 2 ? start->value >> 8 : start->value;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
443 } else {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
444 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
445 context->vdpmem[start->address] = start->value >> 8;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
446 start->partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
447 //skip auto-increment and removal of entry from fifo
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
448 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
449 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
450 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
451 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
452 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
479
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
453 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
454 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
455 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
456 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
457 if (((start->address/2) & 63) < VSRAM_SIZE) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
458 //printf("VSRAM Write: %X to %X\n", start->value, context->address);
479
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
459 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
460 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
461
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
462 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
463 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
464 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
465 if (context->fifo_read == context->fifo_write) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
466 context->fifo_read = -1;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
467 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
468 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
469 context->flags |= FLAG_UNUSED_SLOT;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
470 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
471 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
472
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
473 void run_dma_src(vdp_context * context, uint32_t slot)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
474 {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
475 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
476 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
477 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
478 if (context->fifo_write == context->fifo_read) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
479 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
480 }
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
481 fifo_entry * cur = NULL;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
482 switch(context->regs[REG_DMASRC_H] & 0xC0)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
483 {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
484 //68K -> VDP
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
485 case 0:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
486 case 0x40:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
487 if (!slot || !is_refresh(context, slot-1)) {
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
488 cur = context->fifo + context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
489 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
490 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
491 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
492 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
493 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
494 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
495 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
496 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
497 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
498 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
499 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
500 //Copy
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
501 case 0xC0:
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
502 if (context->flags & FLAG_UNUSED_SLOT && context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
503 //TODO: Fix this to not use the FIFO at all once read-caching is properly implemented
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
504 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
505 cur = context->fifo + context->fifo_read;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
506 cur->cycle = context->cycles;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
507 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
508 cur->partial = 1;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
509 cur->value = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1] | (cur->value & 0xFF00);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
510 cur->cd = VRAM_WRITE;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
511 context->flags &= ~FLAG_UNUSED_SLOT;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
512 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
513 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
514 case 0x80:
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
515 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
516 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
517 cur = context->fifo + context->fifo_read;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
518 cur->cycle = context->cycles;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
519 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
520 cur->partial = 2;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
521 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
522 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
523 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
524
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
525 if (cur) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
526 context->regs[REG_DMASRC_L] += 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
527 if (!context->regs[REG_DMASRC_L]) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
528 context->regs[REG_DMASRC_M] += 1;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
529 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
530 context->address += context->regs[REG_AUTOINC];
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
531 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
532 context->regs[REG_DMALEN_H] = dma_len >> 8;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
533 context->regs[REG_DMALEN_L] = dma_len;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
534 if (!dma_len) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
535 //printf("DMA end at cycle %d\n", context->cycles);
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
536 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
537 context->cd &= 0xF;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
538 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
539 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
540 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
541
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
542 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
543 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
544
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
545 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
547 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
548 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
549 line *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
550 if (context->framebuf != context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
551 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
552 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
553 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
554 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
555 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
556 } else {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
557 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
558 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
559 vscroll_shift = 3;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
560 }
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
561 if (!vsram_off) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
562 uint16_t left_col, right_col;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
563 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
564 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
565 right_col = 42;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
566 } else {
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
567 left_col = 0;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
568 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
569 if (right_col) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
570 right_col += 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
571 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
572 }
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
573 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
574 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
575 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
576 bottom_line = context->double_res ? 481 : 241;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
577 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
578 top_line = 0;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
579 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
580 }
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
581 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
582 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
583 uint16_t line_offset, offset, mask;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
584 if (context->latched_mode & BIT_H40) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
585 address &= 0xF000;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
586 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
587 mask = 0x7F;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
588
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
589 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
590 address &= 0xF800;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
591 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
592 mask = 0x3F;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
593 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
594 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
595 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
596 mask |= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
597 }
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
598 offset = address + line_offset + (((column - 2) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
599 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
600 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
601 offset = address + line_offset + (((column - 1) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
602 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
603 context->v_offset = (line) & v_offset_mask;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
604 context->flags |= FLAG_WINDOW;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
605 return;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
606 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
607 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
608 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
609 uint16_t vscroll;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
610 switch(context->regs[REG_SCROLL] & 0x30)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
611 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
612 case 0:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
613 vscroll = 0xFF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
614 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
615 case 0x10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
616 vscroll = 0x1FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
617 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
618 case 0x20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
619 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
620 vscroll = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
621 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
622 case 0x30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
623 vscroll = 0x3FF;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
624 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
625 }
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
626 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
627 vscroll <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
628 vscroll |= 1;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
629 }
454
e9b6fe443bf2 Fix per-column scrolling bug
Mike Pavone <pavone@retrodev.com>
parents: 453
diff changeset
630 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? (column-2)&63 : 0) + vsram_off] + line);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
631 context->v_offset = vscroll & v_offset_mask;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
632 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
633 vscroll >>= vscroll_shift;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
634 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
635 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
636 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
637 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
638 case 0:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
639 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
640 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
641 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
642 case 0x1:
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
643 hscroll_mask = 0x3F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
644 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
645 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
646 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
647 //TODO: Verify this behavior
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
648 hscroll_mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
649 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
650 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
651 case 0x3:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
652 hscroll_mask = 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
653 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
654 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
655 }
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
656 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
657 for (int i = 0; i < 2; i++) {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
658 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
659 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
660 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
661 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
662 if (i) {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
663 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
664 } else {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
665 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
666 }
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
667 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
668 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
669
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
670 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
671 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
672 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
673 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
674
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
675 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
676 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
677 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
678 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
679
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
680 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
681 {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
682 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
683 uint8_t shift, add;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
684 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
685 address = ((col & 0x3FF) << 6);
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
686 shift = 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
687 add = context->framebuf != context->oddbuf ? 1 : 0;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
688 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
689 address = ((col & 0x7FF) << 5);
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
690 shift = 0;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
691 add = 0;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
692 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
693 if (col & MAP_BIT_V_FLIP) {
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
694 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
695 } else {
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
696 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
697 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
698 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
699 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
700 if (col & MAP_BIT_H_FLIP) {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
701 offset += 7;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
702 offset &= SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
703 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
704 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
705 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
706 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
707 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
708 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
709 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
710 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
711 offset &= SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
712 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
713 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
714 offset &= SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
715 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
716 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
717
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
718 void render_map_1(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
719 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
720 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
721 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
722
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
723 void render_map_2(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
724 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
725 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
726 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
727
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
728 void render_map_3(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
729 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
730 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
731 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
732
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
733 void render_map_output(uint32_t line, int32_t col, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
734 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
735 if (line >= 240) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
736 return;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
737 }
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
738 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
739 uint16_t *dst;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
740 uint32_t *dst32;
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
741 uint8_t *sprite_buf, *plane_a, *plane_b;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
742 int plane_a_off, plane_b_off;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
743 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
744 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
745 col-=2;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
746 if (context->b32) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
747 dst32 = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
748 dst32 += line * 320 + col * 8;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
749 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
750 dst = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
751 dst += line * 320 + col * 8;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
752 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
753 sprite_buf = context->linebuf + col * 8;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
754 uint8_t a_src, src;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
755 if (context->flags & FLAG_WINDOW) {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
756 plane_a_off = context->buf_a_off;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
757 a_src = DBG_SRC_W;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
758 } else {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
759 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
760 a_src = DBG_SRC_A;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
761 }
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
762 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
30
03f9bb57cc54 Small cleanup
Mike Pavone <pavone@retrodev.com>
parents: 29
diff changeset
763 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
764
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
765 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
766 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
767 uint8_t pixel;
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
768 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
769 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
770 uint32_t * colors = context->colors;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
771 src = 0;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
772 pixel = context->regs[REG_BG_COLOR];
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
773 src = DBG_SRC_BG;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
774 if (*plane_b & 0xF) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
775 pixel = *plane_b;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
776 src = DBG_SRC_B;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
777 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
778 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
779 pixel = *plane_a;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
780 src = DBG_SRC_A;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
781 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
782 if (*sprite_buf & 0xF) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
783 uint8_t sprite_color = *sprite_buf & 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
784 if (sprite_color == 0x3E) {
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
785 colors += CRAM_SIZE*2;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
786 src |= DBG_HILIGHT;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
787 } else if (sprite_color == 0x3F) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
788 colors += CRAM_SIZE;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
789 src |= DBG_SHADOW;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
790 } else if ((*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
791 pixel = *sprite_buf;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
792 src = DBG_SRC_S;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
793 if ((pixel & 0xF) == 0xE) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
794 src |= DBG_SHADOW;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
795 colors += CRAM_SIZE;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
796 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
797
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
798 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
799 } else if (!((*plane_a | *plane_b) & BUF_BIT_PRIORITY)) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
800 colors += CRAM_SIZE;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
801 src |= DBG_SHADOW;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
802 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
803 pixel &= 0x3F;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
804 uint32_t outpixel;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
805 if (context->debug) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
806 outpixel = context->debugcolors[src];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
807 } else {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
808 outpixel = colors[pixel];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
809 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
810 if (context->b32) {
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
811 *(dst32++) = outpixel;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
812 } else {
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
813 *(dst++) = outpixel;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
814 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
815 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
816 }
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
817 } else {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
818 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
819 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
820 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
821 uint8_t pixel = context->regs[REG_BG_COLOR];
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
822 src = DBG_SRC_BG;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
823 if (*plane_b & 0xF) {
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
824 pixel = *plane_b;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
825 src = DBG_SRC_B;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
826 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
827 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
828 pixel = *plane_a;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
829 src = DBG_SRC_A;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
830 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
831 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
832 pixel = *sprite_buf;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
833 src = DBG_SRC_S;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
834 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
835 uint32_t outpixel;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
836 if (context->debug) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
837 outpixel = context->debugcolors[src];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
838 } else {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
839 outpixel = context->colors[pixel & 0x3F];
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
840 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
841 if (context->b32) {
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
842 *(dst32++) = outpixel;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
843 } else {
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
844 *(dst++) = outpixel;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
845 }
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
846 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
847 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
848 }
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
849 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
850 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
851 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
852
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
853 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
854 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
855 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
856 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
857 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
858 external_slot(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
859 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
860 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
861 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
862 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
863 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
864 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
865 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
866 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
867 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
868 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
869 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
870 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
871 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
872 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
873 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
874 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
875 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
876 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
877 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
878
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
879 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
880 case startcyc:\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
881 read_map_scroll_a(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
882 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
883 case (startcyc+1):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
884 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
885 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
886 render_map_1(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
887 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
888 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
889 render_map_2(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
890 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
891 case (startcyc+4):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
892 read_map_scroll_b(column, line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
893 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
894 case (startcyc+5):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
895 read_sprite_x(line, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
896 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
897 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
898 render_map_3(context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
899 break;\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
900 case (startcyc+7):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
901 render_map_output(line, column, context);\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
902 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
903
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
904 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
905 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
906 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
907 uint32_t mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
908 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
909 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
910 //sprite render to line buffer starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
911 case 0:
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
912 context->cur_slot = MAX_DRAWS-1;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
913 memset(context->linebuf, 0, LINEBUF_SIZE);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
914 case 1:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
915 case 2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
916 case 3:
329
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
917 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
918 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
919 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
920 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
921 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
922 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
923 //sprite attribute table scan starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
924 case 4:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
925 render_sprite_cells( context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
926 context->sprite_index = 0x80;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
927 context->slot_counter = MAX_SPRITES_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
928 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
929 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
930 case 5:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
931 case 6:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
932 case 7:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
933 case 8:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
934 case 9:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
935 case 10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
936 case 11:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
937 case 12:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
938 case 13:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
939 case 14:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
940 case 15:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
941 case 16:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
942 case 17:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
943 case 18:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
944 case 19:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
945 case 20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
946 //!HSYNC asserted
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
947 case 21:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
948 case 22:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
949 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
950 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
951 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
952 case 23:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
953 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
954 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
955 case 24:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
956 case 25:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
957 case 26:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
958 case 27:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
959 case 28:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
960 case 29:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
961 case 30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
962 case 31:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
963 case 32:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
964 case 33:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
965 case 34:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
966 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
967 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
968 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
969 case 35:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
970 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
971 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
972 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
973 mask |= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
974 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
975 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
976 mask |= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
977 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
978 line &= mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
979 address += line * 4;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
980 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
981 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
982 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
983 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
984 case 36:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
985 //!HSYNC high
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
986 case 37:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
987 case 38:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
988 case 39:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
989 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
990 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
991 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
992 case 40:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
993 read_map_scroll_a(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
994 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
995 case 41:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
996 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
997 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
998 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
999 case 42:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1000 render_map_1(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1001 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1002 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1003 case 43:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1004 render_map_2(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1005 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1006 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1007 case 44:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1008 read_map_scroll_b(0, line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1009 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1010 case 45:
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
1011 render_sprite_cells(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1012 scan_sprite_table(line, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1013 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1014 case 46:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1015 render_map_3(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1016 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1017 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 case 47:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1019 render_map_output(line, 0, context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1020 scan_sprite_table(line, context);//Just a guess
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1021 //reverse context slot counter so it counts the number of sprite slots
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1022 //filled rather than the number of available slots
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
1023 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
1024 context->cur_slot = MAX_SPRITES_LINE-1;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1025 context->sprite_draws = MAX_DRAWS;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
1026 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1027 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1028 COLUMN_RENDER_BLOCK(2, 48)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1029 COLUMN_RENDER_BLOCK(4, 56)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1030 COLUMN_RENDER_BLOCK(6, 64)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1031 COLUMN_RENDER_BLOCK_REFRESH(8, 72)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1032 COLUMN_RENDER_BLOCK(10, 80)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1033 COLUMN_RENDER_BLOCK(12, 88)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1034 COLUMN_RENDER_BLOCK(14, 96)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1035 COLUMN_RENDER_BLOCK_REFRESH(16, 104)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1036 COLUMN_RENDER_BLOCK(18, 112)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1037 COLUMN_RENDER_BLOCK(20, 120)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1038 COLUMN_RENDER_BLOCK(22, 128)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1039 COLUMN_RENDER_BLOCK_REFRESH(24, 136)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1040 COLUMN_RENDER_BLOCK(26, 144)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1041 COLUMN_RENDER_BLOCK(28, 152)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1042 COLUMN_RENDER_BLOCK(30, 160)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1043 COLUMN_RENDER_BLOCK_REFRESH(32, 168)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1044 COLUMN_RENDER_BLOCK(34, 176)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1045 COLUMN_RENDER_BLOCK(36, 184)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1046 COLUMN_RENDER_BLOCK(38, 192)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1047 COLUMN_RENDER_BLOCK_REFRESH(40, 200)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1048 case 208:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1049 case 209:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1050 external_slot(context);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1051 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1052 default:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1053 //leftovers from HSYNC clock change nonsense
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1054 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1055 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1056 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1057
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 {
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1060 uint16_t address;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1061 uint32_t mask;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 switch(linecyc)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1064 //sprite render to line buffer starts
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1065 case 0:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1066 context->cur_slot = MAX_DRAWS_H32-1;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1067 memset(context->linebuf, 0, LINEBUF_SIZE);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1068 case 1:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1069 case 2:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1070 case 3:
329
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1071 if (line == 0xFF) {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1072 external_slot(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1073 } else {
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1074 render_sprite_cells(context);
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1075 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1076 break;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1077 //sprite attribute table scan starts
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1078 case 4:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1079 render_sprite_cells( context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1080 context->sprite_index = 0x80;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1081 context->slot_counter = MAX_SPRITES_LINE_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1082 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1083 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1084 case 5:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1085 case 6:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1086 case 7:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1087 case 8:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1088 case 9:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1089 case 10:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1090 case 11:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1091 case 12:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 case 13:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1093 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1094 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1095 case 14:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1096 external_slot(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1097 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1098 case 15:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1099 case 16:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1100 case 17:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1101 case 18:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1102 case 19:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1103 //HSYNC start
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1104 case 20:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1105 case 21:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1106 case 22:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1107 case 23:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1108 case 24:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1109 case 25:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1110 case 26:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1111 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1112 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1113 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1114 case 27:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1115 external_slot(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1116 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1117 case 28:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1118 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1119 mask = 0;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1120 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1121 mask |= 0xF8;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1122 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1123 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1124 mask |= 0x7;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1125 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1126 line &= mask;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1127 address += line * 4;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1128 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1129 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1130 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1131 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1132 case 29:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1133 case 30:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1134 case 31:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1135 case 32:
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1136 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1137 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1138 break;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1139 //!HSYNC high
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1140 case 33:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1141 read_map_scroll_a(0, line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1142 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1143 case 34:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1144 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1145 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1146 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1147 case 35:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1148 render_map_1(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1149 scan_sprite_table(line, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1150 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1151 case 36:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1152 render_map_2(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1153 scan_sprite_table(line, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1154 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1155 case 37:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1156 read_map_scroll_b(0, line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1157 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1158 case 38:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1159 render_sprite_cells(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1160 scan_sprite_table(line, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1161 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1162 case 39:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1163 render_map_3(context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1164 scan_sprite_table(line, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1165 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1166 case 40:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1167 render_map_output(line, 0, context);
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1168 scan_sprite_table(line, context);//Just a guess
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1169 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1170 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1171 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1172 context->cur_slot = MAX_SPRITES_LINE_H32-1;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1173 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1174 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1175 break;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1176 COLUMN_RENDER_BLOCK(2, 41)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1177 COLUMN_RENDER_BLOCK(4, 49)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1178 COLUMN_RENDER_BLOCK(6, 57)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1179 COLUMN_RENDER_BLOCK_REFRESH(8, 65)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1180 COLUMN_RENDER_BLOCK(10, 73)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1181 COLUMN_RENDER_BLOCK(12, 81)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1182 COLUMN_RENDER_BLOCK(14, 89)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1183 COLUMN_RENDER_BLOCK_REFRESH(16, 97)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1184 COLUMN_RENDER_BLOCK(18, 105)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1185 COLUMN_RENDER_BLOCK(20, 113)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1186 COLUMN_RENDER_BLOCK(22, 121)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1187 COLUMN_RENDER_BLOCK_REFRESH(24, 129)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1188 COLUMN_RENDER_BLOCK(26, 137)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1189 COLUMN_RENDER_BLOCK(28, 145)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1190 COLUMN_RENDER_BLOCK(30, 153)
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1191 COLUMN_RENDER_BLOCK_REFRESH(32, 161)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1192 case 169:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1193 case 170:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
1194 external_slot(context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1195 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1196 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1197 }
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1198
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1199 void vdp_h40_line(uint32_t line, vdp_context * context)
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1200 {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1201 context->cur_slot = MAX_DRAWS-1;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1202 memset(context->linebuf, 0, LINEBUF_SIZE);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1203 if (line == 0xFF) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1204 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1205 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1206 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1207 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1208 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1209 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1210 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1211 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1212 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1213 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1214 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1215 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1216 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1217 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1218 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1219 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1220 for (int i = 0; i < 19; i++)
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1221 {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1222 scan_sprite_table(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1223 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1224 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1225 for (int i = 0; i < 21; i++)
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1226 {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1227 scan_sprite_table(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1228 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1229 //reverse context slot counter so it counts the number of sprite slots
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1230 //filled rather than the number of available slots
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1231 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1232 context->cur_slot = MAX_SPRITES_LINE-1;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1233 context->sprite_draws = MAX_DRAWS;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1234 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1235 for (int column = 2; column < 42; column += 8)
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1236 {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1237 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1238 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1239 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1240 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1241 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1242
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1243 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1244 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1245 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1246 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1247 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1248
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1249 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1250 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1251 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1252 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1253 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1254
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1255 read_sprite_x(line, context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1256 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1257 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1258 if (context->flags & FLAG_DMA_RUN) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1259 run_dma_src(context, 0);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1260 }
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1261 external_slot(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1262 return;
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1263 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1264
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1265 render_sprite_cells(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1266 render_sprite_cells(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1267 render_sprite_cells(context);
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1268 render_sprite_cells(context);
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1269 context->sprite_index = 0x80;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1270 context->slot_counter = MAX_SPRITES_LINE;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1271 for (int i = 0; i < 19; i++)
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1272 {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1273 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1274 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1275 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1276 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1277 for (int i = 0; i < 11; i++)
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1278 {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1279 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1280 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1281 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1282 uint16_t address;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1283 uint32_t mask;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1284 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1285 mask = 0;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1286 if (context->regs[REG_MODE_3] & 0x2) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1287 mask |= 0xF8;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1288 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1289 if (context->regs[REG_MODE_3] & 0x1) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1290 mask |= 0x7;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1291 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1292 address += (line & mask) * 4;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1293 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1294 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1295 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1296 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1297 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1298 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1299 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1300 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1301 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1302 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1303
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1304 read_map_scroll_a(0, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1305 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1306 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1307 render_map_1(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1308 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1309 render_map_2(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1310 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1311 read_map_scroll_b(0, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1312 render_sprite_cells(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1313 scan_sprite_table(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1314 render_map_3(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1315 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1316 render_map_output(line, 0, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1317 scan_sprite_table(line, context);//Just a guess
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1318 //reverse context slot counter so it counts the number of sprite slots
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1319 //filled rather than the number of available slots
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1320 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1321 context->cur_slot = MAX_SPRITES_LINE-1;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1322 context->sprite_draws = MAX_DRAWS;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1323 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1324 for (int column = 2; column < 42; column += 2)
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1325 {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1326 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1327 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1328 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1329 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1330 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1331 render_map_1(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1332 render_map_2(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1333 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1334 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1335 render_map_3(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1336 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1337
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1338 column += 2;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1339 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1340 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1341 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1342 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1343 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1344 render_map_1(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1345 render_map_2(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1346 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1347 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1348 render_map_3(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1349 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1350
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1351 column += 2;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1352 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1353 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1354 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1355 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1356 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1357 render_map_1(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1358 render_map_2(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1359 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1360 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1361 render_map_3(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1362 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1363
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1364 column += 2;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1365 read_map_scroll_a(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1366 render_map_1(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1367 render_map_2(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1368 read_map_scroll_b(column, line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1369 read_sprite_x(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1370 render_map_3(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1371 render_map_output(line, column, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1372 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1373 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1374 if (context->flags & FLAG_DMA_RUN) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1375 run_dma_src(context, 0);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1376 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1377 external_slot(context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1378 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1379
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1380 void latch_mode(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1381 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1382 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1383 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1384
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1385 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1386 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1387 if (line > 0) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1388 line -= 1;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1389 int starti = -1;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1390 if (context->latched_mode & BIT_H40) {
462
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1391 if (slot >= 55 && slot < 210) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1392 uint32_t x = (slot-55)*2;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1393 starti = line * 320 + x;
462
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1394 } else if (slot < 5) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1395 uint32_t x = (slot + 155)*2;
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1396 starti = (line-1)*320 + x;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1397 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1398 } else {
462
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1399 if (slot >= 48 && slot < 171) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1400 uint32_t x = (slot-48)*2;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1401 starti = line * 320 + x;
462
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1402 } else if (slot < 5) {
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1403 uint32_t x = (slot + 123)*2;
5677c053edd6 Fix timing of backdrop rendering when the display is turned off
Mike Pavone <pavone@retrodev.com>
parents: 461
diff changeset
1404 starti = (line-1)*320 + x;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1405 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1406 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1407 if (starti >= 0) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1408 if (context->b32) {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1409 uint32_t color = context->colors[context->regs[REG_BG_COLOR]];
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1410 uint32_t * start = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1411 start += starti;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1412 for (int i = 0; i < 2; i++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1413 *(start++) = color;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1414 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1415 } else {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1416 uint16_t color = context->colors[context->regs[REG_BG_COLOR]];
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1417 uint16_t * start = context->framebuf;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1418 start += starti;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1419 for (int i = 0; i < 2; i++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1420 *(start++) = color;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1421 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1422 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1423 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1424 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1425 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1426
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1427 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1428 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1429 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1430 {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1431 context->flags &= ~FLAG_UNUSED_SLOT;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1432 uint32_t line = context->cycles / MCLKS_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1433 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
334
4c91470e1a53 Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents: 333
diff changeset
1434 if (!context->cycles) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1435 latch_mode(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1436 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1437 uint32_t linecyc = context->cycles % MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1438 if (linecyc == 0) {
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
1439 context->latched_mode &= ~0x81;
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
1440 context->latched_mode |= context->regs[REG_MODE_4] & 0x81;
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
1441 if (line < 1 || line >= active_lines) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1442 context->hint_counter = context->regs[REG_HINT];
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1443 } else if (context->hint_counter) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1444 context->hint_counter--;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1445 } else {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1446 context->flags2 |= FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1447 context->hint_counter = context->regs[REG_HINT];
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1448 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1449 } else if(line == active_lines) {
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1450 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1451 if (linecyc == intcyc) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1452 context->flags2 |= FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1453 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1454 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1455 uint32_t inccycles, slot;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1456 if (context->latched_mode & BIT_H40){
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1457 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1458 slot = linecyc/MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1459 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1460 } else if(linecyc < MCLK_WEIRD_END) {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1461 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1462 {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1463 case 0:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1464 inccycles = 19;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1465 slot = 0;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1466 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1467 case 19:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1468 slot = 1;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1469 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1470 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1471 case 39:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1472 slot = 2;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1473 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1474 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1475 case 59:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1476 slot = 3;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1477 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1478 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1479 case 79:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1480 slot = 4;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1481 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1482 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1483 case 97:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1484 slot = 5;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1485 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1486 break;
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1487 case 117:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1488 slot = 6;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1489 inccycles = 20;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1490 break;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1491 case 137:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1492 slot = 7;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1493 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1494 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1495 case 157:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1496 slot = 8;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1497 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1498 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1499 case 175:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1500 slot = 9;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1501 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1502 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1503 case 195:
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1504 slot = 10;
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1505 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1506 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1507 case 215:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1508 slot = 11;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1509 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1510 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1511 case 235:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1512 slot = 12;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1513 inccycles = 18;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1514 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1515 case 253:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1516 slot = 13;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1517 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1518 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1519 case 273:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1520 slot = 14;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1521 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1522 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1523 case 293:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1524 slot = 15;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1525 inccycles = 20;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1526 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1527 case 313:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1528 slot = 16;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1529 inccycles = 19;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1530 break;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1531 default:
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1532 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1533 exit(1);
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1534 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1535 slot += HSYNC_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1536 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1537 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1538 inccycles = MCLKS_SLOT_H40;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1539 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1540 } else {
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1541 inccycles = MCLKS_SLOT_H32;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1542 slot = linecyc/MCLKS_SLOT_H32;
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1543 }
329
fd5f6577db9b Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents: 328
diff changeset
1544 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) {
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1545 //first sort-of active line is treated as 255 internally
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
1546 //it's used for gathering sprite info for line
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1547 line = (line - 1) & 0xFF;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
1548
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1549 //Convert to slot number
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1550 if (context->latched_mode & BIT_H40){
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1551 if (!slot && line != (active_lines-1) && (target_cycles - context->cycles) >= MCLKS_LINE) {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1552 vdp_h40_line(line, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1553 inccycles = MCLKS_LINE;
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1554 } else {
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1555 vdp_h40(line, slot, context);
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
1556 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1557 } else {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1558 vdp_h32(line, slot, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1559 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1560 } else {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1561 if (!is_refresh(context, slot)) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1562 external_slot(context);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1563 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1564 if (line < active_lines) {
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1565 check_render_bg(context, line, slot);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1566 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1567 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1568 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, slot)) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1569 run_dma_src(context, slot);
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1570 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
1571 context->cycles += inccycles;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1572 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1573 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1574
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1575 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1576 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1577 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1578 vdp_run_context(context, target_cycles);
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1579 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1580 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1581
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1582 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1583 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1584 for(;;) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1585 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1586 if (!dmalen) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1587 dmalen = 0x10000;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1588 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1589 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1590 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1591 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1592 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1593 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1594 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1595 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1596 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1597 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1598 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1599 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1600 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1601 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1602 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1603 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1604 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1605 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1606 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1607
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1608 int vdp_control_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1609 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1610 //printf("control port write: %X at %d\n", value, context->cycles);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1611 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1612 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1613 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1614 if (context->flags & FLAG_PENDING) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1615 context->address = (context->address & 0x3FFF) | (value << 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1616 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1617 context->flags &= ~FLAG_PENDING;
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
1618 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1619 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1620 //
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1621 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1622 //DMA copy or 68K -> VDP, transfer starts immediately
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1623 context->flags |= FLAG_DMA_RUN;
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
1624 context->dma_cd = context->cd;
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
1625 //printf("DMA start at cycle %d\n", context->cycles);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1626 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1627 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1628 return 1;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1629 } else {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1630 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1631 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1632 } else {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
1633 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1634 }
63
a6dd5b7a971b Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents: 58
diff changeset
1635 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1636 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1637 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1638 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1639 uint8_t reg = (value >> 8) & 0x1F;
475
50e0cb475294 Don't allow register writes to regs above when in Mode 4
Mike Pavone <pavone@retrodev.com>
parents: 474
diff changeset
1640 if (reg < (context->regs[REG_MODE_2] & BIT_MODE_5 ? VDP_REGS : 0xA)) {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
1641 //printf("register %d set to %X\n", reg, value & 0xFF);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
1642 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
1643 context->hv_latch = vdp_hv_counter_read(context);
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
1644 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1645 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1646 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1647 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1648 context->regs[reg] = value;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1649 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1650 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
1651 if (!context->double_res) {
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
1652 context->framebuf = context->oddbuf;
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
1653 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1654 }
476
5d7bc113653b Clear the low 2 bits of CD when a register is written to
Mike Pavone <pavone@retrodev.com>
parents: 475
diff changeset
1655 context->cd &= 0x3C;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1656 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1657 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1658 context->flags |= FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1659 context->address = (context->address &0xC000) | (value & 0x3FFF);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1660 context->cd = (context->cd &0x3C) | (value >> 14);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1661 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1662 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1663 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1664 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1665
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1666 int vdp_data_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1667 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1668 //printf("data port write: %X at %d\n", value, context->cycles);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1669 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1670 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1671 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1672 context->flags &= ~FLAG_PENDING;
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
1673 /*if (context->fifo_cur == context->fifo_end) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1674 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
1675 }*/
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1676 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1677 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1678 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1679 while (context->fifo_write == context->fifo_read) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1680 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1681 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1682 fifo_entry * cur = context->fifo + context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1683 cur->cycle = context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1684 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1685 cur->value = value;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1686 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1687 context->flags |= FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1688 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1689 cur->cd = context->cd;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1690 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1691 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1692 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1693 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1694 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1695 context->address += context->regs[REG_AUTOINC];
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1696 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1697 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1698
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1699 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1700 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1701 //TODO: implement test register
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1702 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1703
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1704 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1705 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1706 context->flags &= ~FLAG_PENDING;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1707 uint16_t value = 0x3400;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1708 if (context->fifo_read < 0) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1709 value |= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1710 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1711 if (context->fifo_read == context->fifo_write) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1712 value |= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1713 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1714 if (context->flags2 & FLAG2_VINT_PENDING) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1715 value |= 0x80;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1716 }
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1717 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1718 value |= 0x40;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1719 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1720 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1721 value |= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1722 //TODO: Test when this is actually cleared
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1723 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
1724 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1725 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1726 value |= 0x10;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1727 }
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1728 uint32_t line= context->cycles / MCLKS_LINE;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1729 uint32_t linecyc = context->cycles % MCLKS_LINE;
481
1f3450d1129f Set VBLANK flag in status register when display is disabled
Mike Pavone <pavone@retrodev.com>
parents: 480
diff changeset
1730 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE) || !(context->regs[REG_MODE_2] & BIT_DISP_EN)) {
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1731 value |= 0x8;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1732 }
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1733 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) {
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1734 value |= 0x4;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
1735 }
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
1736 if (context->flags & FLAG_DMA_RUN) {
141
576f55711d8d Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
1737 value |= 0x2;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1738 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1739 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1740 value |= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1741 }
459
c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1742 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1743 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1744 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1745
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1746 #define CRAM_BITS 0xEEE
474
e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents: 473
diff changeset
1747 #define VSRAM_BITS 0x7FF
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1748 #define VSRAM_DIRTY_BITS 0xF800
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1749
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1750 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1751 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1752 context->flags &= ~FLAG_PENDING;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1753 if (context->cd & 1) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1754 return 0;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1755 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1756 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1757 context->flags &= ~FLAG_UNUSED_SLOT;
474
e128e55710bd Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Mike Pavone <pavone@retrodev.com>
parents: 473
diff changeset
1758 //context->flags2 |= FLAG2_READ_PENDING;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1759 while (!(context->flags & FLAG_UNUSED_SLOT)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1760 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1761 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1762 uint16_t value = 0;
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
1763 switch (context->cd & 0xF)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1764 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1765 case VRAM_READ:
472
93dc0382fd70 Fix VSRAM reads
Mike Pavone <pavone@retrodev.com>
parents: 471
diff changeset
1766 value = context->vdpmem[context->address & 0xFFFE] << 8;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1767 context->flags &= ~FLAG_UNUSED_SLOT;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1768 context->flags2 |= FLAG2_READ_PENDING;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1769 while (!(context->flags & FLAG_UNUSED_SLOT)) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1770 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1771 }
472
93dc0382fd70 Fix VSRAM reads
Mike Pavone <pavone@retrodev.com>
parents: 471
diff changeset
1772 value |= context->vdpmem[context->address | 1];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1773 break;
473
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
1774 case VRAM_READ8:
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
1775 value = context->vdpmem[context->address ^ 1];
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
1776 value |= context->fifo[context->fifo_write].value & 0xFF00;
1358045c0bdd Implement undocumented 8-bit VRAM read
Mike Pavone <pavone@retrodev.com>
parents: 472
diff changeset
1777 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1778 case CRAM_READ:
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1779 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1780 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1781 break;
479
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1782 case VSRAM_READ: {
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1783 uint16_t address = (context->address /2) & 63;
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1784 if (address >= VSRAM_SIZE) {
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1785 address = 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1786 }
479
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1787 value = context->vsram[address] & VSRAM_BITS;
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1788 value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1789 break;
479
863e868752cf Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Mike Pavone <pavone@retrodev.com>
parents: 478
diff changeset
1790 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1791 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1792 context->address += context->regs[REG_AUTOINC];
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1793 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1794 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1795
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1796 uint16_t vdp_hv_counter_read(vdp_context * context)
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1797 {
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
1798 if (context->regs[REG_MODE_1] & BIT_HVC_LATCH) {
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
1799 return context->hv_latch;
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
1800 }
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1801 uint32_t line= context->cycles / MCLKS_LINE;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1802 if (!line) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1803 line = 0xFF;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1804 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1805 line--;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1806 if (line > 0xEA) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1807 line = (line + 0xFA) & 0xFF;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1808 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1809 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1810 uint32_t linecyc = context->cycles % MCLKS_LINE;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1811 if (context->latched_mode & BIT_H40) {
332
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1812 uint32_t slot;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1813 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1814 slot = linecyc/MCLKS_SLOT_H40;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1815 } else if(linecyc < MCLK_WEIRD_END) {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1816 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40))
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1817 {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1818 case 0:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1819 slot = 0;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1820 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1821 case 19:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1822 slot = 1;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1823 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1824 case 39:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1825 slot = 2;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1826 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1827 case 59:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1828 slot = 2;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1829 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1830 case 79:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1831 slot = 3;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1832 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1833 case 97:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1834 slot = 4;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1835 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1836 case 117:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1837 slot = 5;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1838 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1839 case 137:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1840 slot = 6;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1841 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1842 case 157:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1843 slot = 7;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1844 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1845 case 175:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1846 slot = 8;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1847 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1848 case 195:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1849 slot = 9;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1850 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1851 case 215:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1852 slot = 11;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1853 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1854 case 235:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1855 slot = 12;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1856 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1857 case 253:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1858 slot = 13;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1859 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1860 case 273:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1861 slot = 14;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1862 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1863 case 293:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1864 slot = 15;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1865 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1866 case 313:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1867 slot = 16;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1868 break;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1869 default:
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1870 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40));
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1871 exit(1);
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1872 }
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1873 slot += HSYNC_SLOT_H40;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1874 } else {
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1875 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END;
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1876 }
671a5be51522 Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents: 331
diff changeset
1877 linecyc = slot * 2;
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1878 if (linecyc >= 86) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1879 linecyc -= 86;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1880 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1881 linecyc += 334;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1882 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1883 if (linecyc > 0x16C) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1884 linecyc += 92;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1885 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1886 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1887 linecyc /= 10;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1888 if (linecyc >= 74) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1889 linecyc -= 74;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1890 } else {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1891 linecyc += 268;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1892 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1893 if (linecyc > 0x127) {
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1894 linecyc += 170;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1895 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1896 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1897 linecyc &= 0xFF;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1898 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1899 line <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1900 if (line & 0x100) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1901 line |= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1902 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1903 }
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1904 return (line << 8) | linecyc;
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1905 }
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 135
diff changeset
1906
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1907 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1908 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1909 //TODO: Find out what actually gets returned here
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1910 return 0xFFFF;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1911 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1912
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1913 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1914 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1915 context->cycles -= deduction;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1916 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1917 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1918 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1919 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1920 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1921 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1922 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1923 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1924 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1925 } while(idx != context->fifo_write);
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1926 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1927 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
1928
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1929 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1930 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1931 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1932 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1933 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1934 if (context->flags2 & FLAG2_HINT_PENDING) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1935 return context->cycles;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1936 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1937 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1938 uint32_t line = context->cycles / MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1939 if (line >= active_lines) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1940 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1941 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1942 uint32_t linecyc = context->cycles % MCLKS_LINE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1943 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1944 return hcycle;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1945 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1946
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1947 uint32_t vdp_next_vint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1948 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
1949 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1950 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1951 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1952 if (context->flags2 & FLAG2_VINT_PENDING) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1953 return context->cycles;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1954 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1955 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1956 uint32_t vcycle = MCLKS_LINE * active_lines;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1957 if (context->latched_mode & BIT_H40) {
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1958 vcycle += VINT_CYCLE_H40;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1959 } else {
331
de17e0352f27 Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents: 330
diff changeset
1960 vcycle += VINT_CYCLE_H32;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1961 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1962 if (vcycle < context->cycles) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1963 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1964 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1965 return vcycle;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1966 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1967
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1968 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1969 {
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1970 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1971 uint32_t vcycle = MCLKS_LINE * active_lines;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1972 if (context->latched_mode & BIT_H40) {
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1973 vcycle += VINT_CYCLE_H40;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1974 } else {
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1975 vcycle += VINT_CYCLE_H32;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1976 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1977 return vcycle;
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1978 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
1979
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1980 void vdp_int_ack(vdp_context * context, uint16_t int_num)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1981 {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1982 if (int_num == 6) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1983 context->flags2 &= ~FLAG2_VINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1984 } else if(int_num ==4) {
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1985 context->flags2 &= ~FLAG2_HINT_PENDING;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1986 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1987 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
1988